CN109166807A - The manufacturing method of novel fan-out package structure - Google Patents
The manufacturing method of novel fan-out package structure Download PDFInfo
- Publication number
- CN109166807A CN109166807A CN201810816552.8A CN201810816552A CN109166807A CN 109166807 A CN109166807 A CN 109166807A CN 201810816552 A CN201810816552 A CN 201810816552A CN 109166807 A CN109166807 A CN 109166807A
- Authority
- CN
- China
- Prior art keywords
- chip
- insulating materials
- convex block
- package structure
- copper post
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Abstract
The present invention relates to a kind of manufacturing methods of novel fan-out package structure, the described method comprises the following steps: Step 1: taking a substrate support plate；Step 2: substrate carrier plate surface presses one layer of adhesive film；Step 3: wafer is cut into single chip by pasting chip, chip has convex block or copper post, the pasting chip on the adhesive film of substrate carrier plate surface；Step 4: fill insulant fill insulant between chip and chip by the way of pressing insulating material membrane, insulating materials film surface is provided with one layer of PET film, so that convex block or copper post is penetrated insulating material membrane after pressing, into PET film layer, solidifies insulating material membrane by heating；Step 5: the PET film on removal insulating materials surface, makes convex block or copper post expose insulating materials；Step 6: being thinned；Step 7: rerouting；Step 8: removal substrate support plate；Step 9: excision forming.Chip surrounding of the present invention is insulating materials, and homogenous material is not in cutting layering, can increase the high reliability of product.
Description
Technical field
The present invention relates to a kind of manufacturing methods of novel fan-out package structure, belong to technical field of semiconductor encapsulation.
Background technique
With the development of semiconductor technology and the driving of consumer electronics market, encapsulation technology to lighter, thinner, volume more
Direction small, that electric heating property is more excellent is developed.Chip package process is changed from chip package one by one to wafer level packaging, and wafer
Grade chip package (WLP) has many advantages, such as high density, small in size, high reliablity, excellent electrical properties, is increasingly becoming in market at first
Into most important encapsulation, WLP has two kinds of techniques of Fan in and Fan out at present, and wherein standard type Fan-out WLP is in wafer
On rerouted, cut again later, package size after the completion is bigger than the size of chip, chip front side convex block
(bumping) or copper post (copper pillar) is used as line, and entire chip makes on disk, and disk utilization rate is low, substantially
All be it is exposed outside, without any material protect chip, there are security risks.
Current Fan-out WLP encapsulating structure is as shown in Figure 1, its technique has the following disadvantages and defect:
1, fan-out is rerouted in disk surfaces, greatly reduces the utilization rate of disk；
2, disk material is hard, will appear stress concentration when being cut into single from disk, chipping easily occurs, influence appearance；
3, disk surfaces have PI, easily lamination occur in two kinds of material inspections when being cut into single, reduce the reliable of product
Property；
4, the thermal expansion coefficient of silicon chip and pcb board has apparent difference, in Thermal Cycling, due to the heat of the two
Mismatch can cause strain and stress to soldered ball, influence the reliability of product；
5, easily there are warpage issues to full wafer wafer level packaging in the Fan-in WLP of standard；
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of novel fan-out package structure for the above-mentioned prior art
Manufacturing method, it to substrate surface paste one layer of adhesive film, the pasting chip on adhesive film, chip have convex block or copper post, absolutely
Edge material is filled by the way of pressing insulating material membrane, and insulating material membrane front has the PET film of super thick, to realize convex block
Or copper post penetrates insulating material membrane, into PET film layer, then removes PET film, exposes convex block or copper post；By mechanically or chemically
Mode flush convex block or copper post with insulating film, then carry out RDL wiring, be cut into single after removing substrate, chip surrounding is
Insulating materials, homogenous material are not in cutting layering, increase the high reliability of product.
The present invention solves the above problems used technical solution are as follows: a kind of manufacturer of novel fan-out package structure
Method, it is characterised in that the described method comprises the following steps:
Step 1: taking a substrate support plate；
Step 2: substrate carrier plate surface presses one layer of adhesive film；
Step 3: pasting chip
Wafer is cut into single chip, chip has convex block or copper post, mounts on the adhesive film of substrate carrier plate surface
Chip；
Step 4: fill insulant
Fill insulant, insulating materials film surface are set between chip and chip by the way of pressing insulating material membrane
It is equipped with one layer of PET film, convex block or copper post is made to penetrate insulating material membrane after pressing, into PET film layer, insulating materials is made by heating
Film solidification；
Step 5: the PET film on removal insulating materials surface, makes convex block or copper post expose insulating materials；
Step 6: being thinned
Step 7: rerouting
Step 8: removal substrate support plate
Step 9: excision forming.
Preferably, substrate support plate uses metal plate or insulation board in step 1.
Preferably, adhesive film uses foam films in step 2.
Preferably, step 6, which is thinned to use, flushes convex block or copper post with insulating materials.
Preferably, plant ball is carried out after rerouting in step 7.
Preferably, step 8 removes substrate support plate by engraving method.
Compared with the prior art, the advantages of the present invention are as follows:
1, the present invention first carries out chip cutting, then carries out pasting chip in substrate, greatly improves the utilization rate of wafer；
2, insulating materials is only cut when present invention cutting, cutting crystal wafer, does not significantly reduce the risk of chipping；
3, the present invention uses and first carries out chip attachment, then presses insulating materials, and chip surrounding is made to have insulating materials filling,
Insulating materials is only cut when chip cutting, the cutting of homogenous material reduces the generation of cutting stress, reduces risk of delamination
Occur, increases the reliable of chip package；
4, the thermal expansion coefficient of silicon is 2.5 or so, such as directly upper pcb board, easily because of strain or stress, this hair caused by thermal mismatching
It is bright then to press insulating materials using first carrying out chip attachment, so that chip surrounding is had insulating materials filling, reduce bare chip with
The difference of the direct thermal expansion coefficient of PCB, increases the reliability of product；
5, the present invention is first cut using wafer, then is mounted, and the warpage issues of full wafer wafer are reduced；
6, fill insulant of the present invention uses pressing mode, does not need fixing mould, replaces traditional encapsulating mode advantageous
Typesetting rate is designed in improving；And process for pressing will not be influenced by tradition encapsulating injecting glue exhaust outlet size, be suitable for filler more
Small insulating materials processing, the final complete filling for realizing fine pitch convex block.
Detailed description of the invention
Fig. 1 is the schematic diagram of the Fan-out WLP encapsulating structure of existing standard.
Fig. 2~Figure 10 is a kind of each process flow chart of the manufacturing method of novel fan-out package structure of the present invention.
Wherein:
Substrate support plate 1
Adhesive film 2
Chip 3
Convex block or copper post 4
Insulating material membrane 5
PET film 6
Metal ball 7.
Specific embodiment
The present invention will be described in further detail below with reference to the embodiments of the drawings.
The manufacturing method of the novel Fan-out WLP encapsulating structure of one of the present embodiment, it the following steps are included:
Step 1: referring to fig. 2, taking a substrate support plate, the substrate support plate uses metal plate or insulation board；
Step 2: participating in Fig. 3, substrate carrier plate surface presses one layer of adhesive film (can be foam films)；
Step 3: referring to fig. 4, pasting chip
Wafer is cut into single chip, chip has convex block or copper post, mounts on the adhesive film of substrate carrier plate surface
Chip；
Step 4: referring to Fig. 5, fill insulant
Fill insulant, insulating materials film surface are set between chip and chip by the way of pressing insulating material membrane
It is equipped with one layer of PET film, convex block or copper post is made to penetrate insulating material membrane after pressing, into PET film layer, insulating materials is made by heating
Film solidification；
Step 5: removing the PET film on insulating materials surface referring to Fig. 6, convex block or copper post is made to expose insulating materials；
Step 6: being thinned referring to Fig. 7
By flushing convex block or copper post with insulating materials；
Step 7: being rerouted referring to Fig. 8
Rewiring design is carried out on insulating materials surface, and plants upper metal ball on rerouting layer；
Step 8: referring to Fig. 9, removal substrate support plate
Pass through the methods of etching removal substrate support plate；
Step 9: referring to Figure 10, excision forming
It is cut into the single product with independent electrical property.
In addition to the implementation, all to use equivalent transformation or equivalent replacement the invention also includes there is an other embodiments
The technical solution that mode is formed should all be fallen within the scope of the hereto appended claims.
Claims (6)
1. a kind of manufacturing method of novel fan-out package structure, it is characterised in that the described method comprises the following steps:
Step 1: taking a substrate support plate；
Step 2: substrate carrier plate surface presses one layer of adhesive film；
Step 3: pasting chip
Wafer is cut into single chip, chip has convex block or copper post, the pasting chip on the adhesive film of substrate carrier plate surface；
Step 4: fill insulant
Fill insulant, insulating materials film surface are provided between chip and chip by the way of pressing insulating material membrane
One layer of PET film, makes convex block or copper post penetrate insulating material membrane after pressing, into PET film layer, consolidate insulating material membrane by heating
Change；
Step 5: the PET film on removal insulating materials surface, makes convex block or copper post expose insulating materials；
Step 6: being thinned
Step 7: rerouting
Step 8: removal substrate support plate
Step 9: excision forming.
2. a kind of manufacturing method of novel fan-out package structure according to claim 1, it is characterised in that: in step 1
Substrate support plate uses metal plate or insulation board.
3. a kind of manufacturing method of novel fan-out package structure according to claim 1, it is characterised in that: in step 2
Adhesive film uses foam films.
4. a kind of manufacturing method of novel fan-out package structure according to claim 1, it is characterised in that: step 6 subtracts
Thin use flushes convex block or copper post with insulating materials.
5. a kind of manufacturing method of novel fan-out package structure according to claim 1, it is characterised in that: in step 7
Plant ball is carried out after rewiring.
6. a kind of manufacturing method of novel fan-out package structure according to claim 1, it is characterised in that: step 8 is logical
Overetch method removes substrate support plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810816552.8A CN109166807A (en) | 2018-07-24 | 2018-07-24 | The manufacturing method of novel fan-out package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810816552.8A CN109166807A (en) | 2018-07-24 | 2018-07-24 | The manufacturing method of novel fan-out package structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109166807A true CN109166807A (en) | 2019-01-08 |
Family
ID=64898177
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810816552.8A Pending CN109166807A (en) | 2018-07-24 | 2018-07-24 | The manufacturing method of novel fan-out package structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109166807A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102456584A (en) * | 2010-11-02 | 2012-05-16 | 新科金朋有限公司 | Semiconductor device and method of forming pentrable film encapsulant around semiconductor die and interconnect structure |
| US20140287555A1 (en) * | 2009-11-13 | 2014-09-25 | Tera Probe, Inc. | Semiconductor device including semiconductor construct installed on base plate, and manufacturing method of the same |
| CN104681456A (en) * | 2015-01-27 | 2015-06-03 | 华进半导体封装先导技术研发中心有限公司 | Fan-out-type wafer level package method |
-
2018
- 2018-07-24 CN CN201810816552.8A patent/CN109166807A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140287555A1 (en) * | 2009-11-13 | 2014-09-25 | Tera Probe, Inc. | Semiconductor device including semiconductor construct installed on base plate, and manufacturing method of the same |
| CN102456584A (en) * | 2010-11-02 | 2012-05-16 | 新科金朋有限公司 | Semiconductor device and method of forming pentrable film encapsulant around semiconductor die and interconnect structure |
| CN104681456A (en) * | 2015-01-27 | 2015-06-03 | 华进半导体封装先导技术研发中心有限公司 | Fan-out-type wafer level package method |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190108 |
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| RJ01 | Rejection of invention patent application after publication |