CN109166806A - A kind of TFT substrate and its preparation method and application - Google Patents
A kind of TFT substrate and its preparation method and application Download PDFInfo
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- CN109166806A CN109166806A CN201811005679.8A CN201811005679A CN109166806A CN 109166806 A CN109166806 A CN 109166806A CN 201811005679 A CN201811005679 A CN 201811005679A CN 109166806 A CN109166806 A CN 109166806A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 27
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- 238000009413 insulation Methods 0.000 claims abstract description 93
- 239000004065 semiconductor Substances 0.000 claims abstract description 62
- 238000005530 etching Methods 0.000 claims abstract description 44
- 230000004888 barrier function Effects 0.000 claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 35
- 239000000463 material Substances 0.000 claims abstract description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 29
- 239000011229 interlayer Substances 0.000 claims abstract description 27
- 238000002161 passivation Methods 0.000 claims abstract description 20
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 15
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 21
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 9
- QHGNHLZPVBIIPX-UHFFFAOYSA-N tin(ii) oxide Chemical compound [Sn]=O QHGNHLZPVBIIPX-UHFFFAOYSA-N 0.000 claims description 6
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- 239000010936 titanium Substances 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 4
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- BERDEBHAJNAUOM-UHFFFAOYSA-N copper(I) oxide Inorganic materials [Cu]O[Cu] BERDEBHAJNAUOM-UHFFFAOYSA-N 0.000 claims description 3
- KRFJLUBVMFXRPN-UHFFFAOYSA-N cuprous oxide Chemical compound [O-2].[Cu+].[Cu+] KRFJLUBVMFXRPN-UHFFFAOYSA-N 0.000 claims description 3
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- 238000003851 corona treatment Methods 0.000 claims description 2
- 239000003292 glue Substances 0.000 claims description 2
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
- 239000007772 electrode material Substances 0.000 claims 1
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- 229910052718 tin Inorganic materials 0.000 claims 1
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- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- Engineering & Computer Science (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention provides a kind of preparation methods of TFT substrate, including provide substrate, and buffer layer and semiconductor layer are sequentially formed on substrate, and the material of semiconductor layer is p-type metal oxide；Gate insulation layer and barrier metal layer are sequentially formed on semiconductor layer and buffer layer；Barrier metal layer is performed etching to form grid using photoresist, gate insulation layer is performed etching to form gate insulation layer, orthographic projection of the gate insulation layer on substrate is bigger than frontal projected area of the grid on substrate, and orthographic projection of the gate insulation layer on substrate is overlapped with orthographic projection center of the grid on substrate；Interlayer insulating film, source electrode, drain electrode and passivation layer are prepared again, obtain TFT substrate.TFT substrate produced by the present invention reduces parasitic capacitance using top-gated self-alignment structure, and by etching so that generation offset between gate insulation layer and grid, reduces grid to the leakage current between source-drain electrode；Material of the p-type metal oxide as semiconductor layer is used simultaneously, and p-type TFT substrate is made.
Description
Technical field
The present invention relates to technical field of display panel more particularly to a kind of TFT substrate and its preparation method and application.
Background technique
Thin film transistor (TFT) (Thin-film transistors, TFT) is used as a type MOS device, is always FPD
The core devices of technology.Thin film transistor (TFT) mainly has silicon substrate TFT, organic tft and oxide TFT, wherein amorphous silicon membrane crystal
Pipe and polycrystalline SiTFT are widely used in flat-panel monitor because of technique relative maturity；In recent years, metal oxide half
The TFT of conductor is gradually widely studied because having the advantages such as relatively high carrier mobility, high translucency, low temperature process
And application.
There is biggish amount over overlap in TFT preparation process and structure, between gate electrode and source-drain electrode, height is realized with this
Device performance and simplified technique.But overlapping between gate electrode and source-drain electrode can introduce big parasitic capacitance, these parasitic electricity
Clock signal on gate electrode can be coupled to drain electrode by appearance, influence circuit work, while big parasitic capacitance can also reduce device
The operating rate of part.Therefore, a kind of method that can reduce the parasitic capacitance in TFT device is needed.
Summary of the invention
In view of this, being reduced using top-gated self-alignment structure parasitic the present invention provides a kind of preparation method of TFT substrate
Capacitor, and by etching so that gate insulation layer and grid generate offset area, reduction grid to the leakage current between source-drain electrode；Together
When, p-type TFT substrate is made in the material by using p-type metal oxide as semiconductor layer.
In a first aspect, the present invention provides a kind of preparation methods of TFT substrate, comprising:
Substrate is provided, sequentially forms buffer layer and semiconductor layer on the substrate, the material of the semiconductor layer is p-type
Metal oxide, buffer layer described in the semiconductor layer covering part；
Gate insulation layer and barrier metal layer are sequentially formed on the semiconductor layer and the buffer layer；
The barrier metal layer is performed etching to form grid using photoresist, and the gate insulation layer is carved
Erosion forms gate insulation layer, orthographic projection of the orthographic projection of the gate insulation layer on the substrate than the grid on the substrate
Area it is big, and the orthographic projection of the gate insulation layer on the substrate and the orthographic projection center of the grid on the substrate
It is overlapped；
Interlayer insulating film, and shape are prepared on the buffer layer, the semiconductor layer, the gate insulation layer and the grid
At source contact area and drain contact region, then it is sequentially prepared source electrode, drain electrode and passivation layer, obtains TFT substrate.
Optionally, the buffer layer and the method for semiconductor layer of being formed includes in physical vapour deposition (PVD) and chemical vapor deposition
At least one.Specifically, can be, but not limited to as magnetic control radio-frequency technique, reactive sputtering technology, atomic layer deposition, plasma
Enhance chemical vapor deposition.
Optionally, the material of the buffer layer is selected from least one of silicon nitride, silica, silicon oxynitride.
Optionally, the buffer layer with a thickness ofIt is further alternative, the buffer layer with a thickness ofSpecifically, the thickness of the buffer layer can be, but not limited to for
Or
Optionally, the formation of the semiconductor further include: formed on the buffer layer and cover the initial of the buffer layer
Semiconductor layer performs etching to form the semiconductor layer to the initial semiconductor layer.In the present invention, to initial semiconductor layer
It performs etching, the part retained after etching is prepared as TFT channel for the formation of subsequent source-drain electrode.
Optionally, the etching includes at least one of wet etching and dry etching.
Optionally, the p-type metal oxide include in tin oxide, stannous oxide, copper oxide and cuprous oxide at least
It is a kind of.
Optionally, the semiconductor layer with a thickness ofIt is further alternative, the thickness of the semiconductor layer
ForSpecifically, the thickness of the semiconductor layer can be, but not limited to for
Or
In the prior art, the semiconductor layer of TFT substrate is n type material composition, and in the present invention, using p-type metal
P-type TFT substrate is made in material of the oxide as semiconductor layer, can arrange in pairs or groups with N-type TFT substrate in the prior art and use shape
At logic circuit.
Optionally, the gate insulation layer and the method for barrier metal layer of being formed includes physical vapour deposition (PVD) and chemical gaseous phase
At least one of deposition.Specifically, can be, but not limited to for magnetic control radio-frequency technique, reactive sputtering technology, atomic layer deposition, etc.
Gas ions enhance chemical vapor deposition.
Optionally, the material of the gate insulation layer is selected from least one of silicon nitride, silica, silicon oxynitride.
Optionally, the gate insulation layer with a thickness ofIt is further alternative, the gate insulation
Material layer with a thickness ofSpecifically, the thickness of the gate insulation layer can be, but not limited to forOr
Optionally, the material of the barrier metal layer is selected from least one of molybdenum, aluminium, copper, titanium.
Optionally, the barrier metal layer with a thickness ofIt is further alternative, the barrier metal layer
With a thickness ofSpecifically, the thickness of the barrier metal layer can be, but not limited to for Or
In the present invention, the thickness of the barrier metal layer is not less than the thickness of gate insulation layer, is formed after etching
Area of the offset area under identical etching condition between grid and gate insulation layer is bigger, reduces grid to source to be more advantageous to
Leakage current between drain electrode.
Optionally, the area of the orthographic projection of the grid on the substrate be the gate insulation layer on the substrate
The 40%-90% of the area of orthographic projection.Specifically, can be, but not limited to the face of the orthographic projection for the grid on the substrate
Product is 40%, 53%, 66%, 72%, 85% or the 90% of the area of the orthographic projection of the gate insulation layer on the substrate, more
Help to reduce grid to the leakage current between source-drain electrode.
Optionally, described that the barrier metal layer is performed etching to form grid using photoresist, and to the gate insulation
Material layer performs etching to form gate insulation layer, comprising: carries out wet etching to the barrier metal layer using the photoresist and is formed
Grid recycles the photoresist to carry out dry etching to the gate insulation layer and forms gate insulation layer.
Optionally, the technological parameter of the wet etching includes being performed etching using acid solution, etch period 1s-
1000s, wherein the concentration of the acid solution is 1%-30%, and the acid solution includes H2C2O4, HF or HNO3In at least one
Kind.Further alternative, the etch period is 10s-850s, 100s-700s, 160s-630s or 200s-500s.
Optionally, the technological parameter of the dry etching includes using CF4、SF6、C2F6、NF6One of or multiple gases
Dry etching, CF are carried out under atmosphere4Flow be 0sccm-5000sccm, SF6Flow be 0sccm-5000sccm, C2F6Stream
Amount is 0sccm-5000sccm, NF6Flow be 0sccm-5000sccm, etch period 1s-1000s.
In the present invention, it using photoresist as barrier layer, is carved using wet etching barrier metal layer due to the presence of etching liquid
Erosion liquid can laterally penetrate into, and accelerate etching speed in a lateral direction, so that the part stopped to photoresist performs etching；It utilizes
Photoresist, using dry etching gate insulation layer, thus be easier to deviate so that existing between gate insulation layer and grid,
That is the area of orthographic projection of orthographic projection of the gate insulation layer on substrate than grid on substrate is big, and gate insulation layer is on substrate
Orthographic projection is overlapped with orthographic projection center of the grid on substrate.Compared to bottom grating structure device, top gate structure is more advantageous to from right
Quasi- realization, top-gated self-alignment structure help to reduce parasitic capacitance.
Optionally, it is described prepare interlayer insulating film before further include: utilize the photoresist, pass through corona treatment
Mode carries out conductor processing to the two sides of the semiconductor layer.Specifically, can be, but not limited to be using the photoresist
Stop, using plasma bombarding semiconductor layer surface, forms metalloid layer.
Optionally, the interlayer insulating film for preparing further includes before removing the photoresist.
Optionally, the method for preparing interlayer insulating film include in physical vapour deposition (PVD) and chemical vapor deposition at least
It is a kind of.Specifically, can be, but not limited to as magnetic control radio-frequency technique, reactive sputtering technology, atomic layer deposition, plasma enhancing
Learn vapor deposition.
Optionally, the material of the interlayer insulating film is selected from least one of silicon nitride, silica, silicon oxynitride.
Optionally, the interlayer insulating film with a thickness ofFurther alternative, the interlayer is exhausted
Edge layer with a thickness ofSpecifically, the thickness of the interlayer insulating film can be, but not limited to forOr
Optionally, the material of the source electrode and drain electrode is independently selected from least one of molybdenum, aluminium, copper, titanium.
Optionally, the material of the passivation layer is selected from least one of silicon nitride, silica, silicon oxynitride.
Optionally, the passivation layer with a thickness ofIt is further alternative, the passivation layer with a thickness ofSpecifically, the thickness of the passivation layer can be, but not limited to for
Or
First aspect present invention provides a kind of preparation method of TFT substrate, is carved by photoresist to barrier metal layer
Erosion forms grid, and performs etching to form gate insulation layer to gate insulation layer, forms top-gated self-alignment structure, is conducive to reduce
Parasitic capacitance；Meanwhile control deviates the etching technics of grid and gate insulation layer so that existing between grid and gate insulation layer,
That is the area of orthographic projection of orthographic projection of the gate insulation layer on substrate than grid on substrate is big, and gate insulation layer is on substrate
Orthographic projection is overlapped with orthographic projection center of the grid on substrate, advantageously reduces the leakage current between grid and source-drain electrode；And
Use p-type metal oxide as the material of semiconductor, p-type TFT substrate is made, can arrange in pairs or groups with N-type TFT substrate and realize logic
Circuit.
Second aspect, the present invention provides a kind of TFT substrates, are prepared using preparation method described in first aspect,
The TFT substrate includes substrate, and sequentially form buffer layer on the substrate, semiconductor layer, gate insulation layer, grid,
Interlayer insulating film, source electrode, drain electrode and passivation layer, wherein the orthographic projection of the gate insulation layer on the substrate is than the grid
The area that the orthographic projection on substrate is stated at place is big, and the orthographic projection of the gate insulation layer on the substrate and the grid are in institute
The orthographic projection center stated on substrate is overlapped, and it is exhausted that the interlayer insulating film is covered on the buffer layer, the semiconductor layer, the grid
In edge layer and the grid, the passivation layer is covered on the layer insulation layer surface and the source electrode and the leakage is completely covered
Pole.
The TFT substrate that second aspect of the present invention provides has top-gated self-alignment structure, reduces parasitic capacitance, and grid and grid
There is offset between insulating layer, advantageously reduces the leakage current between grid and source-drain electrode.
The third aspect, the present invention provides a kind of display devices, including TFT substrate described in second aspect.
Specifically, the display device can be, but not limited to as active matrix organic light-emitting diode (AMOLED), TFT-
LCD。
Beneficial effects of the present invention:
TFT substrate prepared by the present invention performs etching barrier metal layer to form grid by photoresist, and to gate insulation material
The bed of material performs etching to form barrier metal layer, to form top-gated self-alignment structure, is conducive to reduce parasitic capacitance；Meanwhile it controlling
To the etching technics of grid and gate insulation layer, so that there is offset between grid and gate insulation layer, grid and source and drain are reduced
Leakage current between pole；And it uses p-type metal oxide as the material of semiconductor, p-type TFT substrate is made, it can be with N-type
Logic circuit is realized in TFT substrate collocation.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described.Specific embodiment described herein is only used to explain this
Invention, is not intended to limit the present invention.
Fig. 1 is a kind of flow chart of the preparation method for TFT substrate that present invention implementation provides；
Fig. 2 is step S101 schematic diagram in a kind of preparation method for TFT substrate that present invention implementation provides；
Fig. 3 is step S102 schematic diagram in a kind of preparation method for TFT substrate that present invention implementation provides；
Fig. 4 is step S103 schematic diagram in a kind of preparation method for TFT substrate that present invention implementation provides；
Fig. 5 is step S104 schematic diagram in a kind of preparation method for TFT substrate that present invention implementation provides；
Fig. 6 is a kind of schematic diagram for TFT substrate that present invention implementation provides.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Referring to Fig. 1, being a kind of flow chart of the preparation method of TFT substrate provided in an embodiment of the present invention, including as follows
Step:
Step S101: providing substrate, sequentially form buffer layer and semiconductor layer on the substrate, the semiconductor layer
Material is p-type metal oxide, buffer layer described in the semiconductor layer covering part.
Referring to Fig.2, providing substrate 10, the substrate 10 can be glass substrate, quartz base plate, flexible base board etc..Pass through
After dry method cleaning or wet-cleaning substrate 10, the buffer layer 20 of one layer of entire substrate 10 of covering is formed on the substrate 10.Optionally,
The material of the buffer layer 20 is selected from least one of silicon nitride, silica, silicon oxynitride.Optionally, the buffer layer 20
With a thickness ofIt is further alternative, the buffer layer 20 with a thickness ofSpecifically,
The thickness of the buffer layer 20 can be, but not limited to forOrIt is optional
, the formation of the semiconductor 30 further include: the initial semiconductor layer for covering the buffer layer is formed on the buffer layer, it is right
The initial semiconductor layer performs etching to form the semiconductor layer 30.Optionally, the etching includes wet etching and dry method
At least one of etching.In the present invention, initial semiconductor layer is performed etching, the part retained after etching is as TFT ditch
Road is prepared for the formation of subsequent source-drain electrode.In the present invention, the material of the semiconductor layer 30 is the metal oxide of p-type.
Optionally, the metal oxide includes at least one of tin oxide, stannous oxide, copper oxide and cuprous oxide.Optionally,
The semiconductor layer 30 with a thickness ofIt is further alternative, the semiconductor layer 30 with a thickness ofSpecifically, the thickness of the semiconductor layer 30 can be, but not limited to forOrIn the prior art, the material of semiconductor layer is n type material, and
In the present invention, using the metal oxide of p-type as semiconductor layer, it is prepared into p-type TFT substrate, it can be with N-type in the prior art
TFT substrate collocation use forms logic circuit.Optionally, the buffer layer 20 and the method for semiconductor layer 30 of being formed includes physics
At least one of vapor deposition and chemical vapor deposition.Specifically, can be, but not limited to as magnetic control radio-frequency technique, reactive sputtering
Technology, atomic layer deposition, plasma enhanced chemical vapor deposition.
Step S102: gate insulation layer and barrier metal layer are sequentially formed on the semiconductor layer and the buffer layer.
Refering to Fig. 3, gate insulation layer 40 and grid gold are sequentially formed on the semiconductor layer 30 and the buffer layer 20
Belong to layer 50.Optionally, the gate insulation layer 40 and the method for barrier metal layer 50 of being formed includes physical vapour deposition (PVD) and chemistry
At least one of vapor deposition.Specifically, can be, but not limited to as magnetic control radio-frequency technique, reactive sputtering technology, atomic layer deposition
Product, plasma enhanced chemical vapor deposition.Optionally, the material of the gate insulation layer 40 be selected from silicon nitride, silica,
At least one of silicon oxynitride.Optionally, the gate insulation layer 40 with a thickness ofFurther may be used
Choosing, the gate insulation layer 40 with a thickness ofSpecifically, the thickness of the gate insulation layer 40
Can be, but not limited to for OrOptionally, the barrier metal layer 50
Material be selected from least one of molybdenum, aluminium, copper, titanium.Optionally, the barrier metal layer 50 with a thickness of
It is further alternative, the barrier metal layer 50 with a thickness ofSpecifically, the thickness of the barrier metal layer 50
Can be, but not limited to forOr
Step S103: the barrier metal layer is performed etching to form grid using photoresist, and to the gate insulation material
The bed of material performs etching to form gate insulation layer, and the orthographic projection of the gate insulation layer on the substrate is than the grid in the substrate
On orthographic projection area it is big, and the orthographic projection of the gate insulation layer on the substrate and the grid are on the substrate
Orthographic projection center is overlapped.
Refering to Fig. 4, the barrier metal layer 50 is performed etching to form grid 60 using photoresist, and to the gate insulation
Material layer 40 performs etching to form gate insulation layer 41, and orthographic projection of the gate insulation layer 41 on the substrate 10 is than the grid
The area of 60 orthographic projection on the substrate 10 is big, and orthographic projection of the gate insulation layer 41 on the substrate 10 with it is described
Orthographic projection center of the grid 60 on the substrate 10 is overlapped.Optionally, the face of the orthographic projection of the grid on the substrate
Product is the 40%-90% of the area of the orthographic projection of the gate insulation layer on the substrate.Specifically, can be, but not limited to as institute
The area for stating the orthographic projection of grid on the substrate is the area of the orthographic projection of the gate insulation layer on the substrate
40%, 53%, 66%, 72%, 85% or 90%, it is more conducive to reduce grid to the leakage current between source-drain electrode.Optionally, institute
It states and the barrier metal layer 50 is performed etching to form grid 60 using photoresist, and the gate insulation layer 40 is carved
Erosion forms gate insulation layer 41, comprising: and wet etching is carried out to the barrier metal layer 50 using the photoresist and forms grid 60, then
Dry etching is carried out to the gate insulation layer 40 using the photoresist and forms gate insulation layer 41.It is further alternative, institute
The technological parameter for stating wet etching includes being performed etching using acid solution, etch period 1s-1000s, wherein the acid solution
Concentration be 1%-30%, the acid solution includes H2C2O4, HF or HNO3At least one of.It is further optional, it is described
Etch period is 10s-850s, 100s-700s, 160s-630s or 200s-500s.It is further alternative, the dry etching
Technological parameter includes using CF4、SF6、C2F6、NF6One of or multiple gases atmosphere under carry out dry etching, CF4Flow be
0sccm-5000sccm, SF6Flow be 0sccm-5000sccm, C2F6Flow be 0sccm-5000sccm, NF6Flow
For 0sccm-5000sccm, etch period 1s-1000s.In the present invention, using photoresist as barrier layer, using wet etching
Barrier metal layer 50, due to the presence of etching liquid, etching liquid can laterally penetrate into, and accelerate etching speed in a lateral direction, thus
The part stopped to photoresist performs etching；Using photoresist, using dry etching gate insulation layer 40, the gate insulation of formation
There is offset, the i.e. orthographic projection of gate insulation layer 41 on the substrate 10 between layer 41 and grid 60 on the substrate 10 just than grid 60
The area of projection is big, and the orthographic projection center weight of the orthographic projection of gate insulation layer 41 on the substrate 10 and grid 60 on the substrate 10
It closes.Compared to bottom grating structure device, top gate structure is more advantageous to self aligned realization, and top-gated self-alignment structure, which helps to reduce, posts
Raw capacitor.
Step S104: it is exhausted on the buffer layer, the semiconductor layer, the gate insulation layer and the grid to prepare interlayer
Edge layer, and source contact area and drain contact region are formed, then be sequentially prepared source electrode, drain electrode and passivation layer, obtain TFT substrate.
Refering to Fig. 5, prepared on the buffer layer 20, the semiconductor layer 30, the gate insulation layer 41 and the grid
Interlayer insulating film 70, and source contact area and drain contact region are formed, then be sequentially prepared source electrode 80, drain electrode 90 and passivation layer 100,
Obtain TFT substrate.Optionally, it is described prepare interlayer insulating film 70 before further include: utilize the photoresist, pass through plasma
The mode of processing carries out conductor processing to the two sides of the semiconductor layer 30.As shown in figure 5, the two sides of semiconductor layer 30 carry out
Conductorization processing, that is, form metalloid layer.Specifically, can be, but not limited to be blocking using the photoresist, using etc. from
Daughter bombarding semiconductor layer surface is not photo-etched the surface of glue shield portions, through plasma bombardment in bombarding semiconductor layer
After form metalloid layer.Optionally, the interlayer insulating film 70 for preparing further includes before removing the photoresist.Optionally,
The method for preparing interlayer insulating film 70 includes at least one of physical vapour deposition (PVD) and chemical vapor deposition.Specifically,
It can be, but not limited to as magnetic control radio-frequency technique, reactive sputtering technology, atomic layer deposition, plasma enhanced chemical vapor deposition.
Optionally, the material of the interlayer insulating film 70 is selected from least one of silicon nitride, silica, silicon oxynitride.Optionally, institute
State interlayer insulating film 70 with a thickness ofIt is further alternative, the interlayer insulating film 70 with a thickness ofSpecifically, the thickness of the interlayer insulating film 70 can be, but not limited to forOrOptionally, the source electrode 80 and the material of drain electrode 90 are independent
Ground is selected from least one of molybdenum, aluminium, copper, titanium.Optionally, the material of the passivation layer 100 is selected from silicon nitride, silica, nitrogen
At least one of silica.Optionally, the passivation layer 100 with a thickness ofIt is further alternative, institute
State passivation layer 100 with a thickness ofSpecifically, the thickness of the passivation layer 100 can be, but not limited to for Or
The present invention provides a kind of preparation methods of TFT substrate, perform etching to form grid to barrier metal layer by photoresist
Pole, and gate insulation layer is performed etching to form gate insulation layer, top-gated self-alignment structure is formed, is conducive to reduce parasitic electricity
Hold；Meanwhile control, to the etching technics of grid and gate insulation layer, so that there is offset between grid and gate insulation layer, i.e., grid are exhausted
The area of orthographic projection of orthographic projection of the edge layer on substrate than grid on substrate is big, and orthographic projection of the gate insulation layer on substrate
It is overlapped with orthographic projection center of the grid on substrate, advantageously reduces the leakage current between grid and source-drain electrode；And use p-type
P-type TFT substrate is made in material of the metal oxide as semiconductor, can arrange in pairs or groups with N-type TFT substrate and realize logic circuit.
The embodiment of the invention also provides a kind of TFT substrate, the TFT substrate uses the preparation side of above-mentioned TFT substrate
Method is prepared, as shown in fig. 6, the TFT substrate includes substrate 10, and the buffer layer being sequentially formed on the substrate 10
20, semiconductor layer 30, gate insulation layer 41, grid 60, interlayer insulating film 70, source electrode 80, drain electrode 90 and passivation layer 100, wherein institute
It is bigger than the area for stating the orthographic projection on substrate 10 where the grid 60 in the orthographic projection on the substrate 10 to state gate insulation layer 41,
And the gate insulation layer 41 on the substrate 10 orthographic projection and orthographic projection center of the grid 60 on the substrate 10
It is overlapped, the interlayer insulating film 70 is covered on the buffer layer 20, the semiconductor layer 30, the gate insulation layer 41 and the grid
On pole 60, the passivation layer 100 is covered on 70 surface of interlayer insulating film and the source electrode 80 and the drain electrode is completely covered
90。
TFT substrate provided by the invention has top-gated self-alignment structure, advantageously reduces parasitic capacitance；Meanwhile grid and
There is offset between gate insulation layer, can contribute to reduce the leakage current between grid and source-drain electrode.
The embodiment of the invention also provides a kind of display device, the display device includes above-mentioned TFT substrate.Specifically
, the display device can be, but not limited to as active matrix organic light-emitting diode (AMOLED), TFT-LCD.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
Limitations on the scope of the patent of the present invention therefore cannot be interpreted as.It should be pointed out that for those of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to guarantor of the invention
Protect range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (10)
1. a kind of preparation method of TFT substrate characterized by comprising
Substrate is provided, sequentially forms buffer layer and semiconductor layer on the substrate, the material of the semiconductor layer is p-type metal
Oxide, buffer layer described in the semiconductor layer covering part；
Gate insulation layer and barrier metal layer are sequentially formed on the semiconductor layer and the buffer layer；
The barrier metal layer is performed etching to form grid using photoresist, and shape is performed etching to the gate insulation layer
At gate insulation layer, the face of orthographic projection of the orthographic projection of the gate insulation layer on the substrate than the grid on the substrate
Product is big, and the orthographic projection center weight of the orthographic projection of the gate insulation layer on the substrate and the grid on the substrate
It closes；
Interlayer insulating film is prepared on the buffer layer, the semiconductor layer, the gate insulation layer and the grid, and forms source
Pole contact zone and drain contact region, then it is sequentially prepared source electrode, drain electrode and passivation layer, obtain TFT substrate.
2. the preparation method of TFT substrate as described in claim 1, which is characterized in that the grid is on the substrate just
The area of projection is the 40%-90% of the area of the orthographic projection of the gate insulation layer on the substrate.
3. the preparation method of TFT substrate as described in claim 1, which is characterized in that the p-type metal oxide includes oxidation
At least one of tin, stannous oxide, copper oxide and cuprous oxide.
4. the preparation method of TFT substrate as described in claim 1, which is characterized in that using photoresist to the barrier metal layer
It performs etching to form grid, and the gate insulation layer is performed etching to form gate insulation layer, comprising: utilize the photoetching
Glue carries out wet etching to the barrier metal layer and forms grid, and the photoresist is recycled to do the gate insulation layer
Method etches to form gate insulation layer.
5. the preparation method of TFT substrate as described in claim 1, which is characterized in that the buffer layer, the gate insulation
The material of layer, the interlayer insulating film and the passivation layer is independently selected from least one in silicon nitride, silica, silicon oxynitride
Kind.
6. the preparation method of TFT substrate as described in claim 1, which is characterized in that the barrier metal layer, source electrode and drain electrode
Material is independently selected from least one of molybdenum, aluminium, copper, titanium.
7. the preparation method of TFT substrate as described in claim 1, which is characterized in that the semiconductor layer with a thickness ofThe gate insulation layer with a thickness ofThe barrier metal layer with a thickness of
8. the preparation method of TFT substrate as described in claim 1, which is characterized in that described to prepare interlayer insulating film before also
It include: that conductor processing is carried out to the two sides of the semiconductor layer by way of corona treatment using the photoresist.
9. a kind of TFT substrate, which is characterized in that be prepared using such as the described in any item preparation methods of claim 1-8, institute
Stating TFT substrate includes substrate, and sequentially forms buffer layer, semiconductor layer, gate insulation layer, grid, layer on the substrate
Between insulating layer, source electrode, drain electrode and passivation layer, wherein the orthographic projection of the gate insulation layer on the substrate is than the grid institute
It is big in the area for stating the orthographic projection on substrate, and the orthographic projection of the gate insulation layer on the substrate with the grid described
Orthographic projection center on substrate is overlapped, and the interlayer insulating film is covered on the buffer layer, the semiconductor layer, the gate insulation
On layer and the grid, the passivation layer is covered on the layer insulation layer surface and the source electrode and the leakage is completely covered
Pole.
10. a kind of display device, which is characterized in that including TFT substrate as claimed in claim 9.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101304047A (en) * | 2008-07-07 | 2008-11-12 | 友达光电股份有限公司 | Thin-film transistor |
| CN107452809A (en) * | 2017-09-04 | 2017-12-08 | 深圳市华星光电半导体显示技术有限公司 | Thin-film transistor structure and AMOLED drive circuits |
| CN107623042A (en) * | 2017-09-21 | 2018-01-23 | 深圳市华星光电半导体显示技术有限公司 | Thin-film transistor structure and preparation method thereof |
| CN108288586A (en) * | 2018-01-08 | 2018-07-17 | 深圳市华星光电半导体显示技术有限公司 | A kind of P-type TFT and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101304047A (en) * | 2008-07-07 | 2008-11-12 | 友达光电股份有限公司 | Thin-film transistor |
| CN107452809A (en) * | 2017-09-04 | 2017-12-08 | 深圳市华星光电半导体显示技术有限公司 | Thin-film transistor structure and AMOLED drive circuits |
| CN107623042A (en) * | 2017-09-21 | 2018-01-23 | 深圳市华星光电半导体显示技术有限公司 | Thin-film transistor structure and preparation method thereof |
| CN108288586A (en) * | 2018-01-08 | 2018-07-17 | 深圳市华星光电半导体显示技术有限公司 | A kind of P-type TFT and preparation method thereof |
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Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant after: TCL Huaxing Photoelectric Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |
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