CN109148556A - Superjunction devices and its manufacturing method - Google Patents
Superjunction devices and its manufacturing method Download PDFInfo
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- CN109148556A CN109148556A CN201710500206.4A CN201710500206A CN109148556A CN 109148556 A CN109148556 A CN 109148556A CN 201710500206 A CN201710500206 A CN 201710500206A CN 109148556 A CN109148556 A CN 109148556A
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- 230000007704 transition Effects 0.000 claims abstract description 64
- 238000001259 photo etching Methods 0.000 claims abstract description 54
- 238000011049 filling Methods 0.000 claims abstract description 42
- 238000002347 injection Methods 0.000 claims abstract description 37
- 239000007924 injection Substances 0.000 claims abstract description 37
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 28
- 239000010937 tungsten Substances 0.000 claims abstract description 28
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- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 239000000203 mixture Substances 0.000 claims description 9
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- 238000001312 dry etching Methods 0.000 claims description 7
- 238000001459 lithography Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 238000006735 epoxidation reaction Methods 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
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- 230000015556 catabolic process Effects 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 22
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- 239000000758 substrate Substances 0.000 description 18
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- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- Microelectronics & Electronic Packaging (AREA)
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- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a kind of superjunction devices; it is provided with the protection ring oxidation film for being looped around charge flow region side; make the region JFET and source region that can realize comprehensive injection; the depth-width ratio of the second contact hole in transition region be more than or equal to charge flow region in the first contact hole depth-width ratio, using tungsten plug process filling simultaneously realize to different aspect ratios first and two contact hole reliable filling.The invention also discloses a kind of manufacturing methods of superjunction devices.The present invention can in transition region contact hole use higher depth-width ratio when reliably filled; protection ring oxidation film can be formed in transition region and reduces photoetching level using protection ring oxidation film; it also helps and contact hole is laid out according to device needs, while guaranteeing that the avalanche resistance breakdown capability of device is not influenced by the contact hole technique of transition region.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing fields, more particularly to a kind of superjunction (super junction) device
Part；The invention further relates to a kind of manufacturing methods of superjunction devices.
Background technique
In existing superjunction devices, in charge flow region, there are alternately arranged p-type column and N-type column, with the P-N column of strip
For the structure of i.e. alternately arranged p-type column and N-type column, there is a polysilicon gate above each N column, which can be with
Part covers the P column on periphery, can not also cover, have a p-type trap (PWell) above each P column, have one in p-type trap
A N+ source region has a contact hole, and source metal is connected by contact hole with source region, and source metal is by passing through a high concentration
The contact zone P+ be connected with the area P, that is, p-type trap, source metal be form source electrode front metal layer.
Charge flow region and bear voltage terminal area between, there are a transition region, have in transition region one and
The p-type trap of charge flow region connected p-type ring region is formed with contact hole in the p-type ring region, also has one under the contact hole
The contact zone P+ of a high concentration, therefore p-type ring is connected to source metal also by the contact hole of the contact zone P+ and top.
For ease of design, or in order to reduce the number of photoetching, carried out using thick field oxide film as autoregistration
In the case where source region ion implanting, the p-type ring of transition region at least partial region needs to be covered by thick field oxide film, therefore quilt
The depth-width ratio for the contact hole on region that thick oxide film is covered can be greater than the minimum depth-width ratio of the contact hole of charge flow region,
The contact hole of middle charge flow region only needs guiding through interlayer film, and the contact hole on the region covered in transition region by thick oxide film
It then needs also cross interlayer film and thick oxide film, so there is the depth-width ratio of the contact hole on the region covered by thick oxide film
The minimum depth-width ratio of the contact hole of charge flow region can be greater than；And in prior art, Metal deposition be using Ti, TiN and
When the manufacturing process of ALCu, Ti, TiN and ALSiCu, the covering power of the metal to metal contact hole is limited, higher to depth-width ratio
Such as larger than 0.5 hole will appear metal pin hole when carrying out metal filling, cause the Performance And Reliability problem of device.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of superjunction devices, can in transition region contact hole use it is higher
Depth-width ratio when carry out pin-free filling, protection ring oxidation film and subtracted using protection ring oxidation film so as to be formed in transition region
Few photoetching level is also helped and is laid out to contact hole according to device needs, while guaranteeing the avalanche resistance breakdown capability of device
It is not influenced by the contact hole technique of transition region.For this purpose, the present invention also provides a kind of manufacturing methods of superjunction devices.
In order to solve the above technical problems, the intermediate region of superjunction devices provided by the invention is charge flow region, termination environment
It is surrounded on the periphery of the charge flow region, transition region is between the charge flow region and the termination environment；Include:
N-type epitaxy layer, the N-type epitaxy layer carry out dry etching and form multiple grooves；It is filled in the trench by p-type
Epitaxial layer and composition p-type column form N-type column by the N-type epitaxy layer between each p-type column, by multiple alternately arranged
The super-junction structure of the N-type column and p-type column composition.
The top of each p-type column is all formed with a p-type trap in the charge flow region and each p-type trap extends
To the surface of the N-type column of corresponding p-type column two sides.
The surface of the super-junction structure described in the transition region is formed with the p-type for being looped around the side of the charge flow region
Ring；Each p-type trap and the p-type ring are in contact.
The first oxidation film, protection ring are formed on the super-junction structure surface for being formed with the p-type trap and the p-type ring
Oxidation film is formed by carrying out chemical wet etching to first oxidation film, and the protection ring oxidation film reveals the charge flow region
The partial region of the transition region is covered out and at least, the protection ring oxidation film also extends into the termination environment surface simultaneously
The termination environment is all covered or only exposes the outermost circumferential portion of the termination environment, the protection ring oxidation film is looped around institute
State the side of charge flow region.
The surface of the p-type trap of the charge flow region be formed with by N+ district's groups at source region, the injection of the source region
Region is defined by the protection ring oxidation film autoregistration.
It is formed with the first contact hole in the charge flow region, the second contact hole is formed in the transition region, it is described
First contact hole is identical with the lithographic etch process of second contact hole.
The source electrode being made of front metal layer is all connected at the top of first contact hole and second contact hole.
The bottom of first contact hole passes through interlayer film and the source region and realizes and the source region and the p-type trap
Contact.
The surface that second contact hole is distributed in the transition region is covered with the partial region of the protection ring oxidation film
In, the bottom of second contact hole passes through interlayer film and the protection ring oxidation film and realization and the contact of the p-type ring.
The ratio of the depth and smallest lateral dimension that enable first contact hole is the first depth-width ratio, second contact hole
Depth and smallest lateral dimension ratio be the second depth-width ratio；Second depth-width ratio is more than or equal to first depth-width ratio,
First contact hole and second contact hole all use tungsten plug process filling, utilize the tungsten plug technique device to hole covering power
Guarantee while realizing the reliable filling to first contact hole and second contact hole with different aspect ratios.
A further improvement is that be formed with by gate oxidation films on the surface of the super-junction structure of the charge flow region and
Polysilicon gate is superimposed the planar gate structure to be formed, and the forming region of the polysilicon gate is defined by photoetching process, each described more
Crystal silicon grid cover the corresponding p-type trap and are used to form channel by the surface for the p-type trap that the polysilicon gate covers.
The source region autoregistration is formed in the polysilicon gate two sides in the charge flow region.
Each polysilicon gate structure in a strip shape and the length direction of each polysilicon gate and the length side of the groove
To parallel.
Protection ring oxidation film surface in the termination environment is formed with polysilicon bus, and each polysilicon gate passes through
The polysilicon line for being formed in the protection ring oxidation film surface of the transition region is connected to the polysilicon bus, described more
Crystal silicon bus, the polysilicon line and the polysilicon gate use identical polycrystalline silicon deposit and polycrystalline silicon etching process simultaneously
It is formed；The width of the polysilicon line is less than or equal to the width of the polysilicon gate.
A further improvement is that the length direction of each first contact hole structure in a strip shape and each first contact hole
It is parallel with the length direction of the groove；The width of each first contact hole is smallest lateral dimension.
It include first contact hole or two of a structure in a strip shape between the every two adjacent polysilicon gates
First contact hole of more than item structure in a strip shape arranged in parallel or multiple vertical view faces are first contact of rectangle
Hole arranges the array structure to be formed.
The vertical view face of each second contact hole is rectangle, and the width of second contact hole is more than or equal to described first and connects
The width of contact hole includes second contact hole or including by multiple between the every two adjacent polysilicon lines
Second contact hole arranges the array structure to be formed.
A further improvement is that the surplus that second contact hole is encased and guaranteed completely by the p-type ring is more than or equal to 1
Micron.
A further improvement is that third contact hole is formed at the top of the polysilicon bus, first contact hole
It is identical with the lithographic etch process of the third contact hole.
The grid being made of front metal layer is all connected at the top of the third contact hole.
The bottom of the third contact hole pass through interlayer film and enter in the polysilicon bus and the third contact
The bottom in hole rests in the polysilicon bus or passes through the polysilicon bus.
A further improvement is that second contact hole also extends and is distributed to the surface of the transition region and does not cover the guarantor
In the partial region of retaining ring oxidation film, the bottom of second contact hole in the partial region pass through the interlayer film realize and
The contact of the p-type ring.
A further improvement is that being formed with P+ contact in the bottom of each first contact hole and each second contact hole
Area.
A further improvement is that the p-type trap is identical with the process conditions of the p-type ring and is formed simultaneously；Alternatively, described
The process conditions of p-type ring and the p-type trap independence and are formed separately each other.
A further improvement is that the super-junction structure surface in the charge flow region is formed with the area JFET, it is described
The forming region in the area JFET is defined by the protection ring oxidation film autoregistration.
In order to solve the above technical problems, the intermediate region of the superjunction devices of the manufacturing method of superjunction devices provided by the invention
For charge flow region, termination environment is surrounded on the periphery of the charge flow region, and transition region is located at the charge flow region and described
Between termination environment；Include the following steps:
Step 1: providing N-type epitaxy layer, the forming region that first time photoetching process defines groove is carried out, later to institute
It states N-type epitaxy layer progress dry etching and forms multiple grooves.
Filling p-type epitaxial layer forms p-type column in the trench, by the N-type epitaxy layer group between each p-type column
At N-type column, the super-junction structure being made of multiple alternately arranged N-type columns and the p-type column.
Step 2: carrying out the forming region that second of photoetching process defines p-type trap in the charge flow region, later
P-type ion is carried out to inject to form the p-type trap.
The top of each p-type column is all formed with the p-type trap in the charge flow region and each p-type trap prolongs
Reach the surface of the N-type column of corresponding p-type column two sides.
The surface of super-junction structure while forming the p-type trap using identical technique in the transition region
Form the p-type ring for being looped around the side of the charge flow region；Each p-type trap and the p-type ring are in contact.
Step 3: it is raw to carry out the first oxidation film on the super-junction structure surface for being formed with the p-type trap and the p-type ring
It is long, the etch areas that third time photoetching process defines first oxidation film is carried out, first oxidation film is carried out later
Etching forms protection ring oxidation film, and the charge flow region is exposed and at least by the transition region by the protection ring oxidation film
Partial region covering, the protection ring oxidation film also extend into the termination environment surface and by the termination environment all covering or
Only the outermost circumferential portion of the termination environment is exposed, the protection ring oxidation film is looped around the side of the charge flow region.
Comprehensive first time N-type ion, which is carried out, as autoregistration condition using the protection ring oxidation film is infused in the electric charge stream
The region JFET is formed in dynamic area, while in the termination environment except protection ring oxidation film overlay area or outside is formed
The first N-type of terminal injection region.
Step 4: sequentially forming the first layer polysilicon of gate oxidation films and N-type heavy doping, it is fixed to carry out fourth lithography technique
Justice goes out the forming region of polysilicon gate, performs etching to form polysilicon gate to the first layer polysilicon later, each polycrystalline
Si-gate is planar gate structure, the P that each polysilicon gate covers the corresponding p-type trap and covered by the polysilicon gate
The surface of type trap is used to form channel.
Comprehensive second of N-type ion note is carried out using the polysilicon gate and the protection ring oxidation film as autoregistration condition
Enter the polysilicon gate two sides in the charge flow region and be respectively formed source region, while being covered in the protection ring oxidation film
In the termination environment except region or outside forms the second N-type of terminal injection region.
Step 5: deposit interlayer film, carries out the 5th photoetching process and defines the first contact hole, the second contact hole and third
The forming region of contact hole；It performs etching to form first contact hole, second contact hole and third contact later
The opening in hole；Metal is filled in the opening of first contact hole, second contact hole and the third contact hole to be formed
First contact hole, second contact hole and the third contact hole.
The bottom of first contact hole passes through the interlayer film and the source region and realizes and the source region and the P
The contact of type trap.
The surface that second contact hole is distributed in the transition region is covered with the partial region of the protection ring oxidation film
In, the bottom of second contact hole passes through interlayer film and the protection ring oxidation film and realization and the contact of the p-type ring.
The ratio of the depth and smallest lateral dimension that enable first contact hole is the first depth-width ratio, second contact hole
Depth and smallest lateral dimension ratio be the second depth-width ratio；Second depth-width ratio is more than or equal to first depth-width ratio,
First contact hole, second contact hole and the third contact hole all use tungsten plug process filling, utilize the tungsten plug
Technique device to hole covering power guarantees while realizing to first contact hole and second contact hole with different aspect ratios
Reliable filling.
Step 6: carry out front metal deposit to form front metal layer, carry out the 6th photoetching process define grid and
The forming region of source electrode performs etching the front metal layer to form the grid and the source electrode, the electric charge stream later
Each source region and the corresponding p-type trap in dynamic area are connected to the source by identical first contact hole in top
Pole, the p-type ring in the transition region are connected to the source electrode, the polysilicon also by second contact hole at top
Grid are connected to grid by the third contact hole.
A further improvement is that the first contact hole described in step 5, second contact hole and the third contact hole
Opening formed after metal filling before further include the bottom of first contact hole and second contact hole carry out P+ ion
The step of injection forms the contact zone P+.
A further improvement is that the interlayer film is made of oxidation film, in step 5 etching formed first contact hole,
The etching that oxidation film is first carried out when the opening of second contact hole and the third contact hole, in the first contact bore region
The interlayer film stop the etching of oxidation film when completely removing and exposing the source region of bottom, carry out epitaxial film materials
Etching；The epitaxial layer of the bottom of first contact hole described in when carrying out the etching of the epitaxial film materials generates over etching, while institute
The oxidation film for stating the second contact bore region can partial etching；It is not completely removed it in the oxidation film of the second contact bore region
The preceding P+ ion implanting for carrying out the contact zone P+ makes the P+ ion implanting of the contact zone P+ of the second contact bore region
Peak value be located in oxidation film so that the opening of first contact hole, second contact hole and the third contact hole with
And after metal filling completely, the peak value of the doping concentration of the contact zone P+ of second contact hole bottom is less than described first
The peak value of the doping concentration of the contact zone P+ of contact hole bottom.
It is located at the second contact bore region when a further improvement is that stating the P+ ion implanting of the contact zone P+ by adjusting
The thickness of the oxidation film of bottom adjusts the doping concentration of the contact zone P+ of second contact hole bottom, and makes described second
The peak value of the doping concentration of the contact zone P+ of contact hole bottom is the contact zone P+ of first contact hole bottom
The 1/2~1/10 of the peak value of doping concentration.
A further improvement is that forming the p-type ring, and institute using individual photoetching and ion implantation technology in step 2
The formation process for stating p-type ring is located at before the formation process of the p-type trap.
A further improvement is that the protection in step 4 while forming the polysilicon gate in the termination environment
Epoxidation film surface forms polysilicon bus and forms polysilicon company in the protection ring oxidation film surface of the transition region
Line, each polysilicon gate are connected to the polysilicon bus, the width of the polysilicon line by the polysilicon line
Less than or equal to the width of the polysilicon gate.
Third contact hole described in step 5 is located at the top of the polysilicon bus, and the bottom of the third contact hole is worn
It crosses interlayer film and enters in the polysilicon bus and the bottom of the third contact hole rests in the polysilicon bus
Or the polysilicon bus is passed through.
The third is contacted by porose area using photoetching process when carrying out the P+ ion implanting of the contact zone P+ in step 5
Domain protection.
The present invention has done special design to the fill process of contact hole, and contact is specially filled using tungsten plug fill process
Hole, relative to the technique of the existing filling contact hole using metal AlCu or AlSiCu, tungsten plug fill process of the invention can be right
The contact hole of various depth-width ratios carries out pin-free filling, and such present invention can be had in transition region using specific charge flow region
The contact hole of higher depth-width ratio i.e. the second contact hole, the second contact hole can be also cross protection ring oxidation film and layer in the longitudinal direction
Between film, while can guarantee no pin hole.
Since the present invention can guarantee that the second contact hole does not have pin hole filling, so the present invention, which can be realized, is guaranteeing contact hole
Realize and protection ring oxidation film be set in transition region under conditions of good filling, conducive to protection ring oxidation film can be realized source region with
And the autoregistration injection in the region JFET, so as to make the present invention using the technique for saving photoetching level, i.e. the present invention can save shape
Shorten the production cycle at the photoetching process of source region and the area JFET so as to reduce cost of manufacture.
In addition, the lateral dimension of the second contact hole and distribution can be according to the need of device on the transverse structure in the face of vertical view
It is laid out, the second contact hole is very easily arranged so the present invention is able to achieve, can finally make the anti-snow of device
Collapse breakdown capability it is unaffected or improve.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Fig. 1 is the top view of the groove forming region of first embodiment of the invention superjunction devices；
Fig. 2 is the top view of the forming region of the p-type trap of first embodiment of the invention superjunction devices；
Fig. 3 is the top view of the forming region of the protection ring oxidation film of first embodiment of the invention superjunction devices；
Fig. 4 is the top view of the forming region of the polysilicon gate of first embodiment of the invention superjunction devices；
Fig. 5 is the top view of the forming region of the contact hole of first embodiment of the invention superjunction devices；
Fig. 6 is the forming region of source electrode and grid that the front metal layer of first embodiment of the invention superjunction devices is formed
Top view；
Fig. 7 is the schematic cross-section of the A1A2 line along Fig. 6 of first embodiment of the invention superjunction devices；
Fig. 8 is the schematic cross-section of the B1B2 line along Fig. 6 of first embodiment of the invention superjunction devices；
Fig. 9 is the schematic cross-section of the C1C2 line along Fig. 6 of first embodiment of the invention superjunction devices；
Figure 10 is the schematic cross-section of the D1D2 line along Fig. 6 of first embodiment of the invention superjunction devices；
Figure 11 is the top view of the forming region of the contact hole of second embodiment of the invention superjunction devices；
Figure 12 is the top view of the forming region of the contact hole of third embodiment of the invention superjunction devices；
Figure 13 is the top view of the forming region of the contact hole of fourth embodiment of the invention superjunction devices；
Figure 14 is the top view of the forming region of the contact hole of fifth embodiment of the invention superjunction devices；
Figure 15 is the flow chart of the manufacturing method of first embodiment of the invention superjunction devices；
Figure 16 A- Figure 16 D is the structure chart of the contact hole in first embodiment of the invention method in each step of tungsten plug technique.
Specific embodiment
First embodiment of the invention superjunction devices:
As shown in fig. 6, being the source electrode 7a and grid 7b of the front metal layer formation of first embodiment of the invention superjunction devices
Forming region top view；In order to more be apparent from the structure for illustrating first embodiment of the invention device, this place is also tied
It has closed Fig. 1 to Fig. 5 and Fig. 7 to be illustrated to Figure 10, detailed content is described as follows:
First embodiment of the invention superjunction devices is illustrated by taking super node MOSFET as an example, first embodiment of the invention superjunction
The intermediate region of device is charge flow region, and termination environment is surrounded on the periphery of the charge flow region, and transition region is located at the electricity
Between lotus flow region and the termination environment；First embodiment of the invention superjunction devices includes:
N-type epitaxy layer 1, the N-type epitaxy layer 1 carry out dry etching and form multiple grooves；It is filled in the trench by P
Type epitaxial layer and composition p-type column 2 form N-type column 1 by the N-type epitaxy layer 1 between each p-type column 2, by multiple alternatings
The super-junction structure of the N-type column 1 of arrangement and the p-type column 2 composition.The domain namely vertical view face figure of super-junction structure please refer to figure
The N-type column 1 and the p-type column 2 are shown clearly shown in 1, in Fig. 1 is alternately arranged structure.
The top of each p-type column 2 is all formed with a p-type trap 3 and each p-type trap 3 in the charge flow region
Extend to the surface of the N-type column 1 of corresponding 2 two sides of p-type column.
The surface of the super-junction structure described in the transition region is formed with the p-type for being looped around the side of the charge flow region
Ring 4；Each p-type trap 3 and the p-type ring 4 are in contact.The vertical view face structure of the p-type trap 3 and the p-type ring 4 please refers to figure
Shown in 2, Fig. 2 is only a partial top view, and actually p-type ring 4 can be in coil structure.In first embodiment of the invention, the P
Type trap 3 is identical with the process conditions of the p-type ring 4 and is formed simultaneously.In other embodiments, also can are as follows: 4 He of p-type ring
The process conditions of the p-type trap 3 independence and are formed separately each other.
It is formed with the first oxidation film on the super-junction structure surface for being formed with the p-type trap 3 and the p-type ring 4, is protected
Epoxidation film 103 is formed by carrying out chemical wet etching to first oxidation film, and the protection ring oxidation film 103 is by the charge
Flow region exposes and at least covers the partial region of the transition region, and the protection ring oxidation film 103 also extends into described
The termination environment is simultaneously all covered or is only exposed the outermost circumferential portion of the termination environment, the protection epoxy by termination environment surface
Change the side that film 103 is looped around the charge flow region.The specific structure of the protection ring oxidation film 103 please refers to shown in Fig. 7,
The forming region in the vertical view face of the protection ring oxidation film 103 please refers to shown in Fig. 3, and Fig. 3 middle line M1M2 has marked the protection
The forming region of epoxidation film 103, the left side of online M1M2 are the forming region of the protection ring oxidation film 103, online M1M2
The right side then not formed protection ring oxidation film 103, the left side of practical online M1M2 be the direction of direction termination environment, line M1M2
Right side be directed toward charge flow region direction.As shown in Figure 3 it is found that the protection ring oxidation film 103 is not by the p-type ring
4 are completely covered.
It is formed on the surface of the super-junction structure of the charge flow region by gate oxidation films and polysilicon gate 5a superposition
The forming region of the planar gate structure of formation, the polysilicon gate 5a is defined by photoetching process, and each polysilicon gate 5a covers
It covers the corresponding p-type trap 3 and channel is used to form by the surface of the polysilicon gate 5a p-type trap 3 covered.
106 autoregistration of source region is formed in the two sides the polysilicon gate 5a in the charge flow region.
Each polysilicon gate 5a structure in a strip shape and the length direction of each polysilicon gate 5a and the length of the groove
It is parallel to spend direction.
Polysilicon bus 5c, each polysilicon are formed on 103 surface of protection ring oxidation film of the termination environment
Grid 5a is connected to the polycrystalline by being formed in the polysilicon line 5b on 103 surface of protection ring oxidation film of the transition region
Silicon bus 5c, the polysilicon bus 5c, the polysilicon line 5b and the polysilicon gate 5a are formed sediment using identical polysilicon
Long-pending and polycrystalline silicon etching process is formed simultaneously；The width of the polysilicon line 5b is less than or equal to the width of the polysilicon gate 5a
Degree.
The vertical view face structure of the polysilicon bus 5c, the polysilicon line 5b and the polysilicon gate 5a please refer to figure
Shown in 4.
The surface of the p-type trap 3 of the charge flow region be formed with by N+ district's groups at source region 106, the source region 106
Referring to FIG. 10,106 autoregistration of source region is formed in the two sides the polysilicon gate 5a in the charge flow region；So institute
The forming region for stating source region 106 can be defined by polysilicon gate 5a and 103 autoregistration of protection ring oxidation film, wherein the guarantor
Retaining ring oxidation film 103 can will be protected outside the charge flow region, and the polysilicon gate 5a is then by the source region 106 from right
Standard is in the two sides of the polysilicon gate 5a, so first embodiment of the invention does not need additionally photoetching process to be used to define the source
Area 106 can save one layer of light shield for defining the source region 106.
As shown in figure 5, being formed with the first contact hole 6a in the charge flow region, second is formed in the transition region
Contact hole 6b is formed with third contact hole 6c, the first contact hole 6a, described second at the top of the polysilicon bus 5c
Contact hole 6b is identical with the lithographic etch process of the third contact hole 6c, i.e., three is simultaneously formed.
As shown in fig. 6, being all connected at the top of the first contact hole 6a and the second contact hole 6b by front metal
The source electrode 7a of layer composition.The grid 7b being made of front metal layer is all connected at the top of the third contact hole 6c.It is in Fig. 6
Display fabric source electrode 7a and grid 7b only depict forming region with wire frame, and are not filled by corresponding figure, in Fig. 7
Using filling graphical representation in the signal region of source electrode 7a and grid 7b.
The bottom of the first contact hole 6a pass through interlayer film 104 and the source region 106 and realize and the source region 106 with
And the contact of the p-type trap 3.
The surface that the second contact hole 6b is distributed in the transition region is covered with the part of the protection ring oxidation film 103
In region, the bottom of the second contact hole 6b passes through interlayer film 104 and the protection ring oxidation film 103 and realizes and the P
The contact of type ring 4.
The bottom of the third contact hole 6c passes through interlayer film 104 and enters in the polysilicon bus 5c and described the
The bottom of three contact hole 6c rests in the polysilicon bus 5c, in other embodiments also can be the third contact hole 6c
Bottom the polysilicon bus 5c is passed through.The first contact hole 6a, the second contact hole 6b are shown in Fig. 7 simultaneously
With the cross section structure of the third contact hole 6c, the cross section structure of the third contact hole 6c, Fig. 9 are then individually shown in Fig. 8
In then individually show the cross section structure of the second contact hole 6b, then individually show the first contact hole 6a's in Figure 10
Cross section structure.
The ratio of the depth and smallest lateral dimension that enable the first contact hole 6a is the first depth-width ratio, second contact
The depth of hole 6b and the ratio of smallest lateral dimension are the second depth-width ratio；It is high wide that second depth-width ratio is more than or equal to described first
Than the first contact hole 6a and the second contact hole 6b use tungsten plug process filling, utilize the tungsten plug technique device to hole
Covering power guarantee simultaneously realization to different aspect ratios the first contact hole 6a and the second contact hole 6b can
By filling.
As shown in fig. 6, the length direction of each first contact hole 6a structure in a strip shape and each first contact hole 6a
It is parallel with the length direction of the groove；The width of each first contact hole 6a is smallest lateral dimension.
It include the first contact hole 6a of a structure in a strip shape between the every two adjacent polysilicon gate 5a.
The vertical view face of each second contact hole 6b is rectangle, and the width of the second contact hole 6b is equal to described first and connects
The width of contact hole 6a includes that multiple second contact hole 6b arrange to be formed between the every two adjacent polysilicon line 5b
Array structure.Width of the width of the second contact hole 6b equal to the first contact hole 6a uses in the prior art
Structure can also be greater than the width of the first contact hole 6a in other embodiments using the width of the second contact hole 6b
Structure.Multiple second contact hole 6b between the every two adjacent polysilicon line 5b arrange the array junctions to be formed
Structure can be improved the area of the contact hole of total transition region, so as to improve the ability for collecting carrier of the transition region.
In first embodiment of the invention, it is desirable that guarantee that the second contact hole 6b is encased and guaranteed completely by the p-type ring 4
Outer side edges of the surplus more than or equal to 1 micron namely each second contact hole 6b along at the edge of the corresponding p-type ring 4
Interval between the edge on the outer side edges edge and the corresponding p-type ring 4 of inside and each second contact hole 6b is more than or equal to 1
Micron.
In first embodiment of the invention device, the interval of each second contact hole 6b and adjacent inter polysilicon is greater than etc.
In 0.2 micron；The polysilicon adjacent with the second contact hole 6b includes the polysilicon bus 5c, the polysilicon line 5b
With the polysilicon gate 5a.
As shown in Figure 10, P+ contact is formed in the bottom of each first contact hole 6a and each second contact hole 6b
Area 107.
The area JFET 102, the formation in the area JFET 102 are formed on the super-junction structure surface of the charge flow region
Region is defined by 103 autoregistration of protection ring oxidation film, and the area JFET 102 is an ion implanted region, with a void in Figure 10
Line indicates injection phase.
As shown in fig. 7, the N-type epitaxy layer 1 is formed in the surface of semiconductor substrate such as silicon substrate 101, silicon substrate 101 is adopted
With the structure of N-type heavy doping and it is located at the drain region of superjunction devices, is formed at the back side in drain region 101 and is made of metal layer on back
Drain electrode 105.
In first embodiment of the invention superjunction devices, parameter is carried out specifically by taking the super node MOSFET of a 600V as an example
It is bright:
Resistivity 0.001ohmcm~0.003ohmcm of the semiconductor substrate 101；The N-type epitaxy layer 1
Resistance 1ohmcm~2ohm.cm, with a thickness of 30 microns~70 microns, preferably 40 microns~60 microns.The present invention first is real
It applies in example, semiconductor substrate 101 is silicon substrate, and the N-type epitaxy layer 1 is silicon epitaxy layer.
Compare shown in Fig. 9 and Figure 10 it is found that the deielectric-coating that the first contact hole 6a is passed through is only interlayer film 104, and
The deielectric-coating that second contact hole 6b is passed through then includes interlayer film 104 and protection ring oxidation film 103, therefore the first contact hole 6a
The deielectric-coating passed through is thinner, since the first contact hole 6a and the second contact hole 6b uses identical chemical wet etching
Technique is formed simultaneously, and in first embodiment of the invention, the first contact hole 6a needs after passing through interlayer film 104 to bottom
Silicon, that is, N-type epitaxy layer 1 silicon carry out over etching, while its erosion amount needs to meet or exceed the depth of the source region 106；
And the second contact hole 6b then only needs to pass through interlayer film 104 and protection ring oxidation film 103 to expose the p-type ring 4
Surface, whether the second contact hole 6b carry out over etching and not restricted to the silicon of bottom.
In first embodiment of the invention, the interlayer film 104 with a thickness of 8000 angstroms~10000 angstroms, the protection epoxy
Change film with a thickness of 8000 angstroms~10000 angstroms.When the width of the first contact hole 6a takes 0.6 micron, then described second connect
The width of contact hole 6b is also 0.6 micron.
In first embodiment of the invention superjunction devices, especially use tungsten plug technique come fill the first contact hole 6a and
The second contact hole 6b is guaranteed using the tungsten plug technique device to hole covering power while being realized to the institute with different aspect ratios
State the reliable filling of the first contact hole 6a and the second contact hole 6b.For being filled out in tungsten plug technique and prior art using AlCu
The additional symbols for filling the technique of contact hole are as follows:
1, when W not being used to fill in technique, when general depth-width ratio is greater than 0.5, just it is easy to appear ALCu pin hole, this pin hole
In the presence of may cause the metal local ALCU metal foil in contact hole, cause the integrity problem of product.
2, in device of the embodiment of the present invention, after filling in technique using W, since tungsten plug technique has good cover to contact hole
Lid ability, therefore the surface of a planarization can be formed at the top of contact hole after tungsten plug process filling contact hole, in this way subsequent
When progress ALCu deposits to form front metal layer, AlCu is deposited over through planarization surface, therefore the thickness of ALCU is everywhere
The problem of being uniform, being not in the metal local ALCU metal foil in contact hole, so that also ensure that contact hole can
By property.
3, technique itself to be filled in for W, is in fact usually to have pin hole, W plug center generally has a very thin seam,
Intermediate may have empty (Void).But this does not influence the reliability of contact hole, because when ALCu is deposited, in a more flat face
On, W, which fills in some intermediate Void, to be had an impact, and gains in depth of comprehension crack in W plug is generally just filled in when Ti and TiN is deposited, ALCU energy
Enough deposits well.
By using tungsten plug technique, contact hole for depth-width ratio less than 10 is centainly not in filling problem, the present invention
In first embodiment: the width of the first contact hole 6a be 0.6 micron, interlayer film 104 with a thickness ofIt is so described
The depth-width ratio of first contact hole 6a is 1.33；If thick field oxide film, that is, protection ring oxidation film 103 with a thickness ofTransition
The contact hole in area, that is, second contact hole 6b minimum dimension, that is, width is 0.6 micron, then at this contact hole depth-width ratio
It is 2.67, both less than 10, therefore filling problem is not present, is able to achieve pin-free filling.
Second embodiment of the invention superjunction devices:
As shown in figure 11, be second embodiment of the invention superjunction devices contact hole forming region top view；This hair
In place of the difference of bright second embodiment superjunction devices and first embodiment of the invention superjunction devices are as follows: described second in Figure 11 connects
Contact hole 6a is all placed in the transition region for being formed with the protection ring oxidation film 103, namely on the vertical view face of Figure 11
All the second contact hole 6a are the left side of boundary line M1M2, and structure shown in Figure 12 facilitates design.
Third embodiment of the invention superjunction devices:
As shown in figure 12, be third embodiment of the invention superjunction devices contact hole forming region top view；This hair
In place of the difference of bright 3rd embodiment superjunction devices and first embodiment of the invention superjunction devices are as follows: connect in Figure 12 by described second
Contact hole 6a is expanded in the transition region of no protection ring oxidation film 103, as shown in 13 region of virtual coil in Figure 12
The second contact hole 6a, the bottom of the second contact hole 6b in the partial region is realized across the interlayer film 104
With the contact of the p-type ring 4.Structure shown in Figure 12 can be by the maximum area of the second contact hole 6a.
Fourth embodiment of the invention superjunction devices:
As shown in figure 13, be fourth embodiment of the invention superjunction devices contact hole forming region top view；This hair
In place of the difference of bright fourth embodiment superjunction devices and first embodiment of the invention superjunction devices are as follows: polysilicon described in Figure 13 connects
It the width of line 5b and the polysilicon gate 5a of same size and is directly extended to form by the polysilicon gate 5a.
Fifth embodiment of the invention superjunction devices:
As shown in figure 14, be fifth embodiment of the invention superjunction devices contact hole forming region top view；This hair
In place of the difference of bright 5th embodiment superjunction devices and fourth embodiment of the invention superjunction devices are as follows: in Figure 14 every two it is adjacent
The first contact hole 6a between the polysilicon gate 5a including two or more structures in a strip shape arranged in parallel is arranged.
In other embodiments, also can are as follows: between the every two adjacent polysilicon gate 5a include multiple vertical view faces be rectangle institute
It states the first contact hole 6a and arranges the array structure to be formed.
The manufacturing method of first embodiment of the invention superjunction devices:
As shown in figure 15, be first embodiment of the invention superjunction devices manufacturing method flow chart；The present invention first is real
The manufacturing method of a superjunction devices is applied for manufacturing mentioned-above first embodiment of the invention superjunction devices, in superjunction devices
Between region be charge flow region, termination environment is surrounded on the periphery of the charge flow region, and transition region is located at the charge flow region
Between the termination environment；Include the following steps:
Step 1: progress first time photoetching process defines the formation area of groove as shown in Figure 1, providing N-type epitaxy layer 1
Domain carries out dry etching to the N-type epitaxy layer 1 later and forms multiple grooves.
Filling p-type epitaxial layer forms p-type column 2 in the trench, by the N-type epitaxy layer between each p-type column 2
1 composition N-type column 1, the super-junction structure being made of multiple alternately arranged N-type columns 1 and the p-type column 2.
In first embodiment of the invention method, it is described in detail so that the superjunction devices of production is super node MOSFET as an example:
The N-type epitaxy layer 1 is formed on the surface of semiconductor substrate 101, and the semiconductor substrate 101 uses the knot of N-type heavy doping
Structure；Preferably, the N-type epitaxy layer 1 is silicon epitaxy layer, and the semiconductor substrate 101 is silicon substrate namely usually said silicon
Piece or silicon wafer.The drain region of super node MOSFET is generally formed in the back side of half conductive substrate 101, therefore directlys adopt heavy doping
Semiconductor substrate 1, in first embodiment of the invention method, the resistivity 0.001ohmcm of the semiconductor substrate 101~
0.003ohm·cm；Resistance 1ohmcm~2ohm.cm of the N-type epitaxy layer 1, with a thickness of 30 microns~70 microns, preferably
It is 40 microns~60 microns；P-N columnar region, that is, super-junction structure region: the source and drain breakdown voltage BVds of respective devices be 600V~
The height of super-junction structure is 35 microns~45 microns when 700V.In first embodiment of the invention method, it is ensured that the groove and
Such as be more than 5 microns of buffer layer with certain thickness between the semiconductor substrate 101 of high concentration, with retainer member have compared with
Good power of resisting voltaic impingement, buffer layer are generally directly formed with the N-type epitaxy layer 1 for being located at channel bottom.
In first embodiment of the invention method, carrying out the first time photoetching process further includes before in the N-type extension
Layer surface forms the step of first medium film, successively to the first medium film and described after the first time photoetching process
N-type epitaxy layer 1 carries out dry etching and forms multiple grooves.
Fill in the trench carry out chemical mechanical grinding (CMP) technique after the p-type epitaxial layer will be outside the N-type
The p-type epitaxial layer removal for prolonging 1 surface of layer, is only filled with the p-type epitaxial layer in the corresponding groove 1 and forms institute
State p-type column 2；The first medium film removes after the completion of the chemical mechanical milling tech or part retains.
In first embodiment of the invention method, the composition material of the first medium film and corresponding process energy material
Following option:
The first option are as follows: the first medium film is single oxidation film for example more than the oxidation film of 1 micron thickness, should
Oxidation film can be in etching groove as hard mask, and groove leaves after being formed there are also certain thickness oxidation film, such as thickness
It in the oxidation film of 0.1 micron~0.2 micron thickness, fills and completes in extension, during carrying out CMP, the oxidation film is as CMP
When N-type epitaxy layer 1 protective layer cause electric leakage or quality problems so that the silicon at this will not form defect in a cmp process.
Second of option are as follows: the first medium film is by one layer of 0.1 micron~0.15 micron thick oxidation film, a thickness
0.1 micron~0.2 micron of SIN film and one thickness of top be greater than 1 micron~oxidation film composition, as multi-layer film structure；This
Sample can preferably control uniformity in the production process: for example after the completion of etching groove, at least maintaining part SIN film and stay
On the oxidation film under it, being removed before epitaxial growth, then the SIN film, the uniformity of oxidation film is good before such epitaxial growth,
The uniformity for carrying out the CMP of extension can also improve.Further improvement to above-mentioned multi-layer film structure is that first layer oxidation film is
It is formed by thermal oxide, in this way further improvement uniformity.
Step 2: as shown in Fig. 2, carrying out the shape that second of photoetching process defines p-type trap 3 in the charge flow region
At region, P-type ion is carried out later and injects to form the p-type trap 3.
The top of each p-type column 2 is all formed with the p-type trap 3 and each p-type trap in the charge flow region
3 extend to the surface of the N-type column 1 of corresponding 2 two sides of p-type column.
The table of super-junction structure while forming p-type trap 3 using identical technique in the transition region
Face forms the p-type ring 4 for being looped around the side of the charge flow region；Each p-type trap 3 and the p-type ring 4 are in contact.
It further include that annealing process, the lehr attendant are carried out to the p-type trap 6 after the completion of the P-type ion injection of the p-type trap 6
The temperature of skill is 1000 DEG C or more, the time is 30 minutes or more.
The process conditions of the p-type trap 6 need to meet the requirement of device threshold voltage, for threshold voltage requirements at 2 volts
~4 volts of device, can use B 30-100KEV, and the process conditions of 3-10E13/cm2, i.e. implanted dopant are boron (B), injection
Energy is 30Kev~100Kev, implantation dosage 3E13cm-2~10E13cm-2；To guarantee that device occurs in breakdown voltage simultaneously
When, Punchthrough (Punch through) not occur at channel, otherwise will cause that element leakage is big, and breakdown voltage is lower.
Step 3: as shown in figure 3, being carried out on the super-junction structure surface for being formed with the p-type trap 3 and the p-type ring 4
First oxide growth carries out third time photoetching process and defines the etch areas of first oxidation film, later to described the
One oxidation film performs etching to form protection ring oxidation film 103, the protection ring oxidation film 103 by the charge flow region expose with
And at least cover the partial region of the transition region, the protection ring oxidation film 103 also extends into the termination environment surface simultaneously
The termination environment is all covered or only exposes the outermost circumferential portion of the termination environment, the protection ring oxidation film 103 is surround
In the side of the charge flow region.
Preferably, thermal oxidation technology of first oxidation film 7 using temperature higher than 800 DEG C is formed, in this way can be in Si-
Dangling bonds and unstable interfacial state are reduced in the interface SiO2, further increase the ability that voltage is born in terminal area, improve device
The consistency of the breakdown voltage of part.The thickness of first oxidation film 7 needs big according to device BVds, that is, source and drain breakdown voltage
Small to be set, general BVds is bigger, and the thickness needs of first oxidation film 7 are thicker, what general 600V or more device needed
The thickness of first oxidation film 7 is more than 0.8 μm.
It is that the comprehensive first time N-type ion of autoregistration condition progress is infused in the electricity with the protection ring oxidation film 103
102 domain of the area JFET is formed in lotus flow region, while in the termination environment except 103 overlay area of protection ring oxidation film
Or outside forms the first N-type of terminal injection region.
In first embodiment of the invention method, due to there is protection ring oxidation film 7 to be protected transition region and termination environment,
Therefore JFET injection can carry out in the case where no photoetching, the cost of photoetching process saved, because if terminal area
It is filled with JFET, device BVds can significantly be caused to decline, if JFET is injected into the region of transition region, the anti-of device can be reduced
Rush of current ability.
In first embodiment of the invention method, the technique of the corresponding first time N-type ion injection in the region JFET
Condition is phosphorus (phos), 30-100Kev 1-4E13/cm2, namely: implanted dopant is phosphorus, Implantation Energy be 30Kev~
100Kev, implantation dosage 1E13cm-2~4E13cm-2；Alternatively, the corresponding first time N of JFET region described in step 3
Type ion implanting is 30Kev~60Kev by Implantation Energy and Implantation Energy is 1Mev~1.5Mev the combination injected twice and
At the injection of high-energy can further lower the ratio conducting resistance of device, and improve charge balance around p-type trap 6, mention
The Bvds of high device, it is available to carry out experimental verification: for 600V device, Bvds can improve 10V~20V.
Step 4: carrying out the 4th time as shown in figure 4, sequentially form the first layer polysilicon of gate oxidation films and N-type heavy doping
Photoetching process defines the forming region of polysilicon gate 5a, performs etching to form polysilicon gate to the first layer polysilicon later
5a, each polysilicon gate 5a are planar gate structure, and each polysilicon gate 5a covers the corresponding p-type trap 3 and described
The surface of the p-type trap 3 of polysilicon gate 5a covering is used to form channel.
103 surface of protection ring oxidation film while forming the polysilicon gate 5a in the termination environment forms more
Crystal silicon bus 5c and the transition region 103 surface of protection ring oxidation film formed polysilicon line 5b, it is each described more
Crystal silicon grid 5a is connected to the polysilicon bus 5c by the polysilicon line 5b, and the width of the polysilicon line 5b is less than
Equal to the width of the polysilicon gate 5a.The energy when the width of the polysilicon line 5b is less than the width of the polysilicon gate 5a
Conveniently so that the contact hole distributed areas of transition region expand, and it is unlikely to that grid and source metal is caused to leak electricity.It should be polysilicon
Bus (gate bus) can also be covered or be partially covered on the protection ring deielectric-coating of transition region, can also be in terminal area
There is the polycrystalline being mutually isolated for the field plate as the gentle electric field of terminal.
It is that autoregistration condition carries out comprehensive second of N-type with the polysilicon gate 5a and the protection ring oxidation film 103
Polysilicon gate 5a two sides of the ion implanting in the charge flow region are respectively formed source region 106, while in the protection
In the termination environment except 103 overlay area of epoxidation film or outside forms the second N-type of terminal injection region.
The second N-type of terminal injection region can be used to prevent the surface transoid of termination environment, and the breakdown for preferably improving device is special
The stability of property.The second N-type of terminal injection region can also be formed in the termination environment of the most peripheral of device, also become cut-off region.
Preferably, the implanted dopant of corresponding second of N-type ion injection of the source region 106 is arsenic, phosphorus, Huo Zhewei
The combination of arsenic and phosphorus, the process conditions of arsenic injection when including arsenic injection in second of N-type ion injection are as follows: Implantation Energy is
30Kev~100Kev, implantation dosage 1E15cm-2~5E15cm-2。
Step 5: as shown in fig. 6, deposit interlayer film 104, carry out the 5th photoetching process define the first contact hole 6a,
The forming region of second contact hole 6b and third contact hole 6c；It performs etching to form the first contact hole 6a, described later
The opening of two contact hole 6b and the third contact hole 6c；In the first contact hole 6a, the second contact hole 6b and described
Filling metal forms the first contact hole 6a, the second contact hole 6b and the third and connects in the opening of third contact hole 6c
Contact hole 6c.
The bottom of the first contact hole 6a passes through the interlayer film 104 and the source region 106 and realizes and the source region
106 and the p-type trap 3 contact.
The surface that the second contact hole 6b is distributed in the transition region is covered with the part of the protection ring oxidation film 103
In region, the bottom of the second contact hole 6b passes through interlayer film 104 and the protection ring oxidation film 103 and realizes and the P
The contact of type ring 4.
The third contact hole 6c is located at the top of the polysilicon bus 5c, and the bottom of the third contact hole 6c passes through
Interlayer film 104 simultaneously enters in the polysilicon bus 5c and to rest on the polysilicon total for the bottom of the third contact hole 6c
It is passed through in line 5c or by the polysilicon bus 5c.
The ratio of the depth and smallest lateral dimension that enable the first contact hole 6a is the first depth-width ratio, second contact
The depth of hole 6b and the ratio of smallest lateral dimension are the second depth-width ratio；It is high wide that second depth-width ratio is more than or equal to described first
Than the first contact hole 6a, the second contact hole 6b and the third contact hole 6c use tungsten plug process filling, utilize
The tungsten plug technique device to hole covering power guarantees realization simultaneously to the first contact hole 6a with different aspect ratios and described
The reliable filling of second contact hole 6b.
It is the contact hole in first embodiment of the invention method in each step of tungsten plug technique as shown in Figure 16 A to Figure 16 D
Structure chart, tungsten plug technique include the following steps:
As shown in Figure 16 A, it is contacted in contact hole, that is, first contact hole 6a, the second contact hole 6b and the third
After the completion of the opening of hole 6c, one layer of Ti and TiN barrier layer 201 is deposited.Later, as shown in fig 16b, deposit tungsten 202 will connect
Contact hole is filled up, if the opening width of contact hole is 0.6 micron, the thickness of tungsten 202 can be 4000 angstroms.Later, as schemed
Shown in 16C, carries out plasma dry and return carving technology for all removals of the metal on the surface outside contact hole.Figure 16 D is subsequent later
The front metal layer 203 formed in step 6, front metal layer 203 will do it graphical formation source electrode 7a and grid 7b.
In first embodiment of the invention method, it can make the contact hole of different aspect ratios that can realize needleless using tungsten plug technique
Hole filling.
In first embodiment of the invention method, interlayer film 104 is the combination of the oxidation film and bpsg film that undope.Interlayer film
104 with a thickness ofSince the second contact hole 6b realizes the source electrode 7a that subsequent front metal layer is formed
With the connection in 6 region of protection ring p-type trap in transition region, it ensure that the device terminal structure of same size is implemented in the present invention first
Technique is able to bear voltage same as prior art in example method.
In the etching of contact hole, the etching of the first contact hole 6a in charge flow region is needed the N+ of its bottom i.e. source
Area 106, which etches away, needs to carry out silicon over etching, and silicon over etching amount can be specific to need according to described at 2000 angstroms to 4000 angstroms
Injection condition, that is, the implantation dosage and Implantation Energy of corresponding second of N-type ion injection of source region 106 is determined；In transition region
In, the second contact hole 6b only needs guiding through the interlayer film 104 and the protection ring oxidation film 103, can without silicon over etching,
Silicon over etching amount is 0 angstrom to 500 angstroms.
It, will not be because of source region 106 since the first contact hole 6a in charge flow region breaks through the N+ i.e. range of source region 106
Polysilicon gate 5a exterior domain it is comprehensive injection and cause the contact problems between p-type trap 3 and metal, ensure that electrology characteristic
It is normal.
Metal is filled out after the opening of the first contact hole 6a, the second contact hole 6b and the third contact hole 6c are formed
It further include carrying out P+ ion implanting in the bottom of the first contact hole 6a and the second contact hole 6b to form P+ contact before filling
The step of area 107.It carries out using photoetching process by the area third contact hole 6c when the P+ ion implanting of the contact zone P+ 107
Domain protection.The contact resistance of the first contact hole 6a and the second contact hole 6b are reduced by the contact zone P+ 107.Compared with
Good to be, the impurity of the p-type injection of the contact zone P+ 107 here is the combination of B, BF2 or B and BF2, generally injection energy
Amount is in 30Kev~80Kev, and implantation dosage is in 1E15cm-2~3E15cm-2, the anti-of device can be improved by optimizing the injection condition
Rush of current ability.The softness of the reversely restoring process of body diode in order to better improve can also reduce the contact zone P+
The energy and dosage of 107 p-type injection, such as energy can take BF2,5Kev~40KEV, 5E14cm-2~2E15cm-2, dosage
Selection can make to guarantee to be formed the lowest dose level of Ohmic contact, the selection of energy will mainly consider ion implantation device
Ability.
It deposits to form front metal layer Step 6: carrying out front metal, carries out the 6th photoetching process and define grid 7b
With the forming region of source electrode 7a, later the front metal layer is performed etching to form the grid 7b and the source electrode 7a, institute
Each source region 106 and the corresponding p-type trap 3 stated in charge flow region pass through the identical first contact hole 6a in top
It is connected to the source electrode 7a, the p-type ring 4 in the transition region is connected to institute also by the second contact hole 6b at top
Source electrode 7a is stated, the polysilicon gate 5a is connected to grid 7b by the third contact hole 6c.
The material of the front metal layer 14 can be ALSi, AlSiCu, can there is barrier layer, and barrier layer can be Ti/TIN, or
Person TIN.The overall thickness of the front metal layer 14 is generally at 4 μm~6 μm.
Later by the semiconductor substrate 101 carry out back thinning and by be thinned after be formed in the semiconductor substrate 101
In N+ district's groups at drain region, drain region can be directly made of the semiconductor substrate 101 of heavy doping, or be served as a contrast by the semiconductor
Bottom 101 plus N-type heavy doping ion injection composition.Back-side gold is deposited at the back side that the semiconductor substrate 101 is drain region 101 later
Belong to layer and forms drain electrode 105.
First embodiment of the invention superjunction devices is formed after above-mentioned steps.
In manufacturing process on first embodiment of the invention method is corresponding, by using six photoetching, including ditch
Slot photoetching, that is, first time photoetching, p-type trap photoetching are second of photoetching, protection ring oxidation film photoetching i.e. third time photoetching, polycrystalline light
Carve is that fourth lithography, contact hole photoetching i.e. the 5th time photoetching and front metal photoetching i.e. the 6th time photoetching realize the prior art
Needing 8 photoetching, just obtainable device namely first embodiment of the invention method save JFET injection photoetching and source injection
Photoetching.So first embodiment of the invention method reduces manufacturing cost.In production in order to guarantee the stability produced,
Can increase before trench lithography 0 layer of photoetching and mark layer photoetching, it is therefore an objective to formed pair by lithography and etching
Fiducial mark note and alignment precision test badge；0 layer of technical process can be depositOxidation film, photoetching later will aoxidize
Film is etching silicon again after etching awayForm step；In order to preferably be protected to the front of device, improve
The reliability of device can deposit passivation layer after front metal pattern formation again, pass through passivation layer lithography and etching later
The passivation layer for the metallic region opened will be needed to etch away.And passivation layer protection device, passivation layer are left in other region
It can be SIN, SION, SIO2, general thickness is at 0.8 μm~2 μm.
By using tungsten plug technique, contact hole for depth-width ratio less than 10 is centainly not in filling problem, the present invention
In first embodiment: the width of the first contact hole 6a be 0.6 micron, interlayer film 104 with a thickness ofIt is so described
The depth-width ratio of first contact hole 6a is 1.33；If thick field oxide film, that is, protection ring oxidation film 103 with a thickness ofTransition
The contact hole in area, that is, second contact hole 6b minimum dimension, that is, width is 0.6 micron, then at this contact hole depth-width ratio
It is 2.67, both less than 10, therefore filling problem is not present, is able to achieve pin-free filling.
While the distributed areas of i.e. the second contact hole 6b of transition region contact hole are amplified, need to guarantee that p-type ring wraps completely
Live in each contact hole 6b, the capacity generally encased need 1 micron or more.
In first embodiment of the invention method, p-type ring is the same process using p-type trap 3 and is formed simultaneously in step 2.
In other embodiments method, also can are as follows: the p-type ring 4, and the P are formed using individual photoetching and ion implantation technology
The formation process of type ring 4 is located at before the formation process of the p-type trap 3.Such as: according to the requirement of design, carry out primary independent
P-type ring 4 photoetching and injection, such as trench fill completion after, first carry out p-type ring 4 photoetching and injection, Implantation Energy
Can be more preferable than the Implantation Energy of p-type trap 3, and pyroprocesses all thereafter is carried out, so that the knot of the p-type ring 4 is than p-type trap
3 knot is deeper, further improves the reliability of device, and the softness factor that the body diode reverse for increasing device is restored, reason
Are as follows: knot is deepened, and the distance that the hole being collected into reaches high concentration p-type contact zone increases, so that body diode reverse be made to restore
The softness factor increases.The implantation dosage of p-type ring 4 also can according to need, and be less than, more than or equal to the dosage of p-type trap 3.
In other embodiments method, also it can be divided into two when it is the P+ ion implanting of the contact zone P+ 107 that contact hole, which injects,
Secondary injection is formed, such as after the completion of contact hole technique, can first carry out primary comprehensive injection, the energy and dosage of use
It is set according to the demand of transition region, carries out a photoetching later, i.e. the second contact hole 6b of the contact hole of transition region is protected
Firmly, only contact hole i.e. the first contact hole 6a of charge flow region is injected, it at this moment can be according to charge flow region to contact
The requirement of the p type impurity in area 107 is set, technique in this way, so that the p-type of the contact zone 107 in two regions is miscellaneous
Matter can be set according to respective demand, can advanced optimize the performance of device.
The manufacturing method of second embodiment of the invention superjunction devices:
It is that the present invention second is implemented in place of the difference of second embodiment of the invention method and first embodiment of the invention method
The contact zone P+ 107 of contact hole and contact hole bottom is formed in example method using following steps:
The interlayer film 104 is made of oxidation film, and etching forms the first contact hole 6a, described second connects in step 5
The etching that oxidation film is first carried out when the opening of contact hole 6b and the third contact hole 6c, the institute in the region the first contact hole 6a
The etching that interlayer film 104 completely removes and stops oxidation film when exposing the source region 106 of bottom is stated, epitaxial film materials are carried out
That is the etching of silicon materials.
The epitaxial layer of the bottom of first contact hole 6a described in when carrying out the etching of the epitaxial film materials generates over etching, together
The oxidation film in the region Shi Suoshu the second contact hole 6b can partial etching；Oxidation film in the region the second contact hole 6b is not complete
The P+ ion implanting that the contact zone P+ 107 is carried out before full removal, contacts the P+ in the region the second contact hole 6b
The peak value of the P+ ion implanting in area 107 is located in oxidation film, so that the first contact hole 6a, the second contact hole 6b and institute
After the opening and metal filling completely of stating third contact hole 6c, the contact zone P+ 107 of the bottom the second contact hole 6b
Doping concentration peak value be less than the bottom the first contact hole 6a the contact zone P+ 107 doping concentration peak value.
Positioned at the oxidation of the second contact hole 6b sections bottom when stating the P+ ion implanting of the contact zone P+ 107 by adjusting
The thickness of film adjusts the doping concentration of the contact zone P+ 107 of the bottom the second contact hole 6b, and makes second contact
The peak value of the doping concentration of the contact zone P+ 107 of the hole bottom 6b is the contact zone P+ of the bottom the first contact hole 6a
The 1/2~1/10 of the peak value of 107 doping concentration.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (15)
1. the intermediate region of a kind of superjunction devices, superjunction devices is charge flow region, termination environment is surrounded on the charge flow region
Periphery, transition region is between the charge flow region and the termination environment；It is characterised by comprising:
N-type epitaxy layer, the N-type epitaxy layer carry out dry etching and form multiple grooves；It is filled in the trench by p-type extension
Layer simultaneously forms p-type column, N-type column is formed by the N-type epitaxy layer between each p-type column, by multiple alternately arranged N
The super-junction structure of type column and p-type column composition；
The top of each p-type column is all formed with a p-type trap in the charge flow region and each p-type trap extends to pair
The surface of the N-type column for the p-type column two sides answered；
The surface of the super-junction structure described in the transition region is formed with the p-type ring for being looped around the side of the charge flow region；
Each p-type trap and the p-type ring are in contact；
It is formed with the first oxidation film on the super-junction structure surface for being formed with the p-type trap and the p-type ring, protects epoxidation
Film by first oxidation film carry out chemical wet etching formed, the protection ring oxidation film by the charge flow region expose with
And at least cover the partial region of the transition region, the protection ring oxidation film also extends into the termination environment surface and by institute
It states termination environment all to cover or only expose the outermost circumferential portion of the termination environment, the protection ring oxidation film is looped around the electricity
The side of lotus flow region；
The surface of the p-type trap of the charge flow region be formed with by N+ district's groups at source region, the injection zone of the source region
It is defined by the protection ring oxidation film autoregistration；
It is formed with the first contact hole in the charge flow region, is formed with the second contact hole in the transition region, described first
Contact hole is identical with the lithographic etch process of second contact hole；
The source electrode being made of front metal layer is all connected at the top of first contact hole and second contact hole；
The bottom of first contact hole passes through interlayer film and the source region and realizes and the source region and the p-type trap connect
Touching；
The surface that second contact hole is distributed in the transition region is covered in the partial region of the protection ring oxidation film, institute
The bottom for stating the second contact hole passes through interlayer film and the protection ring oxidation film and realization and the contact of the p-type ring；
The ratio of the depth and smallest lateral dimension that enable first contact hole is the first depth-width ratio, the depth of second contact hole
Degree and the ratio of smallest lateral dimension are the second depth-width ratio；Second depth-width ratio is more than or equal to first depth-width ratio, described
First contact hole and second contact hole all use tungsten plug process filling, are guaranteed using the tungsten plug technique device to hole covering power
The reliable filling to first contact hole and second contact hole with different aspect ratios is realized simultaneously.
2. superjunction devices as described in claim 1, it is characterised in that: in the table of the super-junction structure of the charge flow region
Face, which is formed with, is superimposed the planar gate structure formed by gate oxidation films and polysilicon gate, and the forming region of the polysilicon gate passes through light
Carving technology definition, each polysilicon gate cover the corresponding p-type trap and the p-type trap that is covered by the polysilicon gate
Surface is used to form channel；
The source region autoregistration is formed in the polysilicon gate two sides in the charge flow region；
The length direction of the length direction and the groove of each polysilicon gate structure in a strip shape and each polysilicon gate is flat
Row；
Protection ring oxidation film surface in the termination environment is formed with polysilicon bus, and each polysilicon gate passes through to be formed
The polysilicon bus, the polysilicon are connected in the polysilicon line of the protection ring oxidation film surface of the transition region
Bus, the polysilicon line and the polysilicon gate are using identical polycrystalline silicon deposit and polycrystalline silicon etching process while shape
At；The width of the polysilicon line is less than or equal to the width of the polysilicon gate.
3. superjunction devices as claimed in claim 2, it is characterised in that: each first contact hole structure in a strip shape and each described
The length direction of first contact hole is parallel with the length direction of the groove；The width of each first contact hole is minimum lateral
Size；
Include between the every two adjacent polysilicon gates structure in a strip shape first contact hole or two with
First contact hole of upper structure in a strip shape arranged in parallel or multiple vertical view faces are that first contact hole of rectangle is arranged
Arrange the array structure formed；
The vertical view face of each second contact hole is rectangle, and the width of second contact hole is more than or equal to first contact hole
Width, include second contact hole or including by multiple described between the every two adjacent polysilicon lines
Second contact hole arranges the array structure to be formed.
4. superjunction devices as claimed in claim 3, it is characterised in that: the p-type ring encases second contact hole completely
And the surplus guaranteed is more than or equal to 1 micron.
5. superjunction devices as claimed in claim 2, it is characterised in that: be formed with third at the top of the polysilicon bus and connect
Contact hole, first contact hole are identical with the lithographic etch process of the third contact hole；
The grid being made of front metal layer is all connected at the top of the third contact hole；
The bottom of the third contact hole passes through interlayer film and enters in the polysilicon bus and the third contact hole
Bottom rests in the polysilicon bus or passes through the polysilicon bus.
6. superjunction devices as described in claim 1, it is characterised in that: second contact hole, which also extends, is distributed to the transition
The surface in area does not cover in the partial region of the protection ring oxidation film, the bottom of second contact hole in the partial region
It is realized and the contact of the p-type ring across the interlayer film.
7. superjunction devices as described in claim 1, it is characterised in that: in each first contact hole and each second contact
The bottom in hole is formed with the contact zone P+.
8. superjunction devices as described in claim 1, it is characterised in that: the p-type trap is identical with the process conditions of the p-type ring
And it is formed simultaneously；Alternatively, the process conditions of the p-type ring and the p-type trap independence and are formed separately each other.
9. superjunction devices as described in claim 1, it is characterised in that: on the super-junction structure surface of the charge flow region
It is formed with the area JFET, the forming region in the area JFET is defined by the protection ring oxidation film autoregistration.
10. a kind of manufacturing method of superjunction devices, the intermediate region of superjunction devices is charge flow region, and termination environment is surrounded on described
The periphery of charge flow region, transition region is between the charge flow region and the termination environment；It is characterised in that it includes as follows
Step:
Step 1: providing N-type epitaxy layer, the forming region that first time photoetching process defines groove is carried out, later to the N-type
Epitaxial layer carries out dry etching and forms multiple grooves；
Filling p-type epitaxial layer forms p-type column in the trench, forms N by the N-type epitaxy layer between each p-type column
Type column, the super-junction structure being made of multiple alternately arranged N-type columns and the p-type column；
Step 2: carrying out the forming region that second of photoetching process defines p-type trap in the charge flow region, carry out later
P-type ion is injected to form the p-type trap；
The top of each p-type column is all formed with the p-type trap in the charge flow region and each p-type trap extends to
The surface of the N-type column of corresponding p-type column two sides；
The surface of super-junction structure while forming the p-type trap using identical technique in the transition region is formed
It is looped around the p-type ring of the side of the charge flow region；Each p-type trap and the p-type ring are in contact；
Step 3: the first oxide growth is carried out on the super-junction structure surface for being formed with the p-type trap and the p-type ring,
The etch areas that third time photoetching process defines first oxidation film is carried out, first oxidation film is performed etching later
Protection ring oxidation film is formed, the charge flow region is exposed and at least by the portion of the transition region by the protection ring oxidation film
Subregion covering, the protection ring oxidation film also extend into the termination environment surface and all cover the termination environment or only will
The outermost circumferential portion of the termination environment is exposed, and the protection ring oxidation film is looped around the side of the charge flow region；
Comprehensive first time N-type ion, which is carried out, as autoregistration condition using the protection ring oxidation film is infused in the charge flow region
The middle region formation JFET, at the same in the termination environment except protection ring oxidation film overlay area or outside formed terminal
First N-type injection region；
Step 4: sequentially forming the first layer polysilicon of gate oxidation films and N-type heavy doping, carries out fourth lithography technique and define
The forming region of polysilicon gate performs etching to form polysilicon gate to the first layer polysilicon later, each polysilicon gate
The p-type trap for covering the corresponding p-type trap for planar gate structure, each polysilicon gate and being covered by the polysilicon gate
Surface be used to form channel；
Comprehensive second of N-type ion is carried out as autoregistration condition using the polysilicon gate and the protection ring oxidation film to be infused in
The polysilicon gate two sides in the charge flow region are respectively formed source region, while in protection ring oxidation film overlay area
Except the termination environment in or outside formed the second N-type of terminal injection region；
Step 5: deposit interlayer film, carries out the 5th photoetching process and defines the first contact hole, the second contact hole and third contact
The forming region in hole；It performs etching to form first contact hole, second contact hole and the third contact hole later
Opening；Filling metal is formed described in the opening of first contact hole, second contact hole and the third contact hole
First contact hole, second contact hole and the third contact hole；
The bottom of first contact hole passes through the interlayer film and the source region and realizes and the source region and the p-type trap
Contact；
The surface that second contact hole is distributed in the transition region is covered in the partial region of the protection ring oxidation film, institute
The bottom for stating the second contact hole passes through interlayer film and the protection ring oxidation film and realization and the contact of the p-type ring；
The ratio of the depth and smallest lateral dimension that enable first contact hole is the first depth-width ratio, the depth of second contact hole
Degree and the ratio of smallest lateral dimension are the second depth-width ratio；Second depth-width ratio is more than or equal to first depth-width ratio, described
First contact hole, second contact hole and the third contact hole all use tungsten plug process filling, utilize the tungsten plug technique
Device to hole covering power guarantee simultaneously realization to different aspect ratios first contact hole and second contact hole can
By filling；
It deposits to form front metal layer Step 6: carrying out front metal, carries out the 6th photoetching process and define grid and source electrode
Forming region, later the front metal layer is performed etching to form the grid and the source electrode, the charge flow region
In each source region and the corresponding p-type trap source electrode, institute be connected to by identical first contact hole in top
The p-type ring stated in transition region is connected to the source electrode also by second contact hole at top, and the polysilicon gate is logical
It crosses the third contact hole and is connected to grid.
11. the manufacturing method of superjunction devices as claimed in claim 10, it is characterised in that: the first contact described in step 5
It further include in first contact hole before metal is filled after the opening in hole, second contact hole and the third contact hole is formed
The step of P+ ion implanting forms the contact zone P+ is carried out with the bottom of second contact hole.
12. the manufacturing method of superjunction devices as claimed in claim 11, it is characterised in that: the interlayer film is by oxidation film group
At etching is formed advanced when the opening of first contact hole, second contact hole and the third contact hole in step 5
The etching of row oxidation film completely removes in the interlayer film of the first contact bore region and exposes the source region of bottom
When stop oxidation film etching, carry out the etching of epitaxial film materials；First connects described in when carrying out the etching of the epitaxial film materials
The epitaxial layer of the bottom of contact hole generates over etching, while the oxidation film of the second contact bore region can partial etching；Described
The oxidation film of second contact bore region carries out the P+ ion implanting of the contact zone P+ before not being completely removed, make described second
The peak value for contacting the P+ ion implanting of the contact zone P+ of bore region is located in oxidation film, so that first contact hole, institute
State the second contact hole and the third contact hole opening and metal filling completely after, second contact hole bottom it is described
The peak value of the doping concentration of the contact zone P+ is less than the peak value of the doping concentration of the contact zone P+ of first contact hole bottom.
13. the manufacturing method of superjunction devices as claimed in claim 12, it is characterised in that: state the P+ of the contact zone P+ by adjusting
Thickness when ion implanting positioned at the oxidation film of the second contact hole sections bottom adjusts the institute of second contact hole bottom
The doping concentration of the contact zone P+ is stated, and makes the peak value institute of the doping concentration of the contact zone P+ of second contact hole bottom
State the 1/2~1/10 of the peak value of the doping concentration of the contact zone P+ of the first contact hole bottom.
14. the manufacturing method of superjunction devices as claimed in claim 10, it is characterised in that: use individual photoetching in step 2
The p-type ring is formed with ion implantation technology, and the formation process of the p-type ring is located at before the formation process of the p-type trap.
15. the manufacturing method of superjunction devices as claimed in claim 11, it is characterised in that: forming the polycrystalline in step 4
Protection ring oxidation film surface while Si-gate in the termination environment forms polysilicon bus and in the transition region
The protection ring oxidation film surface forms polysilicon line, and each polysilicon gate is connected to described by the polysilicon line
Polysilicon bus, the width of the polysilicon line are less than or equal to the width of the polysilicon gate；
Third contact hole described in step 5 is located at the top of the polysilicon bus, and the bottom of the third contact hole passes through layer
Between film and enter in the polysilicon bus and the bottom of the third contact hole rests in the polysilicon bus or will
The polysilicon bus passes through；
Third contact bore region is protected using photoetching process when carrying out the P+ ion implanting of the contact zone P+ in step 5
Shield.
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