CN109148401A - A kind of semiconductor devices and preparation method thereof, electronic device - Google Patents
A kind of semiconductor devices and preparation method thereof, electronic device Download PDFInfo
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- CN109148401A CN109148401A CN201710464429.XA CN201710464429A CN109148401A CN 109148401 A CN109148401 A CN 109148401A CN 201710464429 A CN201710464429 A CN 201710464429A CN 109148401 A CN109148401 A CN 109148401A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
- H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
- H01L2224/11452—Chemical vapour deposition [CVD], e.g. laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13023—Disposition the whole bump connector protruding from the surface
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Abstract
The present invention provides a kind of semiconductor devices and preparation method thereof, electronic device, the semiconductor devices includes the first metal dish set gradually, top through-hole, second metal dish, pad, first passivation layer and the second passivation layer, second passivation layer formation is on first passivation layer, and second opening with the exposure pad, wherein, the top through-hole includes the first top through-hole and the second top through-hole, first top through-hole is located at the lower section of the second opening, second top through-hole is located at the corresponding position of second open outer side, and the size of first top through-hole is greater than the size of second top through-hole.The adhesion strength between time metal layer at top and top through-hole can be improved in the semiconductor devices, reduces the risk that pad peels off.Advantage as the production method and electronic device concrete kind of the semiconductor devices.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof, electronics
Device.
Background technique
The various transistor devices such as NMOS, PMOS, CMOS are not only needed to form in integrated circuit fabrication, but also
Interconnection structure is needed to form to realize the connection between these devices and between device and external signal.When having made mutual connection
After structure, that is, it is formed on the passivation of the pad and covering device interconnection structure and exposure pad for connecting with package substrate
Layer.
A kind of currently used pad (pad) design is double solid disk (TM, TM-1) designs and copper wire bonding.It is exemplary
Ground, as shown in FIG. 1A and 1B, this pad structure is in the lower section in the quasi- region for forming pad 105, in secondary metal layer at top
(TM-1) and in metal layer at top (TM) the first metal dish 101 and the second metal dish 103,101 He of the first metal dish are respectively formed
Second metal dish 103 is solid disk-like structure, and the second metal dish 103 as shown in fig. 1b can be rectangle, circle, six
The area of the area ratio pad 105 of the various suitable shapes such as side shape, the first metal dish 101 and the second metal dish 103 is big.First
Metal dish 101 and the second metal dish 103 are connected by the top through-hole 102 filled with metal (such as copper), in metal layer at top
On be formed with the first passivation layer 104 of the second metal dish 103 of covering, be formed with that exposure is quasi- to form pad in the first passivation layer 104
The opening in region, pad 105 is formed in said opening and 104 surface of the first passivation layer is on the part of the opening,
It is formed with the second passivation layer 106 on first passivation layer 104, the exposure pad 105 is formed in the second passivation layer 106
Opening 107.Metal layer and substrate and device below being formed with below the first metal dish 101, are represented simply as herein
Metal layer 100.
However, adhesion strength between this first metal dish of pad structure 101 and top through-hole 102 (namely secondary top metal
Adhesion strength between layer (TM-1) and top through-hole) it is more fragile, due to stress in subsequent package lead bonding process
It is subject to the risk of pad peeling, is i.e. is split between the first metal dish 101 of region shown in dotted line time and top through-hole 102 in Figure 1A
It opens, so that the second metal dish 103 and pad 105 of top peel off or deformation.
It is, therefore, desirable to provide a kind of new semiconductor devices and preparation method thereof, electronic device, at least to be partially solved
The above problem.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, the present invention proposes a kind of semiconductor devices, can be improved time metal layer at top and
Adhesion strength between the through-hole of top reduces the risk that pad peels off.
In order to overcome the problems, such as that presently, there are one aspect of the present invention provides a kind of semiconductor devices comprising: the first metal
Disk, top through-hole, the second metal dish, pad, the first passivation layer and the second passivation layer, in which:
First metal dish is formed in the region being located at below pad in time metal layer at top；
The top through-hole is formed between first metal dish and the second metal dish, and is filled with conductive material,
To be electrically connected first metal dish and the second metal dish；
Second metal dish is located on the top through-hole, and is formed in metal layer at top and is located at below pad
Region；
First passivation layer covers the metal layer at top, and has the first opening of the exposure pad；It is described
Second passivation layer formation has the second opening of the exposure pad on first passivation layer,
Wherein, the top through-hole includes the first top through-hole and the second top through-hole, and first top through-hole is located at
The lower section of second opening, second top through-hole are located at the corresponding position of second open outer side, and described
The size of first top through-hole is greater than the size of second top through-hole.
Further, the size of first top through-hole is bigger by 0~40% than the size of second top through-hole.
Further, the pad includes the main part in first opening and is located at the first passivation layer table
The extension in face.
Further, the area of first metal dish and the second metal dish is greater than the area of the pad.
Further, it is isolated between first metal dish and second metal dish by dielectric layer, the top is logical
Hole passes through the dielectric layer.
Semiconductor device according to the invention, by the ruler for increasing top through-hole corresponding to the opening lower section of exposure pad
It is very little to increase the adhesion strength between top through-hole and secondary metal layer at top, to increase the stress ability to bear of pad structure,
Reduce the risk that pad peels off in bonding process.
Further, semiconductor device according to the invention only changes top corresponding to the opening lower section of exposure pad
The size of through-hole, and it is located at the gauge that the top through-hole except the opening of exposure pad still uses technique and design determination
It is very little, process risk can be reduced in this way, improve yield of devices.Furthermore, it is necessary to which the top through-hole of increased in size can pass through logic
Operation determines, simple and convenient.
Another aspect of the present invention provides a kind of production method of semiconductor devices, comprising:
Semiconductor substrate is provided, forms the first metal dish on the semiconductor substrate, first metal dish is formed in
It is located at the region below the quasi- pad formed in secondary metal layer at top；
Top through-hole is formed, the top through-hole is located on first metal dish, and is filled with conductive material；
The second metal dish is formed, second metal dish is located on the top through-hole, and is formed in metal layer at top
In be located at region below the quasi- pad formed, and connect by the top through-hole with first metal dish；
The first passivation layer for covering the metal layer at top is formed, first passivation layer has exposure second metal
First opening of a part of disk；
Pad is formed on second metal dish in first opening；
Form the second passivation layer on first passivation layer, second passivation layer has the of the exposure pad
Two openings,
Wherein, the top through-hole includes the first top through-hole and the second top through-hole, and first top through-hole is located at
The lower section of second opening, second top through-hole are located at the corresponding position of second open outer side, and described
The size of first top through-hole is greater than the size of second top through-hole.
Further, the size of first top through-hole is bigger by 0~40% than the size of second top through-hole.
Further, the pad includes the main part in first opening and is located at the first passivation layer table
The extension in face.
Further, it is isolated between first metal dish and second metal dish by dielectric layer, the top is logical
Hole passes through the dielectric layer.
The production method of semiconductor device according to the invention, by increasing top corresponding to the opening lower section of exposure pad
The size of portion's through-hole come increase top through-hole and secondary metal layer at top between adhesion strength, to increase the stress of pad structure
Ability to bear reduces the risk that pad peels off in bonding process.
Further, the production method of semiconductor device according to the invention only changes institute below the opening of exposure pad
The size of corresponding top through-hole, and be located at the top through-hole except the opening of exposure pad and technique and design is still used to determine
Standard size, can reduce process risk in this way, improve yield of devices.Furthermore, it is necessary to which the top through-hole of increased in size can be with
It is determined by logical operation, it is simple and convenient.
Further aspect of the present invention provides a kind of electronic device comprising semiconductor devices as described above and with described half
The electronic building brick that conductor device is connected.
Electronic device proposed by the present invention due to improving with above-mentioned semiconductor device performance and yield, thus has class
As advantage.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Figure 1A shows a kind of schematic cross sectional views of current pad structure；
Figure 1B shows the perspective view of top through-hole and opening on the second metal dish in pad structure shown in Figure 1A；
Fig. 2A shows the schematic cross sectional views of pad structure according to an embodiment of the present invention；
Fig. 2 B shows the first top through-hole and the second top through-hole and the second opening in pad structure shown in Fig. 2A and exists
Perspective view on second metal dish；
Fig. 3 shows the step flow chart of the production method of semiconductor devices according to an embodiment of the present invention；
Fig. 4 shows the structural schematic diagram of electronic device according to an embodiment of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated phase from beginning to end
Identical element is indicated with appended drawing reference.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " is directly connected to
To " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.Art can be used although should be understood that
Language first, second, third, etc. describes various component, assembly units, area, floor and/or part, these component, assembly units, area, floor and/or portion
Dividing should not be limited by these terms.These terms are used merely to distinguish a component, assembly unit, area, floor or part and another
Component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, component, area,
Floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and being used describe an elements or features shown in figure with it is other
The relationship of elements or features.It should be understood that other than orientation shown in figure, spatial relation term intention further include using with
The different orientation of device in operation.For example, then, being described as " below other elements " if the device in attached drawing is overturn
Or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to illustrate this hair
The technical solution of bright proposition.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention
There can also be other embodiments.
Embodiment one
Ginseng Fig. 2A and Fig. 2 B is described in detail semiconductor devices according to an embodiment of the present invention below.
It is formed on semiconductor substrate (not shown) according to the semiconductor devices of the present embodiment, in the semiconductor substrate
On be formed with various devices and part interconnection structure etc., outlined herein with metal layer 200.Below with reference to Fig. 2A and Fig. 2 B
The pad structure of semiconductor devices according to the present embodiment is described.
As shown in Figure 2 A and 2 B, in the present embodiment, pad structure includes the first metal dish 201, the first top through-hole
202A and the second top through-hole 202B, the second metal dish 203, the first passivation layer 204, pad 205 and the second passivation layer 206.
Wherein, the first metal dish 201 is formed in time metal layer at top (closely top below TM-1, i.e. metal layer at top TM
The metal layer of metal layer TM) in be located at the region of the lower section of pad 205, and preferably, area (the i.e. surface of the first metal dish 201
Projected area long-pending or in horizontal plane) be greater than the area of pad 205, i.e. the first metal dish 201 is greater than pad 205.Top through-hole
It is formed between the first metal dish 201 and the second metal dish 203, and is filled with conductive material, such as copper, to connect the first gold medal
Belong to disk 201 and the second metal dish 203.
Second metal dish 203 is located on the first top through-hole 202A and the second top through-hole 202B, and is formed in
It is located at the region below pad in metal layer at top (i.e. the metal layer TM of interconnection structure top layer), and preferably, the second metal
The area (i.e. surface area or the projected area in horizontal plane) of disk 203 is greater than the area of pad 205, i.e. the second metal dish 203 is big
In pad 205.
First passivation layer 204 covers metal layer at top, and has the first opening of exposure pad 205.Namely pad 205
It is formed in by the second metal dish 203 of the first opening exposure.
Pad 205 illustratively includes the main part in first opening and is located at first passivation layer surface
Extension, the main part and the extension are connected to each other.Pad 205 is illustratively made of metallic aluminium.
Second passivation layer 206 is formed on the first passivation layer 204, and has the second opening of exposure pad 205
207。
In the present embodiment, be two kinds of specifications by top via design in order to reduce the risk of pad peeling, such as Fig. 2A and
Shown in Fig. 2 B, top through-hole includes the first top through-hole 202A and the second top through-hole 202B, wherein the first top through-hole 202A
Positioned at the lower section of the second opening 207, the second top through-hole 202B is located at the outside of second opening, i.e. the first top through-hole
202A is covered by second opening 207 in the projection of horizontal plane in the projection of horizontal plane, and the second top through-hole 202B is in water
The projection of plane is located at the outside of projection of second opening 207 in horizontal plane.The wherein size of the first top through-hole 202A
Size CD2, second top through-hole 202B of the CD1 (characteristic size) greater than the second top through-hole 202B use the institute of technique and design
The standard size used, size CD 2 big 0 of the size CD1 than the second top through-hole 202B of the first top through-hole 202A~
40%, illustratively, such as the size CD1 of the first top through-hole 202A bigger by 11% than the size CD2 of the second top through-hole 202B,
Make the contact area increase about 23.4% between the first top through-hole 202A and the first metal dish 201 in this way, to increase
Adhesion strength between first top through-hole 202A and the first metal dish 201, namely increase the first top through-hole 202A and time top
Adhesion strength between portion's metal layer reduces pad in bonding process to increase the stress ability to bear of pad structure
The risk of peeling.
It is understood that be only the cross-sectional view and top view of pad forming region shown in Fig. 2A and Fig. 2 B, above-mentioned time
The entire secondary top-level metallic that metal layer at top refers to as device interconnected structure, metal layer at top are the entire of device interconnected structure
Top layer metallic layer, other regions in metal layer at top and time metal layer at top can also be formed with conventional interconnection line etc.,
The shape and structure of pad corresponding region are only shown in Fig. 2A and Fig. 2 B.In addition, between metal layer at top and secondary metal layer at top,
Pass through dielectric layer and between first metal dish, the second metal dish and other interconnection lines, between the through-hole of top to be isolated, that is, described
It is isolated between first metal dish and second metal dish by dielectric layer, the top through-hole is in the dielectric layer, figure
The dielectric layer is not shown for brevity.
According to the semiconductor devices of the present embodiment, by increasing top through-hole corresponding to the opening lower section of exposure pad
Size come increase top through-hole and secondary metal layer at top between adhesion strength, thus increase pad structure stress bear energy
Power reduces the risk that pad peels off in bonding process.
Further, according to the semiconductor devices of the present embodiment, only change top corresponding to the opening lower section of exposure pad
The size of portion's through-hole, and it is located at the gauge that the top through-hole except the opening of exposure pad still uses technique and setting determination
It is very little, process risk can be reduced in this way, improve yield of devices.Furthermore, it is necessary to which the top through-hole of increased in size can pass through logic
Operation (determining dashed region shown in Fig. 2A by logical operation) determines, simple and convenient.
Embodiment two
Another embodiment of the present invention provides a kind of production methods of semiconductor devices, as shown in Figure 3, comprising:
Step 301, semiconductor substrate is provided, forms the first metal dish, first metal on the semiconductor substrate
Disk is formed in the region being located at below the quasi- pad formed in time metal layer at top.
Wherein, semiconductor substrate can be following at least one of the material being previously mentioned: Si, Ge, SiGe, SiC,
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors further include the multilayered structure etc. that these semiconductors are constituted
Or it is silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), insulation is laminated on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.It could be formed with device, such as NMOS in semiconductor substrate
And/or PMOS etc..Equally, can also be formed with conductive member in semiconductor substrate, conductive member can be transistor grid,
Source electrode or drain electrode are also possible to the metal interconnection structure, etc. being electrically connected with transistor.In addition, may be used also in the semiconductor substrate
To be formed with isolation structure, the isolation structure is shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation junction
Structure.As an example, in the present embodiment, the constituent material of semiconductor substrate selects monocrystalline silicon.
First metal dish is formed in the region being located at below the quasi- pad formed in time metal layer at top.Secondary top-gold
Belonging to layer is the metal layer below metal layer at top close to metal layer at top.First metal dish can pass through interconnection commonly used in the art
Structure formation method production, such as big cordovan scholar method or double big cordovan scholar methods are formed.First metal dish is illustratively adopted
Made with copper.
Step 302, top through-hole is formed, the top through-hole is located on first metal dish, and is filled with and leads
Electric material.The top through-hole includes the first top through-hole and the second top through-hole, and the size of first top through-hole is greater than
The size of second top through-hole.The top through-hole can be made by interconnection structure forming method commonly used in the art,
Such as big cordovan scholar method or double big cordovan scholar methods are formed.Metallic copper is illustratively filled in the top through-hole.
Step 303, the second metal dish is formed, second metal dish is located on the top through-hole, and is formed in top
It is located at the region below the quasi- pad formed in portion's metal layer, and is connect by the top through-hole with first metal dish.
Metal layer at top is the metal layer of top layer in the device of the peninsula.Second metal dish can pass through interconnection structure shape commonly used in the art
It is made at method, such as big cordovan scholar method or double big cordovan scholar methods are formed.Second metal dish illustratively uses copper
Make.
Step 304, the first passivation layer for covering the metal layer at top is formed, first passivation layer has described in exposure
First opening of a part of the second metal dish.
First passivation layer can be using various suitable dielectric materials, such as oxide, nitride or nitrogen oxides etc..Show
Example property, in the present embodiment, the first passivation layer uses silica.First passivation layer can by PVD (physical vapour deposition (PVD)),
CVD (chemical vapor deposition), ALD (atomic layer deposition) etc., and after having deposited the first passivation layer, pass through chemical wet etching etc.
Patterning process forms the first opening of exposed lower metal layer, so that the pad being subsequently formed is electrically connected with lower metal layer.
Step 305, pad is formed on second metal dish in first opening.
Pad can be made by method commonly used in the art, illustratively, formed pad the step of include:
Form the metal layer that filling described first was open and covered first passivation layer.Metal layer can be normal with aluminium or copper etc.
With metal, and pass through the methods of sputtering, PVD, CVD formation.Illustratively, in the present embodiment, metal layer uses aluminium.
The graphical metal layer is to form pad, wherein the pad includes the pad in first opening
Main part and the extension being connect on first passivation layer and with the pad main part.
Metal layer is graphically completed by photoetching commonly used in the art, etching technics, and details are not described herein.By welding
Disc main body portion periphery setting extension can increase the binding ability of pad.
Step 306, the second passivation layer is formed on first passivation layer, second passivation layer has described in exposure
Second opening of pad.
Second passivation layer can be using various suitable dielectric materials, such as oxide, nitride or nitrogen oxides etc..Show
Example property, in the present embodiment, the second passivation layer uses silica.Second passivation layer can by PVD (physical vapour deposition (PVD)),
CVD (chemical vapor deposition), ALD (atomic layer deposition) etc., and after having deposited the second passivation layer, pass through chemical wet etching etc.
Patterning process forms the second opening of exposed pad ontology, so as to subsequent encapsulation.
Illustratively, the main part of the second opening exposure pad, and the extension of the pad, or at least
The extension of the part pad is covered by second passivation layer.
It further, in the present embodiment, is two kinds of rule by top via design in order to reduce the risk that pad peels off
Lattice, as shown in Figure 2 A and 2 B, top through-hole include the first top through-hole 202A and the second top through-hole 202B, wherein the first top
Portion through-hole 202A is positioned at the lower section of the second opening 207, the outside that the second top through-hole 202B is open positioned at described second, i.e., and first
Top through-hole 202A is covered by second opening 207 in the projection of horizontal plane in the projection of horizontal plane, and the second top through-hole
202B is located at the outside of projection of second opening 207 in horizontal plane in the projection of horizontal plane.Wherein the first top through-hole
The size (CD characteristic size) of 202A is greater than the size of the second top through-hole 202B, and the second top through-hole 202B is using technique and sets
The size of the standard size of meter, the first top through-hole 202A is bigger by 0~40% than the size of the second top through-hole 202B, exemplary
Ground, such as the size of the first top through-hole 202A are bigger by 11% than the size of the second top through-hole 202B, so that the first top
Contact area increase about 23.4% between through-hole 202A and the first metal dish 201, to increase the first top through-hole 202A
With the adhesion strength between the first metal dish 201, namely increase viscous between the first top through-hole 202A and secondary metal layer at top
Attached power reduces the risk that pad peels off in bonding process to increase the stress ability to bear of pad structure.
According to the production method of the semiconductor devices of the present embodiment, by increasing corresponding to the opening lower section of exposure pad
The size of top through-hole come increase top through-hole and secondary metal layer at top between adhesion strength, to increase answering for pad structure
Power ability to bear reduces the risk that pad peels off in bonding process.
Further, according to the production method of the semiconductor devices of the present embodiment, only change the opening lower section of exposure pad
The size of corresponding top through-hole, and be located at the top through-hole except the opening of exposure pad and still use technique and setting true
Fixed standard size can reduce process risk in this way, improve yield of devices.Furthermore, it is necessary to which the top through-hole of increased in size can
It is simple and convenient to be determined by logical operation (determining dashed region shown in Fig. 2A by logical operation).
Embodiment three
Yet another embodiment of the present invention provides a kind of electronic device, including semiconductor devices and with the semiconductor device
The connected electronic building brick of part.Wherein, which includes the first metal dish, top through-hole, the second metal dish, pad, the
One passivation layer and the second passivation layer, in which: first metal dish is formed in the area being located at below pad in time metal layer at top
Domain；The top through-hole is formed between first metal dish and the second metal dish, and is filled with conductive material, to be electrically connected
Connect first metal dish and the second metal dish；Second metal dish is located on the top through-hole, and is formed in top
It is located at the region below pad in metal layer；First passivation layer covers the metal layer at top, and has described in exposure
First opening of pad；Second passivation layer formation has the exposure pad on first passivation layer
Second opening, wherein the top through-hole includes the first top through-hole and the second top through-hole, and first top through-hole is located at
The lower section of second opening, second top through-hole are located at the corresponding position of second open outer side, and described
The size of first top through-hole is greater than the size of second top through-hole.
Wherein, semiconductor substrate can be following at least one of the material being previously mentioned: Si, Ge, SiGe, SiC,
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors further include the multilayered structure etc. that these semiconductors are constituted
Or it is silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), insulation is laminated on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.It could be formed with device, such as NMOS in semiconductor substrate
And/or PMOS etc..Equally, can also be formed with conductive member in semiconductor substrate, conductive member can be transistor grid,
Source electrode or drain electrode are also possible to the metal interconnection structure, etc. being electrically connected with transistor.In addition, may be used also in the semiconductor substrate
To be formed with isolation structure, the isolation structure is shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation junction
Structure.As an example, in the present embodiment, the constituent material of semiconductor substrate selects monocrystalline silicon.
Wherein, the electronic building brick can be any electronic building bricks such as discrete device, integrated circuit.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment can also be
Any intermediate products including the semiconductor devices.
Wherein, Fig. 4 shows the example of mobile phone.The outside of mobile phone 400 is provided with including the display portion in shell 401
402, operation button 403, external connection port 404, loudspeaker 405, microphone 406 etc..
The electronic device of the embodiment of the present invention, since the semiconductor devices for being included can increase top through-hole and time top
Adhesion strength between metal layer, the risk that reduction pad peels off, therefore the electronic device equally have the advantages that similar.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of semiconductor devices characterized by comprising the first metal dish, top through-hole, the second metal dish, pad, first
Passivation layer and the second passivation layer, in which:
First metal dish is formed in the region being located at below pad in time metal layer at top；
The top through-hole is formed between first metal dish and the second metal dish, and is filled with conductive material, with electricity
Connect first metal dish and the second metal dish；
Second metal dish is located on the top through-hole, and is formed in the area being located at below pad in metal layer at top
Domain；First passivation layer covers the metal layer at top, and has the first opening of the exposure pad；
Second passivation layer formation has the second opening of the exposure pad on first passivation layer,
Wherein, the top through-hole includes the first top through-hole and the second top through-hole, and first top through-hole is located at described
The lower section of second opening, second top through-hole are located at the corresponding position of second open outer side, and described first
The size of top through-hole is greater than the size of second top through-hole.
2. semiconductor devices according to claim 1, which is characterized in that the size of first top through-hole is than described
The size of two top through-holes is big by 0~40%.
3. semiconductor devices according to claim 1, which is characterized in that the pad includes being located in first opening
Main part and extension positioned at first passivation layer surface.
4. semiconductor devices according to any one of claims 1-3, which is characterized in that first metal dish and
The area of second metal dish is greater than the area of the pad.
5. semiconductor devices according to any one of claims 1-3, which is characterized in that first metal dish with
It is isolated between second metal dish by dielectric layer, the top through-hole passes through the dielectric layer.
6. a kind of production method of semiconductor devices characterized by comprising
Semiconductor substrate is provided, forms the first metal dish on the semiconductor substrate, first metal dish is formed in time top
It is located at the region below the quasi- pad formed in portion's metal layer；
Top through-hole is formed, the top through-hole is located on first metal dish, and is filled with conductive material；
The second metal dish is formed, second metal dish is located on the top through-hole, and is formed in position in metal layer at top
Region below the quasi- pad formed, and be electrically connected by the top through-hole with first metal dish；
The first passivation layer for covering the metal layer at top is formed, first passivation layer has exposure second metal dish
First opening of a part；
Pad is formed on second metal dish in first opening；
The second passivation layer is formed on first passivation layer, second passivation layer has the second of the exposure pad to open
Mouthful,
Wherein, the top through-hole includes the first top through-hole and the second top through-hole, and first top through-hole is located at described
The lower section of second opening, second top through-hole are located at the corresponding position of second open outer side, and described first
The size of top through-hole is greater than the size of second top through-hole.
7. production method according to claim 6, which is characterized in that the size of first top through-hole is than described second
The size of top through-hole is big by 0~40%.
8. production method according to claim 6, which is characterized in that the pad includes being located in first opening
Main part and extension positioned at first passivation layer surface.
9. production method according to claim 6, which is characterized in that first metal dish and second metal dish it
Between by dielectric layer be isolated, the top through-hole pass through the dielectric layer.
10. a kind of electronic device, which is characterized in that including the semiconductor devices as described in any one in claim 1-5
And the electronic building brick being connected with the semiconductor devices.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050269697A1 (en) * | 2004-06-04 | 2005-12-08 | Seiko Epson Corporation | Semiconductor device, circuit board, and electronic instrument |
| CN101866898A (en) * | 2009-04-15 | 2010-10-20 | 国际商业机器公司 | The metal wiring structure that is used for C4 ball uniform current density |
-
2017
- 2017-06-19 CN CN201710464429.XA patent/CN109148401A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050269697A1 (en) * | 2004-06-04 | 2005-12-08 | Seiko Epson Corporation | Semiconductor device, circuit board, and electronic instrument |
| CN101866898A (en) * | 2009-04-15 | 2010-10-20 | 国际商业机器公司 | The metal wiring structure that is used for C4 ball uniform current density |
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Application publication date: 20190104 |