CN109148305A - A kind of power device and preparation method thereof - Google Patents
A kind of power device and preparation method thereof Download PDFInfo
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- CN109148305A CN109148305A CN201811065926.3A CN201811065926A CN109148305A CN 109148305 A CN109148305 A CN 109148305A CN 201811065926 A CN201811065926 A CN 201811065926A CN 109148305 A CN109148305 A CN 109148305A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 83
- 238000002347 injection Methods 0.000 claims abstract description 76
- 239000007924 injection Substances 0.000 claims abstract description 76
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 60
- 229910052710 silicon Inorganic materials 0.000 claims description 60
- 229910052751 metal Inorganic materials 0.000 claims description 59
- 239000002184 metal Substances 0.000 claims description 59
- 239000010703 silicon Substances 0.000 claims description 56
- 230000003647 oxidation Effects 0.000 claims description 39
- 238000007254 oxidation reaction Methods 0.000 claims description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 28
- 229920005591 polysilicon Polymers 0.000 claims description 27
- 238000005530 etching Methods 0.000 claims description 21
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000000407 epitaxy Methods 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 239000010410 layer Substances 0.000 description 401
- 150000002500 ions Chemical class 0.000 description 55
- 238000000034 method Methods 0.000 description 48
- 239000004065 semiconductor Substances 0.000 description 31
- 239000000463 material Substances 0.000 description 18
- 238000009792 diffusion process Methods 0.000 description 16
- 238000001312 dry etching Methods 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 230000008569 process Effects 0.000 description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 7
- 229910052796 boron Inorganic materials 0.000 description 7
- 229910052785 arsenic Inorganic materials 0.000 description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 239000004411 aluminium Substances 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
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- 239000013078 crystal Substances 0.000 description 5
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- 230000000694 effects Effects 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 238000000927 vapour-phase epitaxy Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
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- 238000010586 diagram Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
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- 238000004544 sputter deposition Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
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- 230000002441 reversible effect Effects 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention provides a kind of power device and preparation method thereof, it include: substrate, first epitaxial layer, first groove, first injection region, second epitaxial layer, second groove, third groove, 4th groove, second injection region, third epitaxial layer, second epitaxial layer is L-type, the medial surface of second epitaxial layer covers side and the portion bottom surface of the third epitaxial layer, the portion bottom surface of the third epitaxial layer is connect with first epitaxial layer, the ion concentration of the third epitaxial layer is greater than the ion concentration of first epitaxial layer, fourth epitaxial layer, source electrode, grid, drain electrode, the structure setting had both increased the breakdown voltage of device, the conducting resistance of device is reduced simultaneously, improve the performance of VDMOS device.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of power device and preparation method thereof.
Background technique
VDMOS (is the abbreviation of VDMOSFET, Vertical Double Diffused Metal Oxide
Semiconductor Field Effect Transistor, vertical DMOS field effect transistor)
Drain-source the two poles of the earth respectively in the two sides of device, so that electric current is vertically circulated in device inside, increase current density, improve specified
The conducting resistance of electric current, unit area is also smaller, is a kind of power device that purposes is very extensive.For power device,
There are two particularly important parameters, and one is conducting resistance, the other is breakdown voltage, wishes that conducting resistance is most for application
It is possible small, and the higher the better for breakdown voltage.Power device needs to bear high voltage using very thick low-doped extension
Layer.By increasing epitaxy layer thickness or reducing the doping concentration of epitaxial layer, while breakdown voltage can be improved, but do so
Conducting resistance is improved, is unfavorable for reducing power loss when break-over of device.It can be seen that the prior art is hit in promotion VDMOS
Voltage is worn, is reduced between conducting resistance there are insurmountable contradiction, the performance for affecting VDMOS device continues to lift up.
Summary of the invention
The embodiment of the present invention based on the above issues, proposes a kind of power device and preparation method thereof, improves VDMOS device
The performance of part.
On the one hand, the present invention provides a kind of preparation methods of power device, this method comprises:
The substrate of first conduction type is provided；
Surface forms the first epitaxial layer of the first conduction type over the substrate；
First groove, the first groove at least two, and described first are formed in first epitaxial layer upper surface
The quantity of groove is even number；
The first injection region of the second conduction type is formed in the bottom surface of the first groove by injection mode；
The second epitaxial layer of the second conduction type is filled in the first groove；
The part for etching first epitaxial layer and second epitaxial layer forms second groove, and the second groove
Depth is less than the first groove；
Form third groove in first epitaxial layer upper surface, the third groove be located at two second grooves it
Between, the depth of the third groove is less than the depth of the first groove；
The 4th groove is formed in the third beneath trenches, the 4th groove connect with the third groove, and described the
The width of four grooves is greater than the width of the third groove；
The second injection region of the second conduction type is formed in the bottom surface of the 4th groove by injection mode；
The third epitaxial layer of the first conduction type is filled in the second groove, second epitaxial layer is L-type, described
The medial surface of second epitaxial layer covers side and the portion bottom surface of the third epitaxial layer, the portion bottom surface of the third epitaxial layer
It is connect with first epitaxial layer, the ion concentration of the third epitaxial layer is greater than the ion concentration of first epitaxial layer；
The fourth epitaxial layer of the first conduction type is filled in the third groove and the 4th groove, outside the described 4th
The ion concentration for prolonging layer is greater than the ion concentration of first epitaxial layer；
By injection mode in the body area of the second conduction type of third epitaxial layer upper surface formation and in the body area
Upper surface forms the source region of the first conduction type, and the third epitaxial layer is wrapped up in second epitaxial layer and the body area jointly
Remainder；
Gate oxidation silicon layer, gate oxidation silicon layer lower surface and described the are formed in first epitaxial layer upper surface
The connection of four epitaxial layers, one end of the gate oxidation silicon layer is connect with the source region；
Polysilicon layer is formed in gate oxidation silicon layer upper surface；
Dielectric layer is formed above first epitaxial layer and the polysilicon layer；
The first metal layer is formed above the dielectric layer, the first metal layer is through the dielectric layer and the source region
Connection forms source electrode；
Second metal layer is formed above the dielectric layer, the second metal layer is through the dielectric layer and the polycrystalline
Silicon layer connects to form grid；
Third metal layer is formed in the substrate lower surface, the third metal layer connect to form drain electrode with the substrate.
Further, the ion concentration of second epitaxial layer is greater than the ion concentration of first injection region.
Further, the depth of the first groove is greater than the sum of the third groove and the 4th trench depth.
Further, the part for etching first epitaxial layer and second epitaxial layer forms second groove, specific to wrap
Include: the part of two neighboring second epitaxial layer of etching and first epitaxial layer of intermediate portion are to form described second
Groove.
Further, the depth of the 4th groove is less than the depth of the third groove.
Further, the ion concentration of second injection region and the ion concentration of first injection region are roughly equal.
Further, the ion concentration of the ion concentration and the fourth epitaxial layer of the third epitaxial layer is roughly equal.
On the other hand, the present invention provides a kind of power device, which includes:
The substrate of first conduction type；
It is formed in the first epitaxial layer of the first conduction type of the upper surface of substrate；
It is formed in described in source region and the package of the first conduction type of first epitaxial layer upper surface by injection mode
The body area of second conduction type of source region；
It is formed in the third epitaxial layer of the first conduction type of body area two sides；
Wrap up the second epitaxial layer of the second conduction type of the third epitaxial layer jointly with the body area；
The first injection region of the second conduction type of second epitaxial layer lower surface is formed in by injection mode；
It is formed in the third groove of first epitaxial layer upper surface, the third groove is located at two second grooves
Between, the depth of the third groove is less than the depth of the first groove；
It is formed in the 4th groove of the third beneath trenches, the 4th groove is connect with the third groove, described
The width of 4th groove is greater than the width of the third groove；
The second injection region of the second conduction type of the bottom surface of the 4th groove is formed in by injection mode；
It is filled in the fourth epitaxial layer of the third groove and the first conduction type in the 4th groove, the described 4th
The ion concentration of epitaxial layer is greater than the ion concentration of first epitaxial layer；
Be formed in the gate oxidation silicon layer of first epitaxial layer upper surface, gate oxidation silicon layer lower surface with it is described
Fourth epitaxial layer connection, one end of the gate oxidation silicon layer is connect with the source region；
It is formed in the polysilicon layer of gate oxidation silicon layer upper surface；
The dielectric layer being formed in above first epitaxial layer and the polysilicon layer；
The first metal layer being formed in above the dielectric layer, the first metal layer is through the dielectric layer and the source
Area connects to form source electrode；
The second metal layer being formed in above the dielectric layer, the second metal layer is through the dielectric layer and described more
Crystal silicon layer connects to form grid；
It is formed in the third metal layer of the substrate lower surface, the third metal layer connect to form leakage with the substrate
Pole.
Further, the ion concentration of second epitaxial layer is greater than the ion concentration of first injection region.
Further, the thickness of second epitaxial layer is greater than the fourth epitaxial layer thickness.
The present invention is through the above technical solutions, propose a kind of power device of inverted T shaped extension supplementary structure of band, in body area
Surrounding increases the third epitaxial layer of the first conduction type and the second epitaxial layer of the second conduction type, and in the second epitaxial layer
The first injection region of the second conduction type is arranged in lower section, the case where not increasing epitaxy layer thickness and not changing epitaxial layer concentration
Under, the area of depletion region is increased, improves device electric breakdown strength, and since epitaxial thickness and concentration do not change, device
Conducting resistance not will increase；Fourth epitaxial layer is increased in epitaxial layer simultaneously, which is less than extension
Layer, and the second injection region is set below fourth epitaxial layer, reduce the conducting resistance of device, therefore the function of the structure setting
Rate device had both increased the breakdown voltage of device, while reducing the conducting resistance of device, improved the performance of VDMOS device.
Detailed description of the invention
For in order to illustrate the technical solution of the embodiments of the present invention more clearly, below to required use in embodiment description
Attached drawing be briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, for this field
For those of ordinary skill, without creative efforts, it is also possible to obtain other drawings based on these drawings.
In the accompanying drawings:
Fig. 1 is the flow diagram of the preparation method for the power device that one embodiment of the present of invention provides；
Fig. 2 to Fig. 8 is the structural schematic diagram of the preparation method step for the power device that one embodiment of the present of invention provides；
Description of symbols:
1- substrate；The first epitaxial layer of 2-；The second epitaxial layer of 3-；31- the first sub-district of the second epitaxial layer；The second epitaxial layer of 32-
Second sub-district；4- third epitaxial layer；5- fourth epitaxial layer；6- first groove；7- second groove；8- third groove；The 4th ditch of 9-
Slot；The first injection region 10-；The second injection region 11-；12- body area；13- source region；14- gate oxidation silicon layer；15- polysilicon layer；
16- dielectric layer；17- the first metal layer；18- third metal layer.
Specific embodiment
It below will the present invention will be described in more detail refering to attached drawing.In various figures, identical element uses similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use that " A is directly on B herein to describe located immediately at another layer, another region above scenario
The expression method of face " or " A on B and therewith abut ".In this application, " A is in B " indicates that A is located in B, and
And A and B is abutted directly against, rather than A is located in the doped region formed in B.
In this application, term " semiconductor structure " refers to entire half formed in each step of manufacturing semiconductor devices
The general designation of conductor structure, including all layers formed or region.
Many specific details of the invention, such as structure, material, the size, processing side of device are described hereinafter
Method and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
A kind of power device provided in an embodiment of the present invention and preparation method thereof is carried out below in conjunction with Fig. 1 to Fig. 8 detailed
Explanation.
The embodiment of the present invention provides a kind of preparation method of power device, the function that one embodiment as shown in Figure 1 provides
The preparation method of the flow diagram of the preparation method of rate device, the power device includes:
Step S1: the substrate 1 of the first conduction type is provided；
Step S2: the first epitaxial layer 2 of the first conduction type is formed in 1 upper surface of substrate；
Step S3: 2 upper surface of the first epitaxial layer formed first groove 6, the first groove 6 at least two,
And the quantity of the first groove 6 is even number；
Step S4: the first injection region of the second conduction type is formed in the bottom surface of the first groove 6 by injection mode
10；
Step S5: the second epitaxial layer 3 of the second conduction type is filled in the first groove 6；
Step S6: the part for etching first epitaxial layer 2 and second epitaxial layer 3 forms second groove 7, and described
The depth of second groove 7 is less than the first groove 6；
Step S7: third groove 8 is formed in 2 upper surface of the first epitaxial layer, the third groove 8 is located at described in two
Between second groove 7, the depth of the third groove 8 is less than the depth of the first groove 6；
The 4th groove 9 is formed below the third groove 8, the 4th groove 9 is connect with the third groove 8, institute
The width for stating the 4th groove 9 is greater than the width of the third groove 8；
Step S8: the second injection region of the second conduction type is formed in the bottom surface of the 4th groove 9 by injection mode
11；
Step S9: the third epitaxial layer 4 of the first conduction type, second epitaxial layer 3 are filled in the second groove 7
For L-type, the medial surface of second epitaxial layer 3 covers side and the portion bottom surface of the third epitaxial layer 4, the third extension
The portion bottom surface of layer 4 is connect with first epitaxial layer 2, and the ion concentration of the third epitaxial layer 4 is greater than first extension
The ion concentration of layer 2；
Step S10: the fourth epitaxial layer of the first conduction type is filled in the third groove 8 and the 4th groove 9
5, the ion concentration of the fourth epitaxial layer 5 is greater than the ion concentration of first epitaxial layer 2；
Step S11: 12 He of body area of the second conduction type is formed in 4 upper surface of third epitaxial layer by injection mode
The source region 13 of the first conduction type is formed in 12 upper surface of body area, second epitaxial layer 3 wraps jointly with the body area 12
Wrap up in the remainder of the third epitaxial layer 4；
2 upper surface of the first epitaxial layer formed gate oxidation silicon layer 14,14 lower surface of gate oxidation silicon layer with
The fourth epitaxial layer 5 connects, and one end of the gate oxidation silicon layer 14 is connect with the source region 13；
Polysilicon layer 15 is formed in 14 upper surface of gate oxidation silicon layer；
Dielectric layer 16 is formed above first epitaxial layer 2 and the polysilicon layer 15；
Form the first metal layer 17 above the dielectric layer 16, the first metal layer 17 through the dielectric layer 16 with
The connection of source region 13 forms source electrode；
Form second metal layer above the dielectric layer 16, the second metal layer through the dielectric layer 16 with it is described
The connection of polysilicon layer 15 forms grid；
Third metal layer 18 is formed in 1 lower surface of substrate, the third metal layer 18 connect formation with the substrate 1
Drain electrode.
Technical solution of the present invention is related to designing and manufacturing for semiconductor devices, and semiconductor refers to that a kind of electric conductivity can be controlled
System, conductive extensions can be from insulator to the material changed between conductor, and common semiconductor material has silicon, germanium, GaAs etc., and
Silicon is most powerful, one kind for being most widely used in various semiconductor materials.Semiconductor is divided into intrinsic semiconductor, p-type
Semiconductor and N-type semiconductor, free from foreign meter and without lattice defect semiconductor is known as intrinsic semiconductor, in pure silicon crystal
It mixes triad (such as boron, indium, gallium), is allowed to replace the seat of silicon atom in lattice, P-type semiconductor is just formed, pure
Silicon crystal in mix pentad (such as phosphorus, arsenic), be allowed to replace the position of silicon atom in lattice, be formed N-type and partly lead
The conduction type of body, P-type semiconductor and N-type semiconductor is different, and in an embodiment of the present invention, the first conduction type is N-type, the
Two conduction types are p-type, in an embodiment of the present invention, if not otherwise specified, the preferred doping of every kind of conduction type from
Son is all that can be changed to the ion with same conductivity type, is just repeated no more below.
Specifically, the substrate 1 is the carrier in integrated circuit, and the substrate 1 plays the role of support, the substrate 1
Also assist in the work of the integrated circuit.The substrate 1 can be silicon substrate 1, or Sapphire Substrate 1 can also be
Silicon carbide substrates 1, it might even be possible to be silicon Chu substrate 1, it is preferred that the substrate 1 is silicon substrate 1, this is because 1 material of silicon substrate
Have the characteristics that low cost, large scale, conductive, avoids edge effect, yield can be increased substantially.In reality of the invention
Apply in example, the substrate 1 is the substrate 1 of the first conduction type, and first conduction type is N-type, the doping of the substrate 1 from
Son is phosphorus or arsenic etc., and 1 doping concentration of substrate is highly doped.
Referring next to attached drawing, the preparation method of power device described above is elaborated.
Attached drawing 2 is please referred to, step S1, S2 is executed, specifically: the substrate 1 of the first conduction type is provided；In the substrate 1
Upper surface forms the first epitaxial layer 2 of the first conduction type.Wherein epitaxial growth shape can be used in 1 upper surface of substrate
At first epitaxial layer 2 can also be formed in 1 upper surface of substrate by ion implanting and/or the method for diffusion.Into one
Step ground, can be epitaxially-formed in the 1 upper surface use of substrate, can also pass through ion implanting and/or diffusion P elements
Or the method for any combination of arsenic element or both forms first epitaxial layer 2 in 1 upper surface of substrate.Specifically, institute
The method for stating extension or diffusion includes depositing operation.In some embodiments of the invention, depositing operation can be used described
1 upper surface of substrate forms first epitaxial layer 2, for example, depositing operation can be selected from electron beam evaporation, chemical vapor deposition
One of product, atomic layer deposition, sputtering.Preferably, it is formed outside described first on the substrate 1 using chemical vapor deposition
Prolong layer 2, chemical vapor deposition includes process for vapor phase epitaxy.In production, chemical vapor deposition uses process for vapor phase epitaxy mostly,
First epitaxial layer 2 is formed using process for vapor phase epitaxy in 1 upper surface of substrate, silicon material can be improved in process for vapor phase epitaxy
The perfection of material improves the integrated level of device, reaches raising minority carrier life time, reduces the leakage current of storage element.Further, institute
The doping concentration for stating substrate 1 is different from the doping concentration of first epitaxial layer 2.Preferably, the doping concentration of the substrate 1 is high
In the doping concentration of first epitaxial layer 2, the resistivity of substrate 1 described in the resistivity ratio of first epitaxial layer 2 is high at this time,
Reduce dead resistance, to improve the breakdown reverse voltage of device.
Attached drawing 2 is please referred to, step S3 is executed, specifically: first groove 6, institute are formed in 2 upper surface of the first epitaxial layer
First groove 6 at least two is stated, and the quantity of the first groove 6 is even number, several first grooves 6 are not connected to, phase
In 2 upper surface of the first epitaxial layer, there are gaps between mutually.Meanwhile the first groove 6 extends to first epitaxial layer 2
Inside, the depth of the first groove 6 is less than the thickness of first epitaxial layer 2, so that the first groove 6 does not extend into
In the substrate 1, also it is not connect with the substrate 1, therefore filled in the first groove 6 in subsequent process steps
Substance will not be connect with the substrate 1.In some embodiments of the invention, in the upper surface system of first epitaxial layer 2
Standby mask material, the mask material is specially the first photoresist, is run through on first photoresist layer by etching to be formed
The first groove 6 of first epitaxial layer 2, then remove first photoresist, the first groove 6 not with the substrate
1 connection.Wherein, the method for etching includes dry etching and wet etching, it is preferred that the method for the etching used is dry method quarter
Erosion, dry etching includes photoablation, gaseous corrosion, plasma etching etc., and dry etching easily realizes automation, treatment process
It is not introduced into pollution, cleannes height.
It please refers to attached drawing 3, executes step S4, specifically: the is formed in the bottom surface of the first groove 6 by injection mode
First injection region 10 of two conduction types.At least partly surface exposure of first injection region 10 is in 6 bottom of first groove
Face.First injection region 10 can also pass through ion implanting and/or the method shape of diffusion by being epitaxially-formed
At.Further, first injection region 10 can also pass through ion implanting and/or diffusion by being epitaxially-formed
The method of any combination of boron element or phosphide element or aluminium element or three is formed.Preferably, the side of ion implanting can be used
Method forms first injection region 10, and total agent of impurity can accurately be controlled by forming first injection region 10 by ion implanting
Amount, depth distribution and surface uniformity, can prevent spreading again for original impurity, while can realize self-aligned technology, to reduce electricity
Hold effect.
Attached drawing 4 is please referred to, step S5 is executed, specifically: the second of the second conduction type is filled in the first groove 6
Epitaxial layer 3.Extension, diffusion and/or the method for injection wherein can be used and form second epitaxial layer 3, it is specifically, described outer
The method prolonged or spread includes depositing operation.It is possible to further use extension, diffusion and/or injection boron element or phosphide element
Or the method for any combination of aluminium element or three forms second epitaxial layer 3.Second epitaxial layer 3 is by first ditch
The covering of 6 bottom surface of slot, and it is equipped with certain thickness, the upper surface of the upper surface of second epitaxial layer 3 and first epitaxial layer 2
Substantially maintain an equal level, in some embodiments, substantially maintains an equal level and refer to 3 upper surface of the second epitaxial layer than on first epitaxial layer 2
Surface is high, and 3 upper surface of the second epitaxial layer can also be lower than 2 upper surface of the first epitaxial layer in further embodiments,
The difference in height of the two is specially in technical process in acceptable error range.Further, the ion of second epitaxial layer 3
Concentration is greater than the ion concentration of first injection region 10.When the work of power device forward direction, such structure setting is conducive to increase
The anti-breakdown voltage capabilities of the strong power device.
It please refers to attached drawing 5, executes step S6, specifically: etch first epitaxial layer 2 and second epitaxial layer 3
Part forms second groove 7, and the depth of the second groove 7 is less than the first groove 6.Further, described the is etched
The part of one epitaxial layer 2 and second epitaxial layer 3 forms second groove 7, specifically includes: outside etching two neighboring described second
Prolong the part of layer 3 and first epitaxial layer 2 of intermediate portion to form the second groove 7.The one of the second groove 7
Side is to etch away the side of second epitaxial layer 3 and formed, so that second epitaxial layer 3 forms the second epitaxial layer of L-type
First sub-district 31；The other side of the second groove 7 is to etch away another second extension adjacent with second epitaxial layer 3
Layer 3 side and formed, form it into second the second sub-district of epitaxial layer 32 of L-type；The middle section of the second groove 7 simultaneously
To etch away first extension between first sub-district of the second epitaxial layer 31 and second sub-district of the second epitaxial layer 32
Layer 2 a part and formed.The upper surface of the second groove 7 and the upper surface of first epitaxial layer 2 substantially maintain an equal level.At this
In some embodiments of invention, mask material is prepared in the upper surface of first epitaxial layer 2 and second epitaxial layer 3, institute
Stating mask material is specially the second photoresist, is formed on second photoresist layer by etching and runs through first epitaxial layer
2 and second epitaxial layer 3 the second groove 7, then remove second photoresist.Wherein, the method for etching includes that dry method is carved
Erosion and wet etching, it is preferred that the method for the etching used be dry etching, dry etching include photoablation, gaseous corrosion, etc.
Gas ions corrosion etc., and dry etching easily realizes that automation, treatment process are not introduced into pollution, cleannes height.
Attached drawing 5 is please referred to, step S7 is executed, specifically: third groove 8, institute are formed in 2 upper surface of the first epitaxial layer
Third groove 8 is stated between two second grooves 7, the depth of the third groove 8 is less than the depth of the first groove 6
Degree.In some embodiments of the invention, mask material, the mask material are prepared in the upper surface of first epitaxial layer 2
Specially third photoresist forms described the through first epitaxial layer 2 by etching on the third photoresist layer
Three grooves 8, then remove the third photoresist.Wherein, the method for etching includes dry etching and wet etching, it is preferred that is made
The method of etching is dry etching, and dry etching includes photoablation, gaseous corrosion, plasma etching etc., and dry method is carved
Erosion easily realizes that automation, treatment process are not introduced into pollution, cleannes height.In the same way, rectangular under the third groove 8
At the 4th groove 9, the 4th groove 9 is connect with the third groove 8, and the width of the 4th groove 9 is greater than the third
The width of groove 8.Further, the depth of the 4th groove 9 is less than the depth of the third groove 8.The first groove 6
Depth be greater than the sum of the third groove 8 and 9 depth of the 4th groove.
It please refers to attached drawing 6, executes step S8, specifically: the is formed in the bottom surface of the 4th groove 9 by injection mode
Second injection region 11 of two conduction types.Further, the ion concentration of second injection region 11 and first injection region
10 ion concentration is roughly equal.At least partly surface exposure of second injection region 11 is in 9 bottom surface of the 4th groove.Institute
Stating the second injection region 11 can also be formed by being epitaxially-formed by ion implanting and/or the method for diffusion.Into one
Step ground, second injection region 11 can by being epitaxially-formed, can also by ion implanting and/or diffusion boron element or
The method of any combination of phosphide element or aluminium element or three is formed.Preferably, the method that ion implanting can be used forms institute
The second injection region 11 is stated, the accumulated dose of impurity, depth point can accurately be controlled by forming second injection region 11 by ion implanting
Cloth and surface uniformity can prevent spreading again for original impurity, while can realize self-aligned technology, to reduce capacity effect.
Attached drawing 7 is please referred to, step S9 is executed, specifically: the third of the first conduction type is filled in the second groove 7
Epitaxial layer 4, second epitaxial layer 3 are L-type, and the medial surface of second epitaxial layer 3 covers the side of the third epitaxial layer 4
And portion bottom surface, the portion bottom surface of the third epitaxial layer 4 are connect with first epitaxial layer 2, the third epitaxial layer 4 from
Sub- concentration is greater than the ion concentration of first epitaxial layer 2.Specifically, it is filled outside the third in 7 bottom surface of second groove
Prolong layer 4, and the third epitaxial layer 4 is equipped with certain thickness, 4 upper surface of third epitaxial layer and second epitaxial layer 3
Upper surface maintains an equal level.The thickness of the third epitaxial layer 4 is less than the thickness of second epitaxial layer 3, and the third epitaxial layer 4
Bottom surface is not connect with the bottom surface of second epitaxial layer 3.The third epitaxial layer 4 only connects with 3 side of the second epitaxial layer
It connects, so that second epitaxial layer 3 is L-type, another adjacent with second extension of the other side of the third epitaxial layer 4
The side of second epitaxial layer 3 connects.The PN junction that second epitaxial layer 3 is formed with the third epitaxial layer 4, is conducive to power device
The anti-breakdown voltage capabilities of part improve.
It please refers to attached drawing 7, executes step S10, specifically: the is filled in the third groove 8 and the 4th groove 9
The fourth epitaxial layer 5 of one conduction type, the ion that the ion concentration of the fourth epitaxial layer 5 is greater than first epitaxial layer 2 are dense
Degree.Extension, diffusion and/or the method for injection wherein can be used and form the fourth epitaxial layer 5, specifically, the extension or
The method of diffusion includes depositing operation.It is possible to further use extension, diffusion and/or injection P elements or arsenic element or two
The method of any combination of person forms the fourth epitaxial layer 5.The fourth epitaxial layer 5 covers 9 bottom surface of the 4th groove,
And it is equipped with certain thickness, the upper surface of the upper surface of the fourth epitaxial layer 5 and first epitaxial layer 2 substantially maintains an equal level.Into
One step, the ion concentration of the third epitaxial layer 4 and the ion concentration of the fourth epitaxial layer 5 are roughly equal.
Attached drawing 8 is please referred to, step S11 is executed, specifically: by injection mode in the 4 upper surface shape of third epitaxial layer
The source region 13 of the first conduction type is formed at the body area 12 of the second conduction type and in 12 upper surface of body area, outside described second
Prolong floor 3 and the remainder of the third epitaxial layer 4 is wrapped up in the body area 12 jointly.Specifically, on the third epitaxial layer 4
Surface forms the body area 12, and at least partly surface exposure in the body area 12 is in the upper surface of the third epitaxial layer 4.It is described
The both ends in body area 12 and the both ends of the third epitaxial layer 4 are substantially aligned.At least one described body area 12 of the power device,
The different body areas 12 is located in the different third epitaxial layers 4.Second epitaxial layer 3 wraps jointly with the body area 12
The remainder of the third epitaxial layer 4 is wrapped up in, the side of 4 remainder of third epitaxial layer is connect with the body area 12, separately
Side is connect with second epitaxial layer 3.The bottom surface in body area 12 described in technical process extends to first epitaxial layer 2
Interior, the side in the body area 12 extends to and first sub-district of the second epitaxial layer 31 and second sub-district of the second epitaxial layer 32
L-type two ends connection so that the body area 12 and second epitaxial layer 3 wrap up the third epitaxial layer 4.Institute
The area Shu Ti 12 can also be formed by being epitaxially-formed by ion implanting and/or the method for diffusion.Specifically, institute
The area Shu Ti 12 can also pass through ion implanting and/or diffusion boron element or phosphide element or aluminium member by being epitaxially-formed
The method of any combination of element or three is formed.Preferably, the method that ion implanting can be used forms the body area 12, passes through
Ion implanting, which forms the body area 12, can accurately control the accumulated dose, depth distribution and surface uniformity of impurity.Pass through injection mode
The source region 13 of the first conduction type is formed in 12 upper surface of body area.
2 upper surface of the first epitaxial layer formed gate oxidation silicon layer 14,14 lower surface of gate oxidation silicon layer with
The fourth epitaxial layer 5 connects, and one end of the gate oxidation silicon layer 14 is connect with the source region 13；In the gate oxidation silicon
14 upper surface of layer form polysilicon layer 15.Dielectric layer 16 is formed above first epitaxial layer 2 and the polysilicon layer 15；?
The first metal layer 17 is formed above the dielectric layer 16, the first metal layer 17 is through the dielectric layer 16 and the source region 13
Connection forms source electrode；Second metal layer is formed above the dielectric layer 16, the second metal layer runs through the dielectric layer 16
It connect to form grid with the polysilicon layer 15；Third metal layer 18, the third metal layer are formed in 1 lower surface of substrate
18 connect formation drain electrode with the substrate 1.It specifically includes: forming gate oxidation silicon layer 14 in 2 upper surface of the first epitaxial layer,
1415 lower surface of gate oxidation silicon layer is connect with the fourth epitaxial layer 5, one end of the gate oxidation silicon layer 14 and institute
The connection of source region 13 is stated, sputtering can be used for the gate oxidation silicon layer 14 or thermal oxide is formed.In the gate oxidation silicon layer 14
Upper surface forms polysilicon layer 15, and the both ends of the polysilicon layer 15 are aligned with the both ends of the gate oxidation silicon layer 14 respectively.
Dielectric layer 16 is formed above first epitaxial layer 2 and the polysilicon layer 15, the dielectric layer 16 is insulating layer, is given an account of
Sputtering can be used in matter layer 16 or thermal oxide is formed, and in subsequent doping step, the dielectric layer 16 is used as protective layer, and
Insulating layer as resulting devices is played into insulating effect.Contact hole is formed in 16 upper surface of dielectric layer, the contact hole passes through
It wears the dielectric layer 16 and the contact hole bottom is connect with the source region 13 far from described 14 one end of gate oxidation silicon layer.At this
In some embodiments of invention, mask material is prepared in the upper surface of the dielectric layer 16, the mask material is specially the 5th
Photoresist is formed by etching on the 5th photoresist and extends to 13 upper surface of source region through the dielectric layer 16
The contact hole, then remove the 5th photoresist.Wherein, the method for etching includes dry etching and wet etching, it is preferred that
The method of the etching used is dry etching, and dry etching includes photoablation, gaseous corrosion, plasma etching etc., and dry method
Etching easily realizes that automation, treatment process are not introduced into pollution, cleannes height.In some embodiments of the invention, the contact
The bottom surface in hole is connected with the source region 13, for example, the bottom surface of the contact hole extends in the source region 13, it is described to connect
The bottom surface of contact hole can also be connect with the upper surface of the source region 13, guarantee that the contact hole bottom surface is contacted with the source region 13.
The first metal layer 17 is formed in 16 upper surface of dielectric layer, the first metal layer 17 further includes filling in the contact hole
Part, the first metal layer 17 connect to form source electrode through the dielectric layer 16 with the source region 13.The contact hole
Quantity is at least one.Fig. 8 is a sectional view of the power device, without showing the second metal layer, institute in figure
Second metal layer is stated to connect to form grid with the polysilicon layer 15 through the dielectric layer 16.The second metal layer not with institute
State the connection of the first metal layer 17.Third metal is formed in 1 lower surface of substrate, the third metal is connect with the substrate 1
Form drain electrode.
A kind of power device provided in an embodiment of the present invention is described in detail below in conjunction with Fig. 1 to Fig. 8.
Present invention implementation provides a kind of power device, and the power device includes:
The substrate 1 of first conduction type；
It is formed in the first epitaxial layer 2 of the first conduction type of 1 upper surface of substrate；
Source region 13 and the package institute of the first conduction type of 2 upper surface of the first epitaxial layer are formed in by injection mode
State the body area 12 of the second conduction type of source region 13；
It is formed in the third epitaxial layer 4 of the first conduction type of 12 two sides of body area；
Wrap up the second epitaxial layer 3 of the second conduction type of the third epitaxial layer 4 jointly with the body area 12；
The first injection region 10 of the second conduction type of 3 lower surface of the second epitaxial layer is formed in by injection mode；
It is formed in the third groove 8 of 2 upper surface of the first epitaxial layer, the third groove 8 is located at two described second
Between groove 7, the depth of the third groove 8 is less than the depth of the first groove 6；
It is formed in the 4th groove 9 of 8 lower section of third groove, the 4th groove 9 is connect with the third groove 8,
The width of 4th groove 9 is greater than the width of the third groove 8；
The second injection region 11 of the second conduction type of the bottom surface of the 4th groove 9 is formed in by injection mode；
It is filled in the fourth epitaxial layer 5 of the third groove 8 and the first conduction type in the 4th groove 9, it is described
The ion concentration of fourth epitaxial layer 5 is greater than the ion concentration of first epitaxial layer 2；
It is formed in the gate oxidation silicon layer 14 of 2 upper surface of the first epitaxial layer, 14 lower surface of gate oxidation silicon layer
It is connect with the fourth epitaxial layer 5, one end of the gate oxidation silicon layer 14 is connect with the source region 13；
It is formed in the polysilicon layer 15 of 14 upper surface of gate oxidation silicon layer；
It is formed in the dielectric layer 16 of 15 top of first epitaxial layer 2 and the polysilicon layer；
It is formed in the first metal layer 17 of 16 top of dielectric layer, the first metal layer 17 runs through the dielectric layer 16
It connect to form source electrode with the source region 13；
It is formed in the second metal layer of 16 top of dielectric layer, the second metal layer runs through the dielectric layer 16 and institute
It states the connection of polysilicon layer 15 and forms grid；
It is formed in the third metal layer 18 of 1 lower surface of substrate, the third metal layer 18 connect shape with the substrate 1
At drain electrode.
Technical solution of the present invention is related to designing and manufacturing for semiconductor devices, and semiconductor refers to that a kind of electric conductivity can be controlled
System, conductive extensions can be from insulator to the material changed between conductor, and common semiconductor material has silicon, germanium, GaAs etc., and
Silicon is most powerful, one kind for being most widely used in various semiconductor materials.Semiconductor is divided into intrinsic semiconductor, p-type
Semiconductor and N-type semiconductor, free from foreign meter and without lattice defect semiconductor is known as intrinsic semiconductor, in pure silicon crystal
It mixes triad (such as boron, indium, gallium), is allowed to replace the seat of silicon atom in lattice, P-type semiconductor is just formed, pure
Silicon crystal in mix pentad (such as phosphorus, arsenic), be allowed to replace the position of silicon atom in lattice, be formed N-type and partly lead
The conduction type of body, P-type semiconductor and N-type semiconductor is different, and in an embodiment of the present invention, the first conduction type is N-type, the
Two conduction types are p-type, in an embodiment of the present invention, if not otherwise specified, the preferred doping of every kind of conduction type from
Son is all that can be changed to the ion with same conductivity type, is just repeated no more below.
Specifically, the substrate 1 is the carrier in integrated circuit, and the substrate 1 plays the role of support, the substrate 1
Also assist in the work of the integrated circuit.The substrate 1 can be silicon substrate 1, or Sapphire Substrate 1 can also be
Silicon carbide substrates 1, it might even be possible to be silicon Chu substrate 1, it is preferred that the substrate 1 is silicon substrate 1, this is because 1 material of silicon substrate
Have the characteristics that low cost, large scale, conductive, avoids edge effect, yield can be increased substantially.In reality of the invention
Apply in example, the substrate 1 is the substrate 1 of the first conduction type, and first conduction type is N-type, the doping of the substrate 1 from
Son is phosphorus or arsenic etc., and 1 doping concentration of substrate is highly doped.
Referring next to attached drawing, power device described above is elaborated.
In some embodiments of the invention, as shown in Fig. 2, the power device includes the substrate 1 of the first conduction type,
It is formed in the first epitaxial layer 2 of the first conduction type of 1 upper surface of substrate.The doping concentration of the substrate 1 and described the
The doping concentration of one epitaxial layer 2 is different.Preferably, the doping concentration of the substrate 1 is dense higher than the doping of first epitaxial layer 2
Degree, the resistivity of substrate 1 described in the resistivity ratio of first epitaxial layer 2 is high at this time, reduces dead resistance, to improve device
The breakdown reverse voltage of part.
In some embodiments of the invention, as shown in figure 8, the power device includes being formed in institute by injection mode
It states the source region 13 of the first conduction type of 2 upper surface of the first epitaxial layer and wraps up the body area of the second conduction type of the source region 13
12.The body area 12 can also be formed by being epitaxially-formed by ion implanting and/or the method for diffusion.Specifically
Ground, the body area 12 can by being epitaxially-formed, can also by ion implanting and/or diffusion boron element or phosphide element or
The method of any combination of aluminium element or three is formed.Preferably, the method that ion implanting can be used forms the body area 12,
The accumulated dose, depth distribution and surface uniformity of impurity can accurately be controlled by forming the body area 12 by ion implanting.The body area
12 at least partly surface exposure is in the upper surface of the third epitaxial layer 4.The both ends in the body area 12 and the third extension
The both ends of layer 4 are substantially aligned.At least one described body area 12 of the power device, the different body areas 12 are located at different
In the third epitaxial layer 4.The source region 13 of the first conduction type is formed in 12 upper surface of body area by injection mode.
In some embodiments of the invention, as shown in figure 8, the power device includes being formed in 12 two sides of body area
The first conduction type third epitaxial layer 4；Wrap up the second conduction type of the third epitaxial layer 4 jointly with the body area 12
The second epitaxial layer 3.Second epitaxial layer 3 wraps up the remainder of the third epitaxial layer 4, institute with the body area 12 jointly
The side for stating 4 remainder of third epitaxial layer is connect with the body area 12, and the other side is connect with second epitaxial layer 3.In work
The bottom surface in the body area 12 extends in first epitaxial layer 2 during skill, the side in the body area 12 extend to it is described
Second the first sub-district of epitaxial layer 31 is connected with two ends of the L-type of second sub-district of the second epitaxial layer 32, so that described
Body area 12 and second epitaxial layer 3 wrap up the third epitaxial layer 4.Second epitaxial layer 3 and the third epitaxial layer 4
The PN junction of formation, the anti-breakdown voltage capabilities for being conducive to power device improve.
In some embodiments of the invention, as shown in figure 8, the power device includes being formed in institute by injection mode
State the first injection region 10 of the second conduction type of 3 lower surface of the second epitaxial layer.Further, second epitaxial layer 3 from
Sub- concentration is greater than the ion concentration of first injection region 10.This structure setting is conducive to enhance the anti-breakdown voltage of power device
Ability.
In some embodiments of the invention, as shown in figure 8, the power device includes being formed in first epitaxial layer
The third groove 8 of 2 upper surfaces, the third groove 8 are located between two second grooves 7, the depth of the third groove 8
Less than the depth of the first groove 6；It is formed in the 4th groove 9 of 8 lower section of third groove, the 4th groove 9 and institute
The connection of third groove 8 is stated, the width of the 4th groove 9 is greater than the width of the third groove 8；It is formed in by injection mode
Second injection region 11 of the second conduction type of the bottom surface of the 4th groove 9；It is filled in the third groove 8 and the described 4th
The ion concentration of the fourth epitaxial layer 5 of the first conduction type in groove 9, the fourth epitaxial layer 5 is greater than first extension
The ion concentration of layer 2.Further, the thickness of second epitaxial layer 3 is greater than 5 thickness of fourth epitaxial layer.Described 4th
The ion concentration of epitaxial layer 5 is greater than the ion concentration of first epitaxial layer 2, this structure setting advantageously reduces power device
Conducting resistance.
In some embodiments of the invention, as shown in figure 8, the power device includes being formed in first epitaxial layer
The gate oxidation silicon layer 14 of 2 upper surfaces, 14 lower surface of gate oxidation silicon layer are connect with the fourth epitaxial layer 5, the grid
One end of pole silicon oxide layer 14 is connect with the source region 13；It is formed in the polysilicon layer of 14 upper surface of gate oxidation silicon layer
15；It is formed in the dielectric layer 16 of 15 top of first epitaxial layer 2 and the polysilicon layer；It is formed in 16 top of dielectric layer
The first metal layer 17, the first metal layer 17 connect to form source electrode through the dielectric layer 16 with the source region 13；It is formed
Second metal layer above the dielectric layer 16, the second metal layer is through the dielectric layer 16 and the polysilicon layer 15
Connection forms grid；It is formed in the third metal layer 18 of 1 lower surface of substrate, the third metal layer 18 and the substrate 1
Connection forms drain electrode.
The technical scheme of the present invention has been explained in detail above with reference to the attached drawings, according to the technical solution of the present invention, proposes one
Kind of the power device with inverted T shaped extension supplementary structure increases the third epitaxial layer and the of the first conduction type around body area
Second epitaxial layer of two conduction types, and the first injection region of the second conduction type is set below the second epitaxial layer, not
In the case where increasing epitaxy layer thickness and not changing epitaxial layer concentration, the area of depletion region is increased, improves device breakdown electricity
Pressure, and since epitaxial thickness and concentration do not change, the conducting resistance of device not will increase；It is increased in epitaxial layer simultaneously
Fourth epitaxial layer, which is less than epitaxial layer, and the second injection region is arranged below fourth epitaxial layer, drops
The low conducting resistance of device, therefore the power device of the structure setting had both increased the breakdown voltage of device, reduced simultaneously
The conducting resistance of device improves the performance of VDMOS device.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of preparation method of power device characterized by comprising
The substrate of first conduction type is provided；
Surface forms the first epitaxial layer of the first conduction type over the substrate；
First groove, the first groove at least two, and the first groove are formed in first epitaxial layer upper surface
Quantity be even number；
The first injection region of the second conduction type is formed in the bottom surface of the first groove by injection mode；
The second epitaxial layer of the second conduction type is filled in the first groove；
The part for etching first epitaxial layer and second epitaxial layer forms second groove, and the depth of the second groove
Less than the first groove；
Third groove is formed in first epitaxial layer upper surface, the third groove is located between two second grooves,
The depth of the third groove is less than the depth of the first groove；
The 4th groove is formed in the third beneath trenches, the 4th groove is connect with the third groove, the 4th ditch
The width of slot is greater than the width of the third groove；
The second injection region of the second conduction type is formed in the bottom surface of the 4th groove by injection mode；
Fill the third epitaxial layer of the first conduction type in the second groove, second epitaxial layer is L-type, described second
The medial surface of epitaxial layer covers side and the portion bottom surface of the third epitaxial layer, the portion bottom surface of the third epitaxial layer and institute
The connection of the first epitaxial layer is stated, the ion concentration of the third epitaxial layer is greater than the ion concentration of first epitaxial layer；
The fourth epitaxial layer of the first conduction type, the fourth epitaxial layer are filled in the third groove and the 4th groove
Ion concentration be greater than first epitaxial layer ion concentration；
Body area by injection mode in the second conduction type of third epitaxial layer upper surface formation and the table in the body area
Face forms the source region of the first conduction type, and the residue of the third epitaxial layer is wrapped up in second epitaxial layer and the body area jointly
Part；
Outside first epitaxial layer upper surface formation gate oxidation silicon layer, gate oxidation silicon layer lower surface and the described 4th
Prolong layer connection, one end of the gate oxidation silicon layer is connect with the source region；
Polysilicon layer is formed in gate oxidation silicon layer upper surface；
Dielectric layer is formed above first epitaxial layer and the polysilicon layer；
The first metal layer is formed above the dielectric layer, the first metal layer is connect through the dielectric layer with the source region
Form source electrode；
Second metal layer is formed above the dielectric layer, the second metal layer is through the dielectric layer and the polysilicon layer
Connection forms grid；
Third metal layer is formed in the substrate lower surface, the third metal layer connect to form drain electrode with the substrate.
2. the preparation method of power device according to claim 1, which is characterized in that the ion of second epitaxial layer is dense
Degree is greater than the ion concentration of first injection region.
3. the preparation method of power device according to claim 1, which is characterized in that the depth of the first groove is greater than
The sum of the third groove and the 4th trench depth.
4. the preparation method of power device according to claim 1, which is characterized in that etching first epitaxial layer and institute
The part for stating the second epitaxial layer forms second groove, specifically includes: the part of two neighboring second epitaxial layer of etching and its
First epitaxial layer of middle section is to form the second groove.
5. the preparation method of power device according to claim 1, which is characterized in that the depth of the 4th groove is less than
The depth of the third groove.
6. the preparation method of power device according to claim 1, which is characterized in that the ion of second injection region is dense
It spends roughly equal with the ion concentration of first injection region.
7. the preparation method of power device according to claim 1, which is characterized in that the ion of the third epitaxial layer is dense
It spends roughly equal with the ion concentration of the fourth epitaxial layer.
8. a kind of power device characterized by comprising
The substrate of first conduction type；
It is formed in the first epitaxial layer of the first conduction type of the upper surface of substrate；
The source region of the first conduction type of first epitaxial layer upper surface is formed in by injection mode and wraps up the source region
The second conduction type body area；
It is formed in the third epitaxial layer of the first conduction type of body area two sides；
Wrap up the second epitaxial layer of the second conduction type of the third epitaxial layer jointly with the body area；
The first injection region of the second conduction type of second epitaxial layer lower surface is formed in by injection mode；
Be formed in the third groove of first epitaxial layer upper surface, the third groove be located at two second grooves it
Between, the depth of the third groove is less than the depth of the first groove；
It is formed in the 4th groove of the third beneath trenches, the 4th groove is connect with the third groove, and the described 4th
The width of groove is greater than the width of the third groove；
The second injection region of the second conduction type of the bottom surface of the 4th groove is formed in by injection mode；
It is filled in the fourth epitaxial layer of the third groove and the first conduction type in the 4th groove, the fourth epitaxial
The ion concentration of layer is greater than the ion concentration of first epitaxial layer；
It is formed in the gate oxidation silicon layer of first epitaxial layer upper surface, gate oxidation silicon layer lower surface and the described 4th
Epitaxial layer connection, one end of the gate oxidation silicon layer is connect with the source region；
It is formed in the polysilicon layer of gate oxidation silicon layer upper surface；
The dielectric layer being formed in above first epitaxial layer and the polysilicon layer；
The first metal layer being formed in above the dielectric layer, the first metal layer connect through the dielectric layer and the source region
It connects to form source electrode；
The second metal layer being formed in above the dielectric layer, the second metal layer is through the dielectric layer and the polysilicon
Layer connection forms grid；
It is formed in the third metal layer of the substrate lower surface, the third metal layer connect to form drain electrode with the substrate.
9. power device according to claim 8, which is characterized in that the ion concentration of second epitaxial layer is greater than described
The ion concentration of first injection region.
10. power device according to claim 8, which is characterized in that the thickness of second epitaxial layer is greater than described the
Four epitaxy layer thickness.
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| US4743952A (en) * | 1983-04-04 | 1988-05-10 | General Electric Company | Insulated-gate semiconductor device with low on-resistance |
| JPH03133180A (en) * | 1989-10-19 | 1991-06-06 | Matsushita Electron Corp | Semiconductor device |
| EP0600229A1 (en) * | 1992-10-30 | 1994-06-08 | Nippondenso Co., Ltd. | Power semiconductor device with protective means |
| CN101211983A (en) * | 2006-12-27 | 2008-07-02 | 东部高科股份有限公司 | Semiconductor device and method for fabricating the same |
| JP2013140935A (en) * | 2012-01-05 | 2013-07-18 | Vanguard Internatl Semiconductor Corp | Semiconductor device and method of manufacturing the same |
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2018
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4743952A (en) * | 1983-04-04 | 1988-05-10 | General Electric Company | Insulated-gate semiconductor device with low on-resistance |
| JPH03133180A (en) * | 1989-10-19 | 1991-06-06 | Matsushita Electron Corp | Semiconductor device |
| EP0600229A1 (en) * | 1992-10-30 | 1994-06-08 | Nippondenso Co., Ltd. | Power semiconductor device with protective means |
| CN101211983A (en) * | 2006-12-27 | 2008-07-02 | 东部高科股份有限公司 | Semiconductor device and method for fabricating the same |
| JP2013140935A (en) * | 2012-01-05 | 2013-07-18 | Vanguard Internatl Semiconductor Corp | Semiconductor device and method of manufacturing the same |
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