CN109144793A - A kind of fault correction device and method calculated based on data flow driven - Google Patents
A kind of fault correction device and method calculated based on data flow driven Download PDFInfo
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- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
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- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
- G06F11/165—Error detection by comparing the output of redundant processing systems with continued operation after detection of the error
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Abstract
This application discloses a kind of fault correction device and method calculated based on data flow driven, which includes: the input terminal that data storage cell is set to fault correction device, for sending former data to two computing units simultaneously according to data address；Computing unit is used to carry out mirror image calculating to former data；Judging unit is used to that mirror image calculated result to be sent to data saving unit when determining that two mirror image calculated results are equal, when determining that two mirror image calculated results are unequal, generates and sends failure breakpoint address to parsing module；Data saving unit is used to generate storage address according to data address, and according to storage address memory image calculated result；Parsing module is used to obtain data address according to failure breakpoint address, and is sent to data storage cell.By the technical solution in the application, the time loss that the driving of chip data stream calculates is advantageously reduced, the resource consumption of chip is reduced, reduces the outage probability of data flow driven calculating.
Description
Technical field
This application involves the technical fields of chip operation, in particular to a kind of event calculated based on data flow driven
Hinder means for correcting and a kind of fault correction method calculated based on data flow driven.
Background technique
There is extremely strong penetration power by the cosmic ray that a variety of ray cores and single heavy ion form, electronic system can be produced
Raw greatly damage.Single-particle inversion is in the space environment of space, since single-particle injection causes the electronic component in chip to produce
Raw failure is to cause in space environment electronic system to break down and one of the main reason for operation irregularity.Existing mainstream is hard
Part accelerator generally use data flow driven calculate mode, due in high-altitude even outer space environment, often will appear by
Electronic component generates the phenomenon that failure in chip caused by single-particle inversion, influences the correctness of chip calculated result, therefore, needs
Fault detection and correction are carried out to the operation result data that data flow driven calculates.
And in the prior art, the reinforcing means generallyd use are mainly the following scheme:
1) it uses time triplication redundancy: same data being allowed to calculate three times, carry out front and back Comparative result, as long as the mistake calculated
Accidentally there is not mistake twice simultaneously in front and back, so that it may correctly avoid module error, guarantee that result correctly exports.But it counts in this way
The period of calculation can be original three times, and having to the performance of hardware accelerator itself greatly reduces, and is for supercomputing unit
It is infeasible；
2) it uses hardware triplication redundancy: three mirror modules being allowed to be performed simultaneously identical operation, with most identical
Export correct result of the result as voting system, the usually voting of two from three etc..Due to mutually independent in three modules,
It is minimum probability that the probability of mistake occur simultaneously in two modules, can greatly improve the reliability of system in this way, but also can simultaneously
Greatly increase hardware resource and system consumption；
3) conventional hardware duplication redundancy is used, allows two mirror modules to be performed simultaneously identical operation, then result data
Verification is compared, then data-flow computation is interrupted if there is different result data, and calculating restarts.The money of this method
Source consumption is a half than hardware triplication redundancy method, but the processing speed calculated will be greatly reduced, and with single-particle
The increase of probability is overturn, data flow driven is calculated also can be relatively high in the probability interrupted.
Summary of the invention
The purpose of the application is: while guaranteeing system-computed result accuracy, reducing system-computed data mistake
Time loss in journey reduces the hardware consumption of system, improves the efficiency and performance of entire computing system.
The technical solution of the application first aspect is: providing a kind of fault correction dress calculated based on data flow driven
It sets, which includes: data storage cell, two computing units, judging unit, data saving unit and parsing module；Number
The input terminal of fault correction device is set to according to storage unit, data storage cell is used to send correspondence simultaneously according to data address
Former data to two computing units；The input terminal of two computing units is connected to the output end of data storage cell, meter
Unit is calculated to be used to carry out mirror image calculating to former data；Two input terminals of judging unit are connected to the defeated of two computing units
Outlet, judging unit are used for when determining that two mirror image calculated results are equal, and mirror image calculated result is sent to data and saves list
Member, judging unit are also used to when determining that two mirror image calculated results are unequal, generate and send failure breakpoint address to parsing
Module；Data saving unit is connected to the first output end of judging unit, and data saving unit according to data address for generating
Storage address, and according to the mirror image calculated result of storage address the first computing unit of storage；The input terminal of parsing module is connected to
The output end of the second output terminal of judging unit, parsing module is connected to the input terminal of data storage cell, and parsing module is used for
Data address is obtained according to failure breakpoint address, and sends data address to data storage cell.
In any of the above-described technical solution, further, parsing module is specifically included: breakpoint storage unit and address solution
Analyse unit；Breakpoint storage unit is set to the input terminal of parsing module, and breakpoint storage unit is used for raw according to failure breakpoint address
At breakpoint list；Address resolution unit is set to the output end of parsing module, and address resolution unit is used to parse breakpoint list, and
Data address is sent to data storage cell.
In any of the above-described technical solution, further, further includes: data mask unit；Data mask unit is set to
Between the first output end and data saving unit of judging unit, data mask unit is used for when two mirror image calculated results of judgement
When unequal, low level enable signal is sent to data saving unit.
In any of the above-described technical solution, further, computing unit is butterfly computation device, and butterfly computation device includes: the
One selection switch unit, two 2 butterfly computation devices of base, the first complex adder and the second complex adder.
The technical solution of the application second aspect is: providing a kind of fault correction side calculated based on data flow driven
Method according to data address, calculates former data by two identical computing units this method comprises: step S10, respectively obtains the
One calculated result and the second calculated result；Step S20, judges whether the first calculated result is equal to the second calculated result, works as judgement
When to be, step S30 is executed, when being determined as no, executing step S40；Step S30 stores the first calculated result；Step S40,
According to the corresponding data address of the first calculated result, breakpoint list is generated；Step S50, according to breakpoint list, restoring data
Location executes step S10.
In any of the above-described technical solution, further, step S30 is specifically included: step S31, is calculated and is tied according to first
The corresponding data address of fruit generates storage address；Step S32 generates calculated result according to storage address and the first calculated result
Storage table.
In any of the above-described technical solution, further, step S50 is specifically included: step S51, is obtained in breakpoint list
Failure breakpoint address；Step S52 obtains corresponding data address according to failure breakpoint address；Step S53, according to default week
Phase sends the corresponding former data of data address, executes step S10 according to data address.
In any of the above-described technical solution, further, step S50 is specific further include: step S54, when judgement is counted again
It is corresponding according to the first calculated result recalculated when the first calculated result calculated is equal with the second calculated result recalculated
Data address, generate insertion storage address；Step S55 will be counted again according to insertion storage address and calculated result storage table
The first calculated result calculated is inserted into calculated result storage table.
The beneficial effect of the application is: by being compared to mirror image calculated result, failure breakpoint address is generated, in data
After the completion of stream driving calculates, failure breakpoint address is parsed, recalculates corresponding former data, under the premise of guaranteeing accuracy rate,
The time loss that the driving of chip data stream calculates is advantageously reduced, the resource consumption of chip is reduced, advantageously reduces chip
Cost of manufacture improves the processing speed of chip, advantageously reduces the probability for generating single-particle inversion failure, reduces data flow
Drive the outage probability calculated.
The application passes through setting first choice switch unit, two 2 butterfly computation devices of base, the first complex adder and second
Complex adder is conducive to that butterfly computation device is reconstructed, and two 2 butterfly computation devices of base are reconstructed into 13 butterfly computation of base
Device improves the utilization efficiency of electronic component, carries out operation using 3 butterfly computation device of base, is conducive to reduce and draw in calculating process
A possibility that entering noise reduces the delay in calculating process.
Detailed description of the invention
The above-mentioned and/or additional aspect and advantage of the application will become from the description of the embodiment in conjunction with the following figures
Obviously and it is readily appreciated that, in which:
Fig. 1 is the schematic block according to the fault correction device calculated based on data flow driven of one embodiment of the application
Figure；
Fig. 2 is the circuit diagram according to the butterfly computation device of one embodiment of the application；
Fig. 3 is the circuit diagram according to the 2 butterfly computation device of base of one embodiment of the application；
Fig. 4 is the circuit diagram according to the 3 butterfly computation device of base of one embodiment of the application；
Fig. 5 is the schematic diagram according to the address resolution unit storing data of one embodiment of the application；
Fig. 6 is the signal stream according to the fault correction method calculated based on data flow driven of one embodiment of the application
Cheng Tu；
Fig. 7 is the illustrative timing diagram of the fault correction calculated according to the data flow driven of one embodiment of the application.
Specific embodiment
It is with reference to the accompanying drawing and specific real in order to be more clearly understood that the above objects, features, and advantages of the application
Mode is applied the application is further described in detail.It should be noted that in the absence of conflict, the implementation of the application
Feature in example and embodiment can be combined with each other.
In the following description, many details are elaborated in order to fully understand the application, still, the application may be used also
To be implemented using other than the one described here other modes, therefore, the protection scope of the application is not by described below
Specific embodiment limitation.
Embodiment one:
The fault correction device in the present embodiment is illustrated below with reference to Fig. 1 to Fig. 5.
As shown in Figure 1, a kind of fault correction device calculated based on data flow driven in the present embodiment, comprising: data are deposited
Storage unit 10, two computing units, judging unit 30, data saving unit 40 and parsing module 50；Data storage cell 10
It is set to the input terminal of fault correction device, data storage cell 10 is used to send corresponding former data simultaneously according to data address
To two computing units；
Specifically, data storage cell 10 is by multiple random access memory (random access memory, RAM) group
At being driven using data address, send former data to two computing units, that is to say, that store in data storage cell 10
There is a data list, data storage cell 10 is according to the data address in data list, the corresponding former data in called data address,
Former data are sent to two computing units again.
In the present embodiment, the input terminal of two computing units is connected to the output end of data storage cell 10, meter
Unit is calculated to be used to carry out mirror image calculating to former data；
Specifically, two computing units can be divided into the first computing unit 21 and the second computing unit 22, between the two
Structure and function the first computing unit 21 all the same and the second computing unit 22 mirror image computing unit each other, pass through first calculate it is single
Member 21 and the second calculating of the computing unit 22 to identical data, verify two computing units whether the shadow by single-particle inversion
It rings.
Further, computing unit is butterfly computation device, and butterfly computation device includes: first choice switch unit, two bases 2
Butterfly computation device, the first complex adder and the second complex adder；
First choice switch unit is used to select corresponding conduction mode according to operational order；
Specifically, as shown in Fig. 2, first choice switch unit is made of the selector of 7 alternatives, including selector
14, selector 16, selector 17, selector 18, selector 19, selector 20 and selector 21 work as fortune by taking selector 14 as an example
When the instruction that calculation instruction inputs selector 14 is " 01 ", corresponding is 2 butterfly computation device of base, the conduction mode of selector 14
For by the input terminal A of 2 butterfly computation device of the second base2Input be sent to complex adder 8.When operational order is defeated to selector 14
When the instruction entered is " 10 ", corresponding is 3 butterfly computation device of base, and the conduction mode of selector 14 is by complex adder 7 (the
The third complex adder of one base, 2 butterfly computation device) operation result be sent to complex adder 8.
2 butterfly computation device of base includes the first complex multiplier, third complex adder and complex subtraction device, 2 butterfly of base fortune
The first input end for calculating device is connected to the first input end of third complex adder and by first choice switch unit
It is connected to the first input end of complex subtraction device, the output end of third complex adder is connected to base 2 by first choice switch
The output end of first output end of butterfly computation device, complex subtraction device is connected to 2 butterfly of base fortune by first choice switch unit
The second output terminal of device is calculated, the second input terminal and twiddle factor of 2 butterfly computation device of base are connected to the first complex multiplier
Input terminal, the output end of the first complex multiplier is connected to the second input terminal and complex subtraction of third complex adder
Second input terminal of device, 2 butterfly computation device of base are used for according to operational data and the corresponding conducting mould of first choice switch unit
Formula carries out 2 butterfly computation of base；
Wherein, 2 butterfly computation device of base includes: the first complex multiplier, third complex adder and complex subtraction device；Base 2
The first input end of butterfly computation device is connected to the first input end of third complex adder and is opened by first choice
The first input end that unit is connected to complex subtraction device is closed, the output end of third complex adder is switched by first choice to be connected
2 butterfly of base fortune is connected to by first choice switch in the output end of the first output end of 2 butterfly computation device of base, complex subtraction device
Calculate the second output terminal of device；The second input terminal and twiddle factor of 2 butterfly computation device of base are connected to the first complex multiplier
Input terminal, the output end of the first complex multiplier is connected to the second input terminal and complex subtraction of third complex adder
Second input terminal of device.
Specifically, as shown in figure 3, the input terminal A of 2 butterfly computation device of base (2 butterfly computation device of the first base)1(2 butterfly of base fortune
Calculate the first input end of device) it is connected to complex adder 7 (third complex adder) and selector 17, it will by selector 17
It is corresponding to be transferred to complex subtraction device 10 to operational data, wherein complex adder 10 is the plural number for executing complex subtraction and calculating
Adder, the output end of complex adder 7 are connected to the first output end X of 2 butterfly computation device of base by selector 181, plural number
The output end of subtracter 10 is connected to the second output terminal X of 2 butterfly computation device of base by selector 192；2 butterfly computation device of base
Second input terminal B and twiddle factor input terminal W1It is connected to complex multiplier 1 (the first complex multiplier), complex multiplier 1 will
The product being calculated is respectively sent to complex adder 7 and complex subtraction device 10.Set input terminal A1It is corresponding to operation
Digital signal is A'=(ar1+ai1* j), the corresponding digital signal to operation of input terminal B is B'=(br+bi* j), twiddle factor
For W1' then corresponding output result are as follows:
X1=A1'+B'*W1'
=[ar1+(br*wr1-bi*wi1)]+j*[ai1+(bi*wr1+br*wi1)]
X2=A1-B*W1'
=[ar1-(br*wr1-bi*wi1)]+j*[ai1-(bi*wr1+br*wi1)]
In formula, W1'=wr1+j*wi1, W2'=wr2+j*wi2。
Wherein, complex adder 9 is to execute the complex adder of complex subtraction operation.Second base, 2 butterfly computation device it is defeated
Enter to hold A2Connection type and input terminal A1Connection type it is similar, the connection of the second input terminal C of 2 butterfly computation device of the second base
Mode is similar to the connection type of the second input terminal B, and details are not described herein again.
Two 2 butterfly computation devices of base are also used to according to the corresponding conduction mode of first choice switch unit, with the first plural number
Adder and the second complex adder form a 3 butterfly computation device of base, 3 butterfly computation device of base further include: the second complex multiplication
Device, third complex multiplier, complex adder group, the first complex adder and the second complex adder, 3 butterfly computation device of base
First input end is connected to the first output of shown 3 butterfly computation device of base by complex adder group and first choice switch unit
End, the first input end of 3 butterfly computation device of base are also attached to the first input end of the first complex adder, the first complex adder
Output end be connected to the second output terminal of 3 butterfly computation device of base by first choice switch unit, the of 3 butterfly computation device of base
One input terminal is also attached to the first input end of the second complex adder, and the output end of the second complex adder passes through first choice
Switch unit is connected to the third output end of 3 butterfly computation device of base, and it is multiple that the second input terminal of 3 butterfly computation device of base is connected to second
First output end of the input terminal of number multiplier, the second complex multiplier passes through complex adder group and first choice switch unit
It is connected to the first output end of 3 butterfly computation device of base, the second output terminal of the second complex multiplier passes through displacement computing unit, the
One selection switch unit and complex adder group are connected to the second input terminal of the first complex adder, the second complex multiplier
Third output end is connected to the second complex adder by displacement computing unit, first choice switch unit and complex adder group
The second input terminal, the third input terminal of 3 butterfly computation device of base is connected to the input terminal of third complex multiplier, third complex multiplication
First output end of musical instruments used in a Buddhist or Taoist mass by complex adder group and first choice switch unit be connected to 3 butterfly computation device of base it is first defeated
Outlet, the second output terminal of third complex multiplier are connected to the first plural number by displacement computing unit and complex adder group and add
The third output end of second input terminal of musical instruments used in a Buddhist or Taoist mass, the second complex multiplier passes through displacement computing unit, first choice switch unit
The second input terminal of the second complex adder is connected to complex adder group, 3 butterfly computation device of base is for treating operational data
Carry out 3 butterfly computation of base, wherein the second complex multiplier is the first complex multiplier of a 2 butterfly computation device of base, and third is multiple
Number multiplier is the first complex multiplier of another 2 butterfly computation device of base, and complex adder group includes two 2 butterfly computations of base
The third complex adder and complex subtraction device of device.
Wherein, 3 butterfly computation device of base includes: the second complex multiplier, third complex multiplier, complex adder group,
One complex adder and the second complex adder, wherein the second complex multiplier is first plural number of a 2 butterfly computation device of base
Multiplier, third complex multiplier are the first complex multiplier of another 2 butterfly computation device of base, and complex adder group includes two
The third complex adder and complex subtraction device of a 2 butterfly computation device of base.
Specifically, as shown in figure 4, the second complex multiplier is complex multiplier 1, third complex multiplier is complex multiplication
Device 2, the first complex adder are complex adder 11, and complex adder group includes complex adder 7, complex adder 8, plural number
Adder 9 and complex adder 10.
The first input end of 3 butterfly computation device of base is connected to shown by complex adder group and first choice switch unit
First output end of 3 butterfly computation device of base, the first input end of 3 butterfly computation device of base are also attached to the of the first complex adder
The output end of one input terminal, the first complex adder is connected to the second of 3 butterfly computation device of base by first choice switch unit
Output end, the first input end of 3 butterfly computation device of base are also attached to the first input end of the second complex adder, and the second plural number adds
The output end of musical instruments used in a Buddhist or Taoist mass is connected to the third output end of 3 butterfly computation device of base by first choice switch unit；
Specifically, as shown in figure 4, input terminal A1(first input end of 3 butterfly computation device of base) is connected to complex adder 7
First input end, complex adder 11 (the first complex adder) first input end and complex adder 12 (second is multiple
Number adders) first input end, the output end of complex adder 7 is connected to the first of complex adder 8 by selector 14
The output end of input terminal, complex adder 8 is connected to output end X by selector 181(the first output of 3 butterfly computation device of base
End).The output end of complex adder 11 is connected to output end X by selector 192(the second output of 3 butterfly computation device of base
End), the output end of complex adder 12 is connected to output end X by selector 203(third of 3 butterfly computation device of base exports
End).
Second input terminal of 3 butterfly computation device of base is connected to the input terminal of the second complex multiplier, the second complex multiplier
The first output end by complex adder group and first choice switch unit be connected to 3 butterfly computation device of base first output
The second output terminal at end, the second complex multiplier passes through displacement computing unit 103, first choice switch unit and complex adder
Group is connected to the second input terminal of the first complex adder, and the third output end of the second complex multiplier passes through displacement computing unit
103, first choice switch unit and complex adder group are connected to the second input terminal of the second complex adder；
Specifically, as shown in figure 4, input terminal B (the second input terminal of 3 butterfly computation device of base) is connected to complex multiplier 1,
First output end of complex multiplier 1 is connected to the second input terminal of complex adder 7.The second output terminal of complex multiplier 1
The input terminal of selector 16 is connected to by complex multiplier 3 and shift register 22, the output end of selector 16 is connected to multiple
The first input end of number adder 9, the output end of complex adder 9 are connected to the second input terminal of complex adder 11.Plural number
The third output end of multiplier 1 is connected to the first input of complex adder 10 by complex multiplier 4 and shift register 23
End, the output end of complex adder 10 are connected to the second input terminal of complex adder 12.
The third input terminal of 3 butterfly computation device of base is connected to the input terminal of third complex multiplier, third complex multiplier
The first output end by complex adder group and first choice switch unit be connected to 3 butterfly computation device of base first output
The second output terminal at end, third complex multiplier is connected to the first plural number by displacement computing unit 103 and complex adder group
The third output end of second input terminal of adder, the second complex multiplier passes through displacement computing unit 103, first choice switch
Unit and complex adder group are connected to the second input terminal of the second complex adder；
Specifically, as shown in figure 4, input terminal C (the third input terminal of 3 butterfly computation device of base) is connected to complex multiplier 2,
First output end of complex multiplier 2 is connected to the second input terminal of complex adder 8, the second output terminal of complex multiplier 2
The second input terminal of complex adder 9, the third of complex multiplier 2 are connected to by complex multiplier 5 and shift register 24
Output end is connected to selector 17 by complex multiplier 6 and shift register 25, and the output end of selector 17 is connected to plural number
Second input terminal of adder 10.
Set input terminal A at this time1It is corresponding to operational data be A1"=(ar1+ai1* j), input terminal B is corresponding to operation
Data are B "=(br+bi* j), input terminal C it is corresponding to operational data be C "=(cr+ci* j), then corresponding output result are as follows:
In formula, W1"=wr1+j*wi1, W2"=wr2+j*wi2,
Butterfly computation device is set by computing unit, is conducive to improve the process range that computing unit calculates data, increase
The flexibility of Digital Signal Processing, especially carry out Discrete Fourier Transform (Discrete Fourier Transform,
When DTF), the DFT for being conducive to the DFT to count greatly to be converted into small point carries out operation, to realize the mesh for reducing computational complexity
's.
By the way that first choice switch unit, two 2 butterfly computation devices of base is arranged, the first complex adder and the second plural number add
Musical instruments used in a Buddhist or Taoist mass is conducive to that butterfly computation device is reconstructed, and two 2 butterfly computation devices of base are reconstructed into 1 base, 3 butterfly computation device, are mentioned
The high utilization efficiency of electronic component, carries out operation using 3 butterfly computation device of base, is conducive to reduce in calculating process and introduces noise
A possibility that, reduce the delay in calculating process.
In the present embodiment, two input terminals of judging unit 30 are connected to the output end of two computing units, sentence
Disconnected unit 30 is used to that mirror image calculated result to be sent to data saving unit 40 when determining that two mirror image calculated results are equal,
Judging unit 30 is also used to generate and send failure breakpoint address to parsing mould when determining that two mirror image calculated results are unequal
Block 50；
Specifically, due to the structure of the first computing unit 21 and the second computing unit 22, function and the former data received
It is all the same, therefore, in the influence for being not affected by single-particle inversion, the calculating knot of the first computing unit 21 and the second computing unit 22
Fruit is identical, at this point, determining that two mirror image calculated results are equal by judging unit 30, the first computing unit 21 or second is calculated
The mirror image calculated result of unit 22 is sent to data saving unit 40 and is saved.
When the first computing unit 21 and/or the second computing unit 22 are influenced by single-particle inversion, first calculates list
Deviation will occur in member 21 and/or the mirror image calculated result of the second computing unit 22, and the mirror image of the two is determined by judging unit 30
Calculated result is not identical, obtains corresponding original according to the mirror image calculated result of the first computing unit 21 or the second computing unit 22
The data address of data, and failure breakpoint address is generated according to the data address obtained at this time, and failure breakpoint address is sent
It is stored to parsing module 50.
Preferably, when determining that two mirror image calculated results are equal, judging unit 30 is by the mirror image of the first computing unit 21
Calculated result is sent to data saving unit 40.
In the present embodiment, data saving unit 40 is connected to the first output end of judging unit 30, data saving unit
40 for generating storage address according to data address, and the mirror image calculated result of the first computing unit is stored according to storage address；
Further, data saving unit 40 is random access memory；
Specifically, data saving unit 40 is RAM, calculates knot when judging unit 30 sends mirror image to data saving unit 40
When fruit, data saving unit 40 is jumped according to the address for meeting progressive law, and the mirror image calculated result received is saved,
When exporting or searching related mirror image calculated result, it is only necessary to obtain corresponding address in RAM, mirror image calculating can be realized
As a result output or lookup, advantageously reduce the time delay during data search.
Further, fault correction device further include: data mask unit 60；It is single that data mask unit 60 is set to judgement
Between the first output end and data saving unit 40 of member 30, data mask unit 60 is used for when two mirror image calculated results of judgement
When unequal, low level enable signal is sent to data saving unit 40.
Specifically, setting data saving unit 40 is high level once-type RAM, when determining two mirror image calculated results not phase
Whens equal, data mask unit 60 sends low level enable signal to data saving unit 40, so that RAM is in corresponding storage address
Data can not be written in place, and realization shields mirror image calculated result at this time, ensure that in data saving unit 40 and save mirror
As the accuracy of calculated result.
In the present embodiment, the input terminal of parsing module 50 is connected to the second output terminal of judging unit 30, parsing module
50 output end is connected to the input terminal of data storage cell 10, and parsing module 50 is used to obtain data according to failure breakpoint address
Address, and data address is sent to data storage cell 10.
Further, parsing module 50 specifically includes: breakpoint storage unit 51 and address resolution unit 52；Breakpoint storage
Unit 51 is set to the input terminal of parsing module 50, and breakpoint storage unit 51 is used to generate breakpoint column according to failure breakpoint address
Table；
Specifically, breakpoint storage unit 51 is formed of registers, and each register can store a failure breakpoint
Address, and then form breakpoint list and transfer the failure breakpoint address in corresponding register in order to foundation breakpoint list.
Address resolution unit 52 is set to the output end of parsing module 50, and address resolution unit 52 is for parsing breakpoint column
Table, and data address is sent to data storage cell 10.
Further, address resolution unit 52 is random access memory.
Specifically, the address synchronization device that address resolution unit 52 is made of RAM, address resolution unit 52 in sequence,
Write-in and identical data address in data list, as shown in Figure 5, wherein AD is the data storage in address resolution unit 52
Address, D is the data that store in address resolution unit 52, is and data address identical in data list.Breakpoint storage is single
Breakpoint list in member 51 is equivalent to a pointer list, address resolution unit according to the failure breakpoint address in power-off list,
Corresponding data address is parsed, then data address is sent to data storage cell 10, so as to 10 basis of data storage cell
Data address sends corresponding former data to computing unit.
Embodiment two:
The fault correction method in the present embodiment is illustrated below with reference to Fig. 6 to Fig. 7.
As shown in fig. 6, the fault correction method that one of the present embodiment is calculated based on data flow driven, comprising:
Step S10 calculates former data by two identical computing units, respectively obtains the first calculating according to data address
As a result with the second calculated result；
Specifically, according to the computations received, corsspoint switch matrix control instruction is generated, control, which generates, meets calculating
The computing unit of instruction, and then realize the calculating to former data, obtain the first calculated result and the second calculated result.
Step S20, judges whether the first calculated result is equal to the second calculated result, when being determined as is, executes step
S30 executes step S40 when being determined as no；
Step S30 stores the first calculated result；
In step S30, specifically include:
Step S31 generates storage address according to the corresponding data address of the first calculated result；
Step S32 generates calculated result storage table according to storage address and the first calculated result.
Specifically, as shown in fig. 7, the default duration that calculates is to calculate duration by the unit of the durations such as N number of to form, at each
Unit calculates in duration, corresponding calculating data can be calculated according to former data, also, the number of address is by list in chip
What the serial number that position calculates duration determined, i.e. the storage that k-th of unit calculates the number, calculated result of the corresponding data address of duration
The number of address and the number of failure dot address are k.Since the number of the address in chip is incremented by according to timing,
After unit calculates duration, calculated result r1 (k) corresponding for former data s (k), the storage in calculated result storage table
The number k of the number k+1 data address more corresponding than former data of address is big by 1, i.e., when generating storage address, to former data
The address number of data address subtracts 1.
For example, calculating duration for second unit, corresponding data address is a (1), and corresponding original data are s
(1), corresponding first calculated result is r1 (1), and the second calculated result is r2 (1), and r1 (1) and r2 (1) are stored in third unit
It calculates in the corresponding storage address of duration.
Step S40 generates breakpoint list according to the corresponding data address of the first calculated result；
Specifically, the number of the failure dot address in breakpoint list is equally than the number of the data address of corresponding former data
It is big by 1.As shown in fig. 7, calculating duration in+1 unit of kth, determine that the first calculated result r1 (k) is not equal to the second calculated result r2
(k), it by the corresponding data address a (k) of the first calculated result r1 (k), is stored in+1 unit of kth in breakpoint list and calculates duration
In corresponding failure breakpoint address g (k+1).
Before the step 40, further includes: generate data mask instruction.
Specifically, as shown in fig. 7, k+1 unit corresponding to calculates duration, when determining the first calculated result r1 (k) not
When equal to the second calculated result r2 (k), data mask instruction is generated, the corresponding memory space of storage address b (k+1) is shielded
It covers, does not store corresponding data.
Step S50, according to breakpoint list, restoring data address executes step S10.
In step S50, specifically include:
Step S51 obtains the failure breakpoint address in breakpoint list；
Step S52 obtains the corresponding data address of failure breakpoint address according to failure breakpoint address；
Step S53 sends the corresponding former data of data address, executes step according to predetermined period according to data address
S10。
Specifically, as shown in fig. 7, after default calculating duration, duration is calculated in n-th unit, obtains breakpoint column
Failure breakpoint address g (k+1) in table, parses failure breakpoint address g (k+1), obtains corresponding data address a (k),
And then the corresponding original data s (k) of data address a (k) is sent to two identical computing units, it re-execute the steps 10.
In step S50, specifically further include:
Step S54, when the first calculated result for determining to recalculate is equal with the second calculated result recalculated, root
According to the corresponding data address of the first calculated result recalculated, insertion storage address is generated；
The first calculated result recalculated is inserted by step S55 according to insertion storage address and calculated result storage table
Calculated result storage table.
Specifically, as shown in fig. 7, at the N+1 moment, as the first calculated result r ' 1 (k) for determining to recalculate and again
When the second calculated result r ' 2 (k) calculated is equal, insertion storage address is generated, is corresponded to storage address b (k+1).Further according to life
At insertion storage address, the first calculated result r1 (k) recalculated is stored into position corresponding to storage address b (k+1),
At this point, the first calculated result r ' 1 (k) recalculated is the corresponding mirror image calculated result of former data s (k) after fault correction.
By the way that the technical solution in the application is compared test with existing two kinds of technical solutions, the comparison knot obtained
Fruit is as shown in table 1.
Table 1
Compared with existing triplication redundancy fault correction method, in the premise that ensure that accuracy rate and time loss ratio
Under, the application only needs 2 computing units can be completed, and reduces the resource consumption in chip, be conducive to reduce chip volume,
Reduce the cost of manufacture of chip.
Compared with existing conventional hardware duplication redundancy bearing calibration, guaranteeing that hardware resource consumption and accuracy rate are identical
Under the premise of, the application reduces the time loss in calculating process, improves the processing speed of chip, and it is single to advantageously reduce generation
Particle overturns the probability of failure, reduces the outage probability of data flow driven calculating.
Step in the application can be sequentially adjusted, combined, and deleted according to actual needs.
Unit in the application device can be combined, divided and deleted according to actual needs.
Although disclosing the application in detail with reference to attached drawing, it will be appreciated that, these descriptions are only exemplary, not
For limiting the application of the application.The protection scope of the application may include not departing from this Shen by appended claims
It please be in the case where protection scope and spirit for various modifications, remodeling and equivalent scheme made by inventing.
Claims (8)
1. a kind of fault correction device calculated based on data flow driven, which is characterized in that the fault correction device includes: number
According to storage unit (10), two computing units, judging unit (30), data saving unit (40) and parsing module (50)；
The data storage cell (10) is set to the input terminal of the fault correction device, and the data storage cell (10) is used
In sending corresponding former data simultaneously according to data address to two computing units；
The input terminal of two computing units is connected to the output end of the data storage cell (10), and the calculating is single
Member is for carrying out mirror image calculating to the former data；
Two input terminals of the judging unit (30) are connected to the output end of two computing units, and the judgement is single
First (30) are used to that the mirror image calculated result to be sent to the data and is protected when determining that two mirror image calculated results are equal
Memory cell (40), the judging unit (30) are also used to when determining that two mirror image calculated results are unequal, generate concurrent
Send failure breakpoint address to parsing module (50)；
The data saving unit (40) is connected to the first output end of the judging unit (30), the data saving unit
(40) for generating storage address according to the data address, and first computing unit is stored according to the storage address
The mirror image calculated result；
The input terminal of the parsing module (50) is connected to the second output terminal of the judging unit (30), the parsing module
(50) output end is connected to the input terminal of the data storage cell (10), and the parsing module (50) is used for according to the event
Hinder breakpoint address and obtain the data address, and sends the data address to the data storage cell (10).
2. the fault correction device calculated as described in claim 1 based on data flow driven, which is characterized in that the parsing mould
Block (50) specifically includes: breakpoint storage unit (51) and address resolution unit (52)；
The breakpoint storage unit (51) is set to the input terminal of the parsing module (50), and the breakpoint storage unit (51) is used
According to failure breakpoint address generation breakpoint list；
The address resolution unit (52) is set to the output end of the parsing module (50), and the address resolution unit (52) is used
In the parsing breakpoint list, and the data address is sent to the data storage cell (10).
3. the fault correction device calculated as described in claim 1 based on data flow driven, which is characterized in that further include: number
According to screen unit (60)；
The data mask unit (60) is set to first output end of the judging unit (30) and the data save
Between unit (40), the data mask unit (60) is used for when determining that two mirror image calculated results are unequal, to institute
It states data saving unit (40) and sends low level enable signal.
4. the fault correction device calculated as described in claim 1 based on data flow driven, which is characterized in that the calculating is single
Member is butterfly computation device, and the butterfly computation device includes: first choice switch unit, two 2 butterfly computation devices of base, the first plural number
Adder and the second complex adder.
5. a kind of fault correction method calculated based on data flow driven, which is characterized in that the fault correction method includes:
Step S10 calculates former data by two identical computing units, respectively obtains the first calculated result according to data address
With the second calculated result；
Step S20, judges whether first calculated result is equal to second calculated result and executes step when being determined as is
Rapid S30 executes step S40 when being determined as no；
Step S30 stores first calculated result；
Step S40 generates breakpoint list according to the corresponding data address of first calculated result；
Step S50 restores the data address according to the breakpoint list, executes the step S10.
6. the fault correction device calculated as claimed in claim 5 based on data flow driven, which is characterized in that the step
S30 is specifically included:
Step S31 generates storage address according to the corresponding data address of first calculated result；
Step S32 generates calculated result storage table according to the storage address and first calculated result.
7. the fault correction method calculated as claimed in claim 6 based on data flow driven, which is characterized in that the step
S50 is specifically included:
Step S51 obtains the failure breakpoint address in the breakpoint list；
Step S52 obtains the corresponding data address according to the failure breakpoint address；
Step S53 sends the corresponding former data of the data address, holds according to predetermined period according to the data address
The row step S10.
8. the fault correction method calculated as claimed in claim 7 based on data flow driven, which is characterized in that the step
S50 is specific further include:
Step S54, when first calculated result for determining to recalculate is equal with second calculated result recalculated
When, according to the corresponding data address of first calculated result recalculated, generate insertion storage address；
Step S55 is calculated according to the insertion storage address and the calculated result storage table by recalculate described first
As a result it is inserted into the calculated result storage table.
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