CN109144230B - Control method, terminal and the virtual digit coin of series-fed circuit dig mine machine - Google Patents
Control method, terminal and the virtual digit coin of series-fed circuit dig mine machine Download PDFInfo
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- CN109144230B CN109144230B CN201810868052.9A CN201810868052A CN109144230B CN 109144230 B CN109144230 B CN 109144230B CN 201810868052 A CN201810868052 A CN 201810868052A CN 109144230 B CN109144230 B CN 109144230B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
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Abstract
The invention discloses a kind of series-fed circuits, comprising steps of the internal register of each chip to be powered opens m preset arithmetic element groups according to preset delay value in batches when series-fed power on circuitry；Wherein, there is n arithmetic element, and n arithmetic element is divided into m preset arithmetic element groups in each chip to be powered, m, n are the integer greater than 1；Micro-control unit sends pulse signal to chipset to be powered in batches according to preset interval time, within the same time, each chip to be powered is after receiving pulse signal, the arithmetic element starting operation for i-th of preset arithmetic element group having turned in m preset arithmetic element groups；Wherein, 1≤i≤m, and pulse signal and m preset arithmetic element groups are one-to-one relationship.The present invention can be realized the balance of voltage of every chips, the voltage stability between series-fed circuit chip be improved, to improve the job stability of whole system.
Description
Technical field
The present invention relates to power supply power supply technical fields, more particularly, to control method, the terminal of a kind of series-fed circuit
And virtual digit coin digs mine machine.
Background technique
Currently, digging in mine machine product in virtual digit currency, the energy consumption ratio for digging mine machine is very crucial index；Due to digging
Mine machine is integrated with several hundred chips, and the energy consumption for digging mine machine is mainly derived from the energy consumption of these chips, therefore reduces chip operation electricity
Pressure is very effective one of the means for reducing chip power-consumption.
In the prior art, it in order to improve the production cost for digging the calculation power of mine machine and reducing digging mine machine, is imitated since DC/DC exists
The low problem of rate, itself causes the waste of power supply energy, while designing complexity, high production cost, therefore the scheme of mainstream at present
The parallel connection type circuit of DC/DC (DC to DC) chip is all no longer used to power for every chips.With chip operating voltage
Reduce, the chip for digging mine machine has used series-fed scheme, i.e., the power supply of chip and join end to end to form the electricity of plural serial stage
Domain is pressed, each voltage domain possesses one or several chips, each voltage domain mean allocation supply voltage.
However, the operating voltage due to chip is very low, lesser voltage fluctuation will make chip operation unstable, and
The voltage of each chip is by the voltage of all same power supplys of chip mean allocation come when chip is in different work
When state, internal resistance value is different, and especially in the conversion process from off-position to normal operating conditions, the resistance value of chip becomes
Change larger, therefore, it is difficult to guarantee the balance of voltage of every chips, leads to the voltage stability shadow between series-fed circuit chip
Ring the job stability for arriving whole system.
Summary of the invention
The embodiment of the invention provides a kind of control method of series-fed circuit, terminal and virtual digit coin to dig mine machine,
To solve the technical issues of existing series-fed circuit is difficult to ensure the balance of voltage of every chips, to realize every chips
The balance of voltage, improve series-fed circuit chip between voltage stability, and then improve whole system job stability.
In order to solve the above-mentioned technical problem, the embodiment of the invention provides a kind of control method of series-fed circuit, institutes
Stating series-fed circuit includes micro-control unit and the core to be powered for being connected in series in progress series-fed between feeder ear and ground
Piece group, the chipset to be powered include the voltage domain that multiple chips to be powered being sequentially connected in series form plural serial stage；Position
It is connect by control signal wire with the micro-control unit in the chip to be powered of the chipset head end to be powered, it is multiple described
Two adjacent chips to be powered are connected by control signal wire in chip to be powered；
The described method includes:
When the series-fed power on circuitry, the internal register of each chip to be powered is according to preset delay
Value opens m preset arithmetic element groups in batches；Wherein, the register of the configuration is for controlling the chip to be powered
The on/off of internal arithmetic element, each chip to be powered is interior to have n arithmetic element, and n arithmetic element is drawn
It is divided into m preset arithmetic element groups, m, n are the integer greater than 1；
The micro-control unit sends pulse signal to the chipset to be powered in batches according to preset interval time,
Within the same time, each chip to be powered is after receiving the pulse signal, the m preset arithmetic element groups
In have turned on i-th of preset arithmetic element group arithmetic element starting operation；Wherein, 1≤i≤m, and the pulse signal
It is one-to-one relationship with the m preset arithmetic element groups.
Preferably, positioned at the chip ground to be powered of the chipset head end to be powered, and the microcontroller list
First and the head end chip to be powered is altogether.
Preferably, when the series-fed power on circuitry, the inside of each chip to be powered is deposited
After device opens i-th of preset arithmetic element group according to preset delay value,
It is sent to the chipset to be powered with described i-th in advance in the micro-control unit according to preset interval time
If the corresponding pulse signal of arithmetic element group before,
The method also includes:
The arithmetic element of i-th of preset arithmetic element group is not turned on operation.
Preferably, when i is equal to 1, which comprises
When the series-fed power on circuitry, the internal register of each chip to be powered is according to preset delay
Value opens the 1st preset arithmetic element group；
The micro-control unit sends to the chipset to be powered according to preset interval time and presets with described 1st
The corresponding pulse signal of arithmetic element group；
Within the same time, each chip to be powered is after receiving the pulse signal, the m preset fortune
Calculate the arithmetic element starting operation for the 1st preset arithmetic element group having turned in unit group.
Preferably, when the series-fed power on circuitry, the inside of each chip to be powered is deposited
After device opens the 1st preset arithmetic element group according to preset delay value,
It is sent to the chipset to be powered with described 1st in advance in the micro-control unit according to preset interval time
If the corresponding pulse signal of arithmetic element group before,
The method also includes:
The arithmetic element of the 1st preset arithmetic element group is not turned on operation.
Preferably, when i is equal to 2, which comprises
After the arithmetic element of the 2nd preset arithmetic element group starts operation, each chip to be powered
Internal register the 2nd preset arithmetic element group is opened according to preset delay value；
The micro-control unit sends to the chipset to be powered according to preset interval time and presets with described 2nd
The corresponding pulse signal of arithmetic element group；
Within the same time, each chip to be powered is after receiving the pulse signal, the m preset fortune
Calculate the arithmetic element starting operation for the 2nd preset arithmetic element group having turned in unit group.
Preferably, when the 2nd preset arithmetic element group arithmetic element start operation after, it is each
After the internal register of the chip to be powered opens the 2nd preset arithmetic element group according to preset delay value,
The micro-control unit sends to the chipset to be powered according to preset interval time and presets with described 2nd
The corresponding pulse signal of arithmetic element group before,
The method also includes:
The arithmetic element of the 2nd preset arithmetic element group is not turned on operation.
In order to solve identical technical problem, the embodiment of the invention also provides a kind of control of series-fed circuit ends
End including processor, memory and stores in the memory and is configured as the computer executed by the processor
Program, the processor realize the control method such as above-mentioned series-fed circuit when executing the computer program.
In order to solve identical technical problem, the embodiment of the invention also provides a kind of virtual digit coin to dig mine machine, including
Cabinet, the control panel positioned at cabinet inside, the expansion board that is connect with the control panel and the operation board being connect with expansion board, institute
State the control method that operation board executes above-mentioned series-fed circuit.
In order to solve identical technical problem, the embodiment of the invention also provides a kind of computer readable storage medium, institutes
State the computer program that computer readable storage medium includes storage, wherein in computer program operation described in control
Equipment executes the control method such as above-mentioned series-fed circuit where computer readable storage medium.
Compared with the prior art, the embodiment of the present invention has the following beneficial effects:
In the present embodiment, every chips are uniformly controlled in order to realize, on the basis of the series-fed circuit
The control signal wire is added, the control signal wire is coupled to from the micro-control unit grade positioned at described by concatenated mode
The chip to be powered of chip group end to be powered；Wherein, the chip to be powered of the end is connect with the feeder ear；To logical
It crosses the arithmetic element that the micro-control unit transmission pulse signal controls in each chip to be powered and starts operation in batches.
Wherein, clock signal controls delay in such a way that internal register plays bat, and internal deposit described in the delay value
Device can match, to control the starting time of chip internal circuits by the signal after delay.By adjusting the series-fed
The delay value of each chip to be powered on circuit can allow the internal circuit of each chip to be powered to start the time difference
It is different to be accurate in 1~2 clock cycle (ns grades of delays).The synchronism that can guarantee every chips movement in this way, to protect
Demonstrate,prove the internal resistance consistency between chip.
Be further, since the particularity of mine machine core piece, in each chip to be powered by it is multiple (tens to several hundred not
Deng) the same computing unit composition, therefore, the open and close of each arithmetic element are controlled by register.It is being
System initial start stage first starts a small amount of arithmetic element, and control whole system electric current will not rise too fast, and is then stepped up fortune
The starting quantity of unit is calculated, until all arithmetic elements all start；It, can be opposite in conjunction with the starting time control of control signal
It is accurately controlled the job stability of whole system.
In this way, the embodiment of the present invention provides the control method of the series-fed circuit by controlling the series-fed electricity
The Booting sequence of each chip to be powered and starting timing on the road, so that the work step of each chip to be powered is protected
It holds unanimously, to maintain the internal resistance consistency of chip at any time, realizes the balance of voltage of every chips, improve series-fed
Voltage stability between circuit chip, and then effectively improve the job stability of whole system.
Detailed description of the invention
Fig. 1 is the flow chart of the control method of the series-fed circuit of the embodiment of the present invention one；
Fig. 2 is the structural schematic diagram of the series-fed circuit of the embodiment of the present invention one；
Fig. 3 is the flow chart of the control method of the series-fed circuit of the embodiment of the present invention two；
Fig. 4 is the structural schematic diagram of the series-fed circuit of the embodiment of the present invention two；
Fig. 5 is the chip internal control signal to be powered transmission of the embodiment of the present invention one and uses design structure diagram；
Wherein, the appended drawing reference in Figure of description is as follows:
1, feeder ear；2, micro-control unit；3, the chip to be powered of head end；4, the chip to be powered of end；5, control letter
Number line.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Referring to Figure 1 and Fig. 2, the preferred embodiment of the present invention provides a kind of control method of series-fed circuit, described
Series-fed circuit includes micro-control unit 2 and the core to be powered for being connected in series in progress series-fed between feeder ear 1 and ground
Piece group, the chipset to be powered include the voltage domain that multiple chips to be powered being sequentially connected in series form plural serial stage；Position
It is connect by control signal wire 5 with the micro-control unit 2 in the chip to be powered 3 of the chipset head end to be powered, it is multiple
Two adjacent chips to be powered are connected by control signal wire 5 in the chip to be powered；
The described method includes:
S1, when the series-fed power on circuitry, the internal register of each chip to be powered is according to preset
Delay value opens m preset arithmetic element groups in batches；Wherein, the internal register of configuration is described to be powered for controlling
The on/off of the arithmetic element of chip interior, each chip to be powered is interior to have n arithmetic element, and n operation list
Member is divided into m preset arithmetic element groups, and m, n are the integer greater than 1；
S2, the micro-control unit 2 send pulse to the chipset to be powered in batches according to preset interval time
Signal, within the same time, each chip to be powered is after receiving the pulse signal, the m preset operations
The arithmetic element of the preset arithmetic element group of i-th had turned in unit group starts operation；Wherein, 1≤i≤m, and the arteries and veins
Rushing signal and the m preset arithmetic element groups is one-to-one relationship.
In embodiments of the present invention, each chip to be powered is uniformly controlled in order to realize, is supplied in the series connection
Add the control signal wire 5 on the basis of circuit, the control signal wire 5 is by concatenated mode from the microcontroller list
2 grades of member is coupled to the chip to be powered 4 positioned at the chip group end to be powered；Wherein, the chip to be powered 4 of the end and institute
State the connection of feeder ear 1；The fortune in each chip to be powered is controlled to send pulse signal by the micro-control unit 2
It calculates unit and starts operation in batches.
Wherein, clock signal controls delay in such a way that internal register plays bat, and internal deposit described in the delay value
Device can match, to control the starting time of chip internal circuits by the signal after delay.By adjusting the series-fed
The delay value of each chip to be powered on circuit can allow the internal circuit of each chip to be powered to start the time difference
It is different to be accurate in 1~2 clock cycle (ns grades of delays).It can guarantee the synchronization of each chip activity to be powered in this way
Property, to guarantee the internal resistance consistency between chip.
Be further, since the particularity of mine machine core piece, in each chip to be powered by it is multiple (tens to several hundred not
Deng) the same arithmetic element composition, therefore, the open and close of each arithmetic element are controlled by register.It is being
System initial start stage first starts a small amount of arithmetic element, and control whole system electric current will not rise too fast, and is then stepped up fortune
The starting quantity of unit is calculated, until all arithmetic elements all start；It, can be opposite in conjunction with the starting time control of control signal
It is accurately controlled the job stability of whole system.
In this way, the embodiment of the present invention provides the control method of the series-fed circuit by controlling the series-fed electricity
The Booting sequence of each chip to be powered and starting timing on the road, so that the work step of each chip to be powered is protected
It holds unanimously, to maintain the internal resistance consistency of chip at any time, realizes the balance of voltage of every chips, improve series-fed
Voltage stability between circuit chip, and then effectively improve the job stability of whole system.
Fig. 2 is referred to, in embodiments of the present invention, the chip to be powered 3 positioned at the chipset head end to be powered is grounded,
And the chip to be powered 3 of the micro-control unit 2 and the head end is altogether.
In embodiments of the present invention, the technical principle of the control method of the series-fed circuit is as follows:
According to Ohm's law U=I*R, in the series-fed circuit of chip cascade, each chip to be powered
Electric current it is equal, then the operating voltage of each chip to be powered depends on itself internal resistance value, therefore control chip work
The key for making voltage is to control the internal resistance of chip.
It is each described only when the internal resistance value of all chips on the series-fed circuit is all consistent as far as possible
The operating voltage of chip to be powered is likely to be consistent.In the case where electric current is smaller, the influence of resistance value is bigger, wherein
In the case where electric current is bigger, the influence of resistance value is smaller.
The internal resistance value of the chip to be powered is again related with the working condition of chip itself, specifically:
In the power-off state, all logic gates of the chip interior to be powered are in close state, described wait supply
Electrical chip shows a biggish internal resistance value.
After the chip to be powered powers on, logic gates gradually opens conducting, and logic gates is in the on-state
Resistance value is extremely low, and with the continuous unlatching of logic gates, the resistance value of chip also constantly declines.
The chip internal resistance value decline to be powered, corresponding electric current increase.
When all logic gates of the chip to be powered are all in working condition, operating current peaks value, interior
Resistance value also reaches minimum, and at this time the subtle fluctuation of the chip interior to be powered is to the influence of voltage very little,
Whole system enters an opposite steady-working state.
How to allow chip from off-position to normal operating conditions during have one smoothly be excessively system enter
The key point of steady-working state.Therefore, the present invention is started and all chip synchronizations in batches by controlling chip interior logic
The scheme of movement allows the operating current of system slowly to increase from low to high, while when the state change of all chips of strict control
Between, allow all chips to act in the same time, as far as possible to ensure the smooth starting of system.
Further, in embodiments of the present invention, when the series-fed power on circuitry, each core to be powered
After the internal register of piece opens i-th of preset arithmetic element group according to preset delay value,
It is sent and described i-th according to preset interval time to the chipset to be powered in the micro-control unit 2
Before the corresponding pulse signal of preset arithmetic element group,
The method also includes:
The arithmetic element of i-th of preset arithmetic element group is not turned on operation.
Fig. 3 and Fig. 4 are referred to, the following content is the control methods to the above-mentioned series-fed circuit specifically
It is bright:
In embodiments of the present invention, when i is equal to 1, which comprises
When the series-fed power on circuitry, the internal register of each chip to be powered is according to preset delay
Value opens the 1st preset arithmetic element group；
The micro-control unit 2 is sent with described 1st in advance according to preset interval time to the chipset to be powered
If the corresponding pulse signal of arithmetic element group；
Within the same time, each chip to be powered is after receiving the pulse signal, the m preset fortune
Calculate the arithmetic element starting operation for the 1st preset arithmetic element group having turned in unit group.
In embodiments of the present invention, when the series-fed power on circuitry, the inside of each chip to be powered
After register root opens the 1st preset arithmetic element group according to preset delay value,
It is sent and described 1st according to preset interval time to the chipset to be powered in the micro-control unit 2
Before the corresponding pulse signal of preset arithmetic element group,
The method also includes:
The arithmetic element of the 1st preset arithmetic element group is not turned on operation.
In embodiments of the present invention, when i is equal to 2, which comprises
After the arithmetic element of the 2nd preset arithmetic element group starts operation, each chip to be powered
Internal register the 2nd preset arithmetic element group is opened according to preset delay value；
The micro-control unit 2 is sent with described 2nd in advance according to preset interval time to the chipset to be powered
If the corresponding pulse signal of arithmetic element group；
Within the same time, each chip to be powered is after receiving the pulse signal, the m preset fortune
Calculate the arithmetic element starting operation for the 2nd preset arithmetic element group having turned in unit group.
In the present embodiment, it should be noted that need to repeat above step, until in each circuit to be powered
All arithmetic elements all start in all chips to be powered, so that the arithmetic element in each chip to be powered is opened
In the process, a relatively stable starting state is kept, and then improves the voltage stability between series-fed circuit chip, and
Improve the job stability of whole system.
In embodiments of the present invention, when the 2nd preset arithmetic element group arithmetic element start operation after,
2nd preset arithmetic element group is opened it according to preset delay value by the internal register of each chip to be powered
Afterwards,
The micro-control unit 2 is sent with described 2nd in advance according to preset interval time to the chipset to be powered
If the corresponding pulse signal of arithmetic element group before,
The method also includes:
The arithmetic element of the 2nd preset arithmetic element group is not turned on operation.
Illustratively, continuing with referring to Fig. 3 and Fig. 4, it is assumed that the power supply of the feeder ear 1 is 12v, the chip to be powered
The number of chips n to be powered of group is 30, and the voltage of each chip to be powered is same by all chip mean allocations
The voltage of the feeder ear 1, according to Ohm's law U=I*R, series-fed circuit I is equal, so each chip is got
Voltage and itself internal resistance it is proportional.
Specifically, being uniformly controlled to realize to each chip to be powered, need to increase a control signal wire
5, the control signal wire 5 is cascaded to the chip to be powered 4 of end also by concatenated mode from micro-control unit 2.The signal
It is controlled by micro-control unit 2.
Step1, system cut-off, each chip to be powered are in close state, and all arithmetic element defaults are closed；
Step2, system electrification, the internal register of each chip to be powered open a collection of arithmetic element, but at this time
Arithmetic element do not start operation；
Step3, MCU send cpen pulse, after each chip to be powered all receives cpen control signal, same
Time starts first arithmetic element, and system power is smaller at this time；
The internal register unlatching next group arithmetic element of Step4, the chip to be powered, but arithmetic element at this time is not
Start operation；
Step5, MCU send cpen pulse, after each chip to be powered all receives cpen control signal, same
Time starts next group arithmetic element, and system power incrementally increases at this time；
Step6, step4~step5 is repeated, until all arithmetic elements all start, in this process, system can be protected
Hold a relatively stable starting state.
The cpeni of the chip to be powered 3 (chip1) of the head end is connected with micro-control unit 2 (MCU), receives from micro-control
The cpen signal that unit 2 processed issues, while the signal is directly output to second chip to be powered from pin cpeno
(chip2), and so on, until the chip to be powered 4 of end；In the inside of the chip to be powered, control signal cpen's
Transmission and using design structure diagram as shown in figure 5,
Wherein, cpen signal controls delay in such a way that internal register plays bat, and the delay value register can match, and leads to
Signal after crossing delay controls starting time of chip internal circuits.
By adjusting the delay value of the chip to be powered each on link in tandem, each chip to be powered can be allowed
Internal circuit starting time difference be accurate in 1~2 clock cycle (ns grade of delays), can guarantee in this way it is each described in
The synchronism of chip activity to be powered, to ensure that the internal resistance consistency between the chip to be powered；
Be further, since the particularity of mine machine core piece, in each chip to be powered by it is multiple (tens to several hundred not
Deng) the same arithmetic element composition.Therefore, the open and close of each arithmetic element are controlled by register.It is being
System initial start stage first starts a small amount of arithmetic element, and control whole system electric current will not rise too fast, and is then stepped up fortune
The starting quantity of unit is calculated, until all arithmetic elements all start.It, can be in conjunction with the starting time control of control signal cpen
The opposite job stability for being accurately controlled whole system.
In order to solve identical technical problem, the embodiment of the invention also provides a kind of control of series-fed circuit ends
End including processor, memory and stores in the memory and is configured as the computer executed by the processor
Program, the processor realize the control method of above-mentioned series-fed circuit when executing the computer program.
Illustratively, the computer program can be divided into one or more module/units, one or more
A module/unit is stored in the memory, and is executed by the processor, to complete the present invention.It is one or more
A module/unit can be the series of computation machine program instruction section that can complete specific function, and the instruction segment is for describing institute
State implementation procedure of the computer program in the controlling terminal of the series-fed circuit.
The controlling terminal of the series-fed circuit can be desktop PC, notebook, palm PC and cloud clothes
Business device etc. calculates equipment.The controlling terminal of the series-fed circuit may include, but be not limited only to, processor, memory.Ability
Field technique personnel are appreciated that above-mentioned component is only the example of the access-in management terminal device of USB interface, composition pair
The restriction of the access-in management terminal device of USB interface may include than above-mentioned more or fewer components, or the certain portions of combination
Part or different components, such as the controlling terminal of the series-fed circuit can also connect including input-output equipment, network
Enter equipment, bus etc..
Alleged processor can be central processing unit (Central Processing Unit, CPU), can also be it
His general processor, digital signal processor (Digital Signal Processor, DSP), specific integrated circuit
(Application Specific Integrated Circuit, ASIC), ready-made programmable gate array (Field-
Programmable Gate Array, FPGA) either other programmable logic device, discrete gate or transistor logic,
Discrete hardware components etc..General processor can be microprocessor or the processor is also possible to any conventional processor
Deng the processor is the control centre of the controlling terminal of the series-fed circuit, whole using various interfaces and connection
The various pieces of the access-in management terminal device of a USB interface.
The memory can be used for storing the computer program and/or module, and the processor is by operation or executes
Computer program in the memory and/or module are stored, and calls the data being stored in memory, described in realization
The various functions of the controlling terminal of series-fed circuit.The memory can mainly include storing program area and storage data area,
Wherein, storing program area can application program needed for storage program area, at least one function (such as sound-playing function, figure
As playing function etc.) etc.；Storage data area can store according to terminal device use created data (such as audio data,
Phone directory etc.) etc..In addition, memory may include high-speed random access memory, it can also include nonvolatile memory, example
Such as hard disk, memory, plug-in type hard disk, intelligent memory card (Smart Media Card, SMC), secure digital (Secure
Digital, SD) card, flash card (Flash Card), at least one disk memory, flush memory device or other volatibility are solid
State memory device.
Wherein, if the integrated module/unit of the controlling terminal of the series-fed circuit is with the shape of SFU software functional unit
Formula realize and when sold or used as an independent product, can store in a computer readable storage medium.It is based on
Such understanding, the present invention realize above-described embodiment method in all or part of the process, can also by computer program come
Relevant hardware is instructed to complete, the computer program can be stored in a computer readable storage medium, the computer
Program is when being executed by processor, it can be achieved that the step of above-mentioned each embodiment of the method.Wherein, the computer program includes meter
Calculation machine program code, the computer program code can be source code form, object identification code form, executable file or certain
Intermediate form etc..The computer-readable medium may include: can carry the computer program code any entity or
Device, recording medium, USB flash disk, mobile hard disk, magnetic disk, CD, computer storage, read-only memory (ROM, Read-Only
Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software
Distribution medium etc..It should be noted that the content that the computer-readable medium includes can be according to making laws in jurisdiction
Requirement with patent practice carries out increase and decrease appropriate, such as in certain jurisdictions, according to legislation and patent practice, computer
Readable medium does not include electric carrier signal and telecommunication signal.
In order to solve identical technical problem, the embodiment of the invention also provides a kind of virtual digit coin to dig mine machine, including
Cabinet, the control panel positioned at cabinet inside, the expansion board that is connect with the control panel and the operation board being connect with expansion board, institute
State the control method that operation board executes above-mentioned series-fed circuit.
In the present embodiment, the control panel that the virtual digit coin is dug in mine machine is in the entire control for digging mine machine
The heart, the control panel send instruction and data by I/O expansion plate, and it is entire that operation board is powered using the series-fed circuit
Dig the arithmetic center of mine machine.
Instruction and data is issued to I/O expansion plate by the control panel, and instruction and data is forwarded to operation by I/O expansion plate
Result is returned to control panel by I/O expansion plate after operation board operation by plate, and control panel is uploaded to mutually by wired network interface
In networking.
In order to solve identical technical problem, the embodiment of the invention also provides a kind of computer readable storage medium, institutes
State the computer program that computer readable storage medium includes storage, wherein in computer program operation described in control
Equipment executes the control method such as above-mentioned series-fed circuit where computer readable storage medium.
To sum up, the embodiment of the invention provides a kind of control methods of series-fed circuit, which is characterized in that the series connection
Power supply circuit include micro-control unit 2 and be connected in series between feeder ear 1 and ground carry out series-fed chipset to be powered,
The chipset to be powered includes the voltage domain that multiple chips to be powered being sequentially connected in series form plural serial stage；Positioned at described
The chip to be powered 3 of chipset head end to be powered is connect by control signal wire 5 with the micro-control unit 2, it is multiple described in
Two adjacent chips to be powered are connected by control signal wire 5 in power supply chip；
The described method includes:
When the series-fed power on circuitry, the internal register of each chip to be powered is according to preset delay
Value opens m preset arithmetic element groups in batches；Wherein, the register of the configuration is for controlling the chip to be powered
The on/off of internal arithmetic element, each chip to be powered is interior to have n arithmetic element, and n arithmetic element is drawn
It is divided into m preset arithmetic element groups, m, n are the integer greater than 1；
The micro-control unit 2 sends pulse letter to the chipset to be powered in batches according to preset interval time
Number, within the same time, each chip to be powered is after receiving the pulse signal, the m preset operation lists
The arithmetic element of the preset arithmetic element group of i-th had turned in tuple starts operation；Wherein, and the pulse signal with
The m preset arithmetic element groups are one-to-one relationship.
Compared with the prior art, the embodiment of the present invention has the following beneficial effects:
(1) in the present embodiment, every chips are uniformly controlled in order to realize, on the basis of the series-fed circuit
On add the control signal wire 5, the control signal wire 5 is coupled to position for 2 grades from the micro-control unit by concatenated mode
In the chip to be powered 4 of the chip group end to be powered；Wherein, the chip to be powered 4 of the end and the feeder ear 1 connect
It connects；The arithmetic element in each chip to be powered is controlled in batches to send pulse signal by the micro-control unit 2
Secondary starting operation.
(2) clock signal controls delay, and internal register described in the delay value in such a way that internal register plays bat
It can match, to control the starting time of chip internal circuits by the signal after delay.By adjusting the series-fed electricity
The delay value of each chip to be powered on the road can allow the internal circuit of each chip to be powered to start time difference
(ns grades of delays) were accurate in 1~2 clock cycle.The synchronism that can guarantee every chips movement in this way, to guarantee
Internal resistance consistency between chip.
(3) be due to the particularity of mine machine core piece, in each chip to be powered by it is multiple (tens to several hundred not
Deng) the same computing unit composition, therefore, the open and close of each arithmetic element are controlled by register.It is being
System initial start stage first starts a small amount of arithmetic element, and control whole system electric current will not rise too fast, and is then stepped up fortune
The starting quantity of unit is calculated, until all arithmetic elements all start；It, can be opposite in conjunction with the starting time control of control signal
It is accurately controlled the job stability of whole system.
(4) embodiment of the present invention provides the control method of the series-fed circuit by controlling the series-fed circuit
The Booting sequence and starting timing of upper each chip to be powered, so that the work step of each chip to be powered is kept
Unanimously, it to maintain the internal resistance consistency of chip at any time, realizes the balance of voltage of every chips, improves series-fed electricity
Voltage stability between the chip of road, and then effectively improve the job stability of whole system.
(5) control method that the embodiment of the present invention provides the series-fed circuit improves the series-fed circuit
Voltage stability simplifies the single board design difficulty of the series-fed circuit, and simplifies one-board power supply Managed Solution, to drop
The low debugging difficulty of veneer, and reduce the development cost and production cost of veneer.
It should be noted that the apparatus embodiments described above are merely exemplary, wherein described be used as separation unit
The unit of explanation may or may not be physically separated, and component shown as a unit can be or can also be with
It is not physical unit, it can it is in one place, or may be distributed over multiple network units.It can be according to actual
It needs that some or all of the modules therein is selected to achieve the purpose of the solution of this embodiment.In addition, device provided by the invention
In embodiment attached drawing, the connection relationship between module indicate between them have communication connection, specifically can be implemented as one or
A plurality of communication bus or signal wire.Those of ordinary skill in the art are without creative efforts, it can understand
And implement.
The above is a preferred embodiment of the present invention, it is noted that for those skilled in the art
For, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also considered as
Protection scope of the present invention.
Claims (9)
1. a kind of control method of series-fed circuit, which is characterized in that the series-fed circuit include micro-control unit and
Be connected in series between feeder ear and ground carry out series-fed chipset to be powered, the chipset to be powered include it is multiple according to
The chip to be powered of secondary series connection forms the voltage domain of plural serial stage；Positioned at the core to be powered of the chipset head end to be powered
Piece is connect by control signal wire with the micro-control unit, two adjacent chips to be powered in multiple chips to be powered
It is connected by control signal wire；
The described method includes:
When the series-fed power on circuitry, the internal register of each chip to be powered will according to preset delay value
M preset arithmetic element groups are opened in batches, guarantee the synchronism of each chip activity to be powered and described to be powered
Internal resistance consistency between chip；Wherein, the internal register of configuration is used to control the operation list of the chip interior to be powered
The on/off of member, has n arithmetic element in each chip to be powered, and to be divided into m a preset for n arithmetic element
Arithmetic element group, m, n are the integer greater than 1；
The micro-control unit sends pulse signal to the chipset to be powered in batches according to preset interval time, same
In one time, each chip to be powered is after receiving the pulse signal, in the m preset arithmetic element groups
The arithmetic element for i-th of the preset arithmetic element group opened starts operation；Wherein, 1≤i≤m, and the pulse signal and institute
Stating m preset arithmetic element groups is one-to-one relationship.
2. the control method of series-fed circuit as described in claim 1, which is characterized in that be located at the chipset to be powered
The chip ground to be powered of head end, and the chip to be powered of the micro-control unit and the head end is altogether.
3. the control method of series-fed circuit as claimed in claim 1 or 2, which is characterized in that
When the series-fed power on circuitry, the internal register of each chip to be powered is according to preset delay value
After i-th of preset arithmetic element group is opened,
It is preset to the chipset transmission to be powered and described i-th according to preset interval time in the micro-control unit
Before the corresponding pulse signal of arithmetic element group,
The method also includes:
The arithmetic element of i-th of preset arithmetic element group is not turned on operation.
4. the control method of series-fed circuit as claimed in claim 3, which is characterized in that when i is equal to 1, the method
Include:
When the series-fed power on circuitry, the internal register of each chip to be powered will according to preset delay value
1st preset arithmetic element group is opened；
The micro-control unit is sent and the 1st preset fortune according to preset interval time to the chipset to be powered
Calculate the corresponding pulse signal of unit group；
Within the same time, each chip to be powered is after receiving the pulse signal, the m preset operation lists
The arithmetic element for the 1st preset arithmetic element group having turned in tuple starts operation.
5. the control method of series-fed circuit as claimed in claim 4, which is characterized in that
When the series-fed power on circuitry, the internal register of each chip to be powered is according to preset delay value
After 1st preset arithmetic element group is opened,
It is preset to the chipset transmission to be powered and described 1st according to preset interval time in the micro-control unit
Before the corresponding pulse signal of arithmetic element group,
The method also includes:
The arithmetic element of the 1st preset arithmetic element group is not turned on operation.
6. the control method of series-fed circuit as claimed in claim 3, which is characterized in that when i is equal to 2, the method
Include:
When the series-fed power on circuitry, the internal register of each chip to be powered will according to preset delay value
2nd preset arithmetic element group is opened；
The micro-control unit is sent and the 2nd preset fortune according to preset interval time to the chipset to be powered
Calculate the corresponding pulse signal of unit group；
Within the same time, each chip to be powered is after receiving the pulse signal, the m preset operation lists
The arithmetic element for the 2nd preset arithmetic element group having turned in tuple starts operation.
7. the control method of series-fed circuit as claimed in claim 6, which is characterized in that
When the series-fed power on circuitry, the internal register of each chip to be powered is according to preset delay value
After 2nd preset arithmetic element group is opened,
The micro-control unit is sent and the 2nd preset fortune according to preset interval time to the chipset to be powered
Before calculating the corresponding pulse signal of unit group,
The method also includes:
The arithmetic element of the 2nd preset arithmetic element group is not turned on operation.
8. a kind of controlling terminal of series-fed circuit, which is characterized in that including processor, memory and be stored in described deposit
In reservoir and it is configured as the computer program executed by the processor, the processor executes real when the computer program
The now control method of series-fed circuit as claimed in any of claims 1 to 7 in one of claims.
9. a kind of virtual digit coin digs mine machine, including cabinet, the control panel positioned at cabinet inside, the expansion that is connect with the control panel
Panel and the operation board connecting with expansion board, the operation board execute series connection as claimed in any of claims 1 to 7 in one of claims
The control method of power supply circuit.
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| CN201810868052.9A CN109144230B (en) | 2018-08-01 | 2018-08-01 | Control method, terminal and the virtual digit coin of series-fed circuit dig mine machine |
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| CN110308781A (en) * | 2019-03-26 | 2019-10-08 | 深圳大锄科技有限公司 | One kind can tolerance high power density series-fed devices and methods therefor |
| CN111290787B (en) * | 2019-06-19 | 2022-11-08 | 锐迪科（重庆）微电子科技有限公司 | Arithmetic device and arithmetic method |
| CN110413399A (en) * | 2019-08-16 | 2019-11-05 | 紫光展锐(重庆)科技有限公司 | Operation method and arithmetic unit |
| CN110489220A (en) * | 2019-08-16 | 2019-11-22 | 紫光展锐(重庆)科技有限公司 | Arithmetic unit and operation method |
| CN111309353B (en) * | 2020-01-20 | 2023-05-23 | 超越科技股份有限公司 | Method and equipment for updating operation board FPGA firmware based on server control board |
| CN111538382B (en) * | 2020-04-16 | 2021-08-27 | 深圳比特微电子科技有限公司 | Starting method and device of digital currency mining machine and digital currency mining machine |
| CN111966202B (en) * | 2020-08-18 | 2021-06-04 | 深圳比特微电子科技有限公司 | Power supply voltage control method and device of digital currency mining machine and digital currency mining machine |
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| CN107621865B (en) * | 2017-09-20 | 2020-12-11 | 北京比特大陆科技有限公司 | Series power supply circuit and electrifying method, mining machine, server and equipment thereof |
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| JP2009004162A (en) * | 2007-06-20 | 2009-01-08 | Shishido Seidenki Kk | Method for adjusting ion balance |
| CN105045364A (en) * | 2015-07-21 | 2015-11-11 | 北京比特大陆科技有限公司 | Serial power supply circuit, virtual digital coin mining machine and computer server |
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Denomination of invention: Control method, terminal and virtual digital coin digger of series power supply circuit Effective date of registration: 20201010 Granted publication date: 20190712 Pledgee: Bank of China Limited Guangzhou Pearl River Branch Pledgor: UNICMICRO (GUANGZHOU) Co.,Ltd. Registration number: Y2020440000309 |
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Date of cancellation: 20211221 Granted publication date: 20190712 Pledgee: Bank of China Limited Guangzhou Pearl River Branch Pledgor: UNICMICRO (GUANGZHOU) Co.,Ltd. Registration number: Y2020440000309 |