CN109119474B - Normally-off field effect transistor - Google Patents
Normally-off field effect transistor Download PDFInfo
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- CN109119474B CN109119474B CN201810935833.5A CN201810935833A CN109119474B CN 109119474 B CN109119474 B CN 109119474B CN 201810935833 A CN201810935833 A CN 201810935833A CN 109119474 B CN109119474 B CN 109119474B
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- 230000005669 field effect Effects 0.000 title claims abstract description 44
- 239000000463 material Substances 0.000 claims abstract description 93
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 230000004888 barrier function Effects 0.000 claims abstract description 17
- 239000002131 composite material Substances 0.000 claims description 14
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 12
- 229910021389 graphene Inorganic materials 0.000 claims description 12
- 238000002161 passivation Methods 0.000 claims description 12
- 239000003989 dielectric material Substances 0.000 claims description 10
- 229910052582 BN Inorganic materials 0.000 claims description 4
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 4
- CWQXQMHSOZUFJS-UHFFFAOYSA-N molybdenum disulfide Chemical compound S=[Mo]=S CWQXQMHSOZUFJS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052982 molybdenum disulfide Inorganic materials 0.000 claims description 4
- ITRNXVSDJBHYNJ-UHFFFAOYSA-N tungsten disulfide Chemical compound S=[W]=S ITRNXVSDJBHYNJ-UHFFFAOYSA-N 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 60
- 239000002356 single layer Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000012876 topography Methods 0.000 description 3
- 238000007599 discharging Methods 0.000 description 2
- 239000002086 nanomaterial Substances 0.000 description 2
- 230000005355 Hall effect Effects 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002127 nanobelt Substances 0.000 description 1
- 239000002120 nanofilm Substances 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- -1 silylene, germylene Chemical group 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
Abstract
The invention provides a normally-off field effect transistor, which belongs to the field of semiconductor devices and comprises a substrate, at least two-dimensional material layers arranged at the upper side of the substrate at intervals, a source electrode arranged at the upper side of the two-dimensional material layers, a drain electrode arranged at the upper side of the two-dimensional material layers and arranged at intervals with the source electrode, a barrier layer arranged at the upper side of the two-dimensional material layers and positioned between the source electrode and the drain electrode, and at least one gate electrode arranged at the upper side of the barrier layer; and a two-dimensional material fault region is formed between every two adjacent two-dimensional material layers, and at least one side edge of the two-dimensional material fault region protrudes outwards from the side edge of a projection region of the gate electrode on the plane of the two-dimensional material layers. The normally-off field effect transistor provided by the invention can ensure that the transistor can be pinched off, realize normally-off, simultaneously do not sacrifice the mobility and the electronic saturation velocity of the device, and have no loss of the performance of the device.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a normally-off field effect transistor.
Background
Two-dimensional nanomaterials are materials in which electrons are free to move (planar motion) only in two dimensions, on a non-nanoscale (1-100nm) such as a nanofilm. In the past decade, the discovery and research of two-dimensional nanomaterials have been greatly developed, a two-dimensional material family including graphene, hexagonal boron nitride, molybdenum disulfide, tungsten disulfide, silylene, germylene and the like has been formed, and the development of the whole two-dimensional material field has also risen to a new step. Graphene is typical of two-dimensional material devicesAnd (4) representing. It has many excellent physical and chemical properties, is the thinnest and lightest material known at present, has the thickness of only 0.34nm and the specific surface area of 2630m2(ii) in terms of/g. The graphene has peculiar electric transport characteristics, an abnormal integer quantum Hall effect exists, and electrons are dirac fermions without static mass. The graphene has excellent electrical characteristics, extremely high carrier mobility and 2 multiplied by 10 at room temperature5cm2The V.s is 100 times of that of Si material, and the theoretical mobility value can reach 106cm2V · s, the highest of the currently known materials; the saturation velocity of the current carrier is 4-5 multiplied by 107cm/s; the current density is large.
Due to the superior characteristics of the material and the breakthrough of the nano-gate process, the cut-off frequency of the graphene field effect transistor is frequency-refreshed, but the maximum oscillation frequency of the graphene device is always a difficult problem, and the bottleneck problem is that the graphene field effect transistor cannot be clamped off, the output conductance is large, and the application in the fields of high-frequency power and digital circuits is limited. At present, methods for normally turning off a graphene field effect transistor comprise a nanobelt and the like, the mobility and the electronic saturation speed of a device are sacrificed, and the performance loss of the device such as the saturation current and the frequency is large.
Disclosure of Invention
The invention aims to provide a normally-off type field effect transistor, and the technical problem that device performance loss of saturation current and frequency of the normally-off type graphene field effect transistor is large in the prior art is solved.
In order to achieve the purpose, the invention adopts the technical scheme that: provided is a normally-off type field effect transistor including: the transistor comprises a substrate, at least two-dimensional material layers arranged on the upper side of the substrate at intervals, a source electrode arranged on the upper side of the two-dimensional material layers, a drain electrode arranged on the upper side of the two-dimensional material layers at intervals with the source electrode, a barrier layer arranged on the upper side of the two-dimensional material layers and positioned between the source electrode and the drain electrode, and at least one gate electrode arranged on the upper side of the barrier layer; and a two-dimensional material fault region is formed between every two adjacent two-dimensional material layers, and at least one side edge of the two-dimensional material fault region protrudes outwards from the side edge of a projection region of the gate electrode on the plane of the two-dimensional material layers.
Further, the width of the two-dimensional material fault region is larger than or equal to 1nm and smaller than or equal to 10 μm.
Further, the width of the two-dimensional material fault region is greater than or equal to 10nm and less than or equal to 300 nm.
Further, the gate electrode is one or a combination of a straight gate, a T-shaped gate, a TT-shaped gate, a TTT-shaped gate, a V-shaped gate, a U-shaped gate or a Y-shaped gate.
Further, the two-dimensional material layer is a graphene member, a boron nitride member, a molybdenum disulfide member, a tungsten disulfide member, a black phosphorus member, a silylene member or a germanium silylene member.
Further, the substrate is an insulating dielectric member, a semiconductor member, or a multilayer composite member composed of an insulating dielectric material and a semiconductor material.
Further, the barrier layer is an insulating dielectric member, a semiconductor member or a multilayer composite member composed of an insulating dielectric material and a semiconductor material.
Further, the normally-off field effect transistor further comprises an epitaxial layer arranged on the upper surface of the substrate, and the two-dimensional material layer is arranged on the upper surface of the epitaxial layer.
Further, the epitaxial layer is a semiconductor member.
Further, the normally-off type field effect transistor further includes a passivation layer disposed on an upper side of the blocking layer, the passivation layer is connected to the gate electrode and the source electrode, and the passivation layer is further connected to the gate electrode and the drain electrode.
The normally-off field effect transistor provided by the invention has the beneficial effects that: compared with the prior art, the normally-off field effect transistor has the advantages that the two-dimensional material fault region is arranged below the gate electrode and protrudes out of the gate electrode, and when the normally-off field effect transistor is used, the barrier height and the shape of the carrier fault region are adjusted through the gate voltage, so that carriers can pass through the two-dimensional material fault region at high speed, and a device is started; when the device is started, the current carriers of the two-dimensional material fault region move at a high speed, and the saturation current is large; the device is turned on and off only by controlling the charging and discharging of a small amount of electrons in the two-dimensional material fault region, and the switching speed is high; when the device is started, the influence of the width of the two-dimensional material fault region on the threshold voltage is large, and the ultra-wide region of the threshold voltage can be controlled. The normally-off field effect transistor provided by the invention can be clamped off, normally-off is realized, the mobility and the electronic saturation speed of the device are not sacrificed, and the performance of the device is not lost.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a normally-off fet according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a normally-off fet according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of a normally-off fet according to a third embodiment of the present invention.
Wherein, in the figures, the respective reference numerals:
1-a substrate; 2-a two-dimensional material layer; 3-a source electrode; 4-a drain electrode; 5-a barrier layer; 6-a gate electrode; 7-two-dimensional material fault zone; 8-an epitaxial layer; 9-passivation layer
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1 to fig. 3, a normally-off fet according to the present invention will be described. The normally-off field effect transistor comprises a substrate 1, at least two-dimensional material layers 2 arranged on the upper side of the substrate 1 at intervals, a source electrode 3 arranged on the upper side of the two-dimensional material layer 2, a drain electrode 4 arranged on the upper side of the two-dimensional material layer 2 at intervals with the source electrode 3, a barrier layer 5 arranged on the upper side of the two-dimensional material layer 2 and positioned between the source electrode 3 and the drain electrode 4, and at least one gate electrode 6 arranged on the upper side of the barrier layer 5; two-dimensional material fault areas 7 are formed between two adjacent two-dimensional material layers 2, and at least one side edge of each two-dimensional material fault area 7 protrudes outwards from the side edge of the projection area of the gate electrode 6 on the plane of the two-dimensional material layers 2.
The two-dimensional material layer 2 is predominantly nanoscale in the thickness direction and non-nanoscale in a direction parallel to the upper surface of the substrate 1.
It should be noted that at least one side edge of the two-dimensional material fault region 7 protrudes outward from the side edge of the projection region of the gate electrode 6 on the plane of the two-dimensional material layer 2, specifically, two side edges of the projection region of a single gate electrode 6 on the plane of the two-dimensional material layer 2 cannot completely include two side edges of a single two-dimensional material fault region 7, two side edges of a single projection region cannot coincide with two side edges of a single two-dimensional material fault region 7 at the same time, and at least one side of the two-dimensional material fault region 7 must protrude outward from the projection region of the gate electrode 6 on the plane of the two-dimensional material layer 2.
The two-dimensional material fault 7 region can be prepared by etching, oxidation or plasma treatment and the like so as to realize the carrier fault of the channel region beside the gate and the pinch-off of the device.
Wherein, fig. 1 shows a normally-off type field effect transistor based on two-dimensional material, and the area between the arrows A-A' is a two-dimensional material fault area 7; FIG. 2 shows a dual-gate two-dimensional normally-off FET, wherein the region between the arrows B-B' is a two-dimensional material fault region 7; fig. 3 shows a tri-gate two-dimensional normally-off fet, where the regions between the arrows C-C 'and D-D' are two-dimensional material fault regions 7, respectively.
Compared with the prior art, the normally-off field effect transistor provided by the invention has the advantages that the two-dimensional material fault region 7 is arranged below the gate electrode 6 and protrudes out of the gate electrode 6, and when the normally-off field effect transistor is used, the barrier height and the shape of the carrier fault region are adjusted through the gate voltage, so that carriers can pass through the two-dimensional material fault region at a high speed, and a device is started; when the device is started, the current carrier of the two-dimensional material fault region 7 moves at a high speed, and the saturation current is large; the device is turned on and off only by controlling the charging and discharging of a small amount of electrons in the two-dimensional material fault 7 area, and the switching speed is high; when the device is started, the width of the two-dimensional material fault region 7 has large influence on the threshold voltage, and the ultra-wide region of the threshold voltage can be controlled. The normally-off field effect transistor provided by the invention can be clamped off, normally-off is realized, the mobility and the electronic saturation speed of the device are not sacrificed, and the performance of the device is not lost.
In one embodiment of the normally-off field effect transistor according to the present invention, the width of the two-dimensional material fault region 7 is 1nm or more and 10 μm or less. By properly setting the width of the two-dimensional material fault region 7, the switching speed can be effectively controlled to obtain better device performance.
Optionally, as a specific embodiment of the normally-off fet provided in the present invention, to balance the difficulty of the manufacturing process and the device performance, the width of the two-dimensional material fault region 7 is greater than or equal to 10nm and less than or equal to 300 nm.
Referring to fig. 1 to 3, in order to meet different device performance requirements, the gate electrode 6 of the normally-off fet according to an embodiment of the present invention is one or more combinations of a straight gate, a T-gate, a TT-gate, a TTT-gate, a V-gate, a U-gate, or a Y-gate. The above-mentioned model mainly corresponds to the topography of the gate electrode 6. For example, the embodiments of fig. 1 and 2 both use straight gates, while the embodiment of fig. 3 is a combination of straight gates and T-shaped gates. The topography of the gate electrode 6 includes, but is not limited to, the topography described above.
As a specific embodiment of the normally-off type field effect transistor provided by the present invention, when the gate electrode 6 has a plurality of gate electrodes, the length of each gate electrode 6 may be equal or may not be equal.
In a case where the gate electrode 6 has a plurality of gate electrodes, different gate electrodes 6 may be connected to the same metal electrode (metal PAD) or different metal electrodes (metal PAD).
As a specific embodiment of the normally-off type field effect transistor provided by the present invention, in order to make the two-dimensional material layer 2 have good electrical properties, the two-dimensional material layer 2 is a graphene member, a boron nitride member, a molybdenum disulfide member, a tungsten disulfide member, a black phosphorus member, a silylene member, or a germanium silylene member.
In order to meet the requirements of different device performances, the substrate 1 is an insulating dielectric member, a semiconductor member, or a multilayer composite member composed of an insulating dielectric material and a semiconductor material. The multilayer composite member composed of the insulating dielectric material and the semiconductor material may be such that the substrate 1 has a multilayer structure, each layer structure being either an insulating dielectric material or a semiconductor material, the layers being stacked in a predetermined order to form the substrate 1. The insulating dielectric member may be a single-layer structure or a multilayer composite structure, and the semiconductor member may be a single-layer structure or a multilayer composite structure.
Further, as a specific embodiment of the normally-off type field effect transistor provided by the present invention, the barrier layer 5 is an insulating dielectric member, a semiconductor member, or a multilayer composite member composed of an insulating dielectric material and a semiconductor material. The multilayer composite member composed of the insulating dielectric material and the semiconductor material may be such that the barrier layer 5 has a multilayer structure, each layer structure being an insulating dielectric material or a semiconductor material, the layers being stacked in a predetermined order to form the barrier layer 5. The insulating dielectric member may be a single-layer structure or a multilayer composite structure, and the semiconductor member may be a single-layer structure or a multilayer composite structure.
In particular, the barrier layer 5 is Al2O3Member and HfO2A component or a high resistance semiconductor component.
Referring to fig. 1 and fig. 2, as an embodiment of the normally-off fet provided in the present invention, the normally-off fet further includes an epitaxial layer 8 disposed on the upper surface of the substrate 1, and the two-dimensional material layer 2 is disposed on the upper surface of the epitaxial layer 8.
As a specific embodiment of the normally-off type field effect transistor provided by the present invention, the epitaxial layer 8 is a semiconductor member. The semiconductor member may be a single-layer structure or a multi-layer composite structure.
Referring to fig. 2, as an embodiment of the normally-off type field effect transistor provided by the present invention, the normally-off type field effect transistor further includes a passivation layer 9 disposed on the upper side of the blocking layer 5, the passivation layer 9 is respectively connected to the gate electrode 6 and the source electrode 3, and the passivation layer 9 is further respectively connected to the gate electrode 6 and the drain electrode 4.
As a specific embodiment of the normally-off type field effect transistor provided by the present invention, the passivation layer 9 has a single insulating layer structure or a composite insulating layer structure.
As a specific embodiment of the normally-off field effect transistor provided by the present invention, the basic device structure of the normally-off field effect transistor of the present invention may be a source field plate, a drain field plate, a gate field plate, a floating field plate, or an air bridge field plate, or may be a combination structure of the above field plates.
It should be understood that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the present invention (e.g., the two-dimensional material fault region 7 is formed by a method other than the method exemplified by the present invention, the substrate 1 is selected as an external insulating layer or semiconductor exemplified by the present invention, the epitaxial layer 8 is directly epitaxial-grown onto the substrate 1 or transferred onto another substrate, the gate electrode 6 is selected as an external shape exemplified by the present invention, the passivation layer 9 is selected as an external insulating layer or material exemplified by the present invention), are all included in the protection scope of the present invention.
Claims (10)
1. A normally-off field effect transistor characterized by: the transistor comprises a substrate, at least two-dimensional material layers arranged on the upper side of the substrate at intervals, a source electrode arranged on the upper side of the two-dimensional material layers, a drain electrode arranged on the upper side of the two-dimensional material layers at intervals with the source electrode, a barrier layer arranged on the upper side of the two-dimensional material layers and positioned between the source electrode and the drain electrode, and at least one gate electrode arranged on the upper side of the barrier layer; and a two-dimensional material fault region is formed between two adjacent two-dimensional material layers, at least one side edge of the two-dimensional material fault region protrudes outwards from the side edge of the projection region of the gate electrode on the plane of the two-dimensional material layers, and an overlapping region exists between the two-dimensional material fault region and the projection region of the gate electrode on the plane of the two-dimensional material layers.
2. A normally-off field effect transistor as claimed in claim 1, wherein: the width of the two-dimensional material fault region is greater than or equal to 1nm and less than or equal to 10 mu m.
3. A normally-off field effect transistor as claimed in claim 2, wherein: the width of the two-dimensional material fault region is greater than or equal to 10nm and less than or equal to 300 nm.
4. A normally-off field effect transistor as claimed in claim 1, wherein: the grid electrode is one or a combination of a plurality of straight grids, T-shaped grids, TT-shaped grids, TTT-shaped grids, V-shaped grids, U-shaped grids or Y-shaped grids.
5. A normally-off field effect transistor as claimed in claim 1, wherein: the two-dimensional material layer is a graphene member, a boron nitride member, a molybdenum disulfide member, a tungsten disulfide member, a black phosphorus member, a silylene member or a germanium silylene member.
6. A normally-off field effect transistor as claimed in claim 1, wherein: the substrate is an insulating dielectric member, a semiconductor member or a multilayer composite member composed of an insulating dielectric material and a semiconductor material.
7. A normally-off field effect transistor as claimed in claim 1, wherein: the barrier layer is an insulating dielectric member, a semiconductor member or a multilayer composite member composed of an insulating dielectric material and a semiconductor material.
8. A normally-off field effect transistor as claimed in claim 1, wherein: the normally-off field effect transistor further comprises an epitaxial layer arranged on the upper surface of the substrate, and the two-dimensional material layer is arranged on the upper surface of the epitaxial layer.
9. The normally-off field effect transistor of claim 8, wherein: the epitaxial layer is a semiconductor member.
10. A normally-off field effect transistor as claimed in claim 1, wherein: the normally-off field effect transistor further comprises a passivation layer arranged on the upper side of the blocking layer, the passivation layer is respectively connected with the gate electrode and the source electrode, and the passivation layer is further respectively connected with the gate electrode and the drain electrode.
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|---|---|---|---|---|
| CN104103696A (en) * | 2013-04-15 | 2014-10-15 | 清华大学 | Bipolar thin film transistor |
| US9252247B1 (en) * | 2010-06-02 | 2016-02-02 | Hrl Laboratories, Llc | Apparatus and method for reducing the interface resistance in GaN Heterojunction FETs |
| KR101718961B1 (en) * | 2010-11-05 | 2017-03-23 | 삼성전자주식회사 | Semiconductor device comprising Graphene and method of manufacturing the same |
| CN107994078A (en) * | 2017-12-14 | 2018-05-04 | 北京华碳科技有限责任公司 | Field-effect transistor, manufacture method and electronic device with source electrode coordination electrode |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9252247B1 (en) * | 2010-06-02 | 2016-02-02 | Hrl Laboratories, Llc | Apparatus and method for reducing the interface resistance in GaN Heterojunction FETs |
| KR101718961B1 (en) * | 2010-11-05 | 2017-03-23 | 삼성전자주식회사 | Semiconductor device comprising Graphene and method of manufacturing the same |
| CN104103696A (en) * | 2013-04-15 | 2014-10-15 | 清华大学 | Bipolar thin film transistor |
| CN107994078A (en) * | 2017-12-14 | 2018-05-04 | 北京华碳科技有限责任公司 | Field-effect transistor, manufacture method and electronic device with source electrode coordination electrode |
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