CN109119462A - A kind of silicon carbide groove MOS device - Google Patents
A kind of silicon carbide groove MOS device Download PDFInfo
- Publication number
- CN109119462A CN109119462A CN201810992057.2A CN201810992057A CN109119462A CN 109119462 A CN109119462 A CN 109119462A CN 201810992057 A CN201810992057 A CN 201810992057A CN 109119462 A CN109119462 A CN 109119462A
- Authority
- CN
- China
- Prior art keywords
- type
- layer
- slot
- axis
- silicon carbide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 19
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 19
- 238000000407 epitaxy Methods 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 8
- NTHWMYGWWRZVTN-UHFFFAOYSA-N sodium silicate Chemical compound [Na+].[Na+].[O-][Si]([O-])=O NTHWMYGWWRZVTN-UHFFFAOYSA-N 0.000 claims description 3
- 238000003780 insertion Methods 0.000 claims description 2
- 230000037431 insertion Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 claims 15
- 239000002344 surface layer Substances 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 abstract 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 239000000377 silicon dioxide Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 239000002305 electric material Substances 0.000 description 4
- 238000005457 optimization Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 241000790917 Dioxys <bee> Species 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention belongs to power semiconductor technologies fields, and in particular to a kind of silicon carbide groove MOS device.Present invention be primarily characterized in that: T-shaped slot grid structure is used, drift region concentration is improved in assisted depletion drift region, reduces conducting resistance, while improving breakdown voltage；Using p type buried layer as buffer layer, saturation current is reduced, improves anti-short circuit capability.Compared to traditional silicon carbide groove MOS device, the present invention not only has lower conducting resistance, higher breakdown voltage, but also has better anti-short circuit capability.
Description
Technical field
The invention belongs to power semiconductor technologies fields, and in particular to a kind of silicon carbide groove MOS device.
Background technique
Silicon carbide is as third generation semiconductor material, the spy with broad stopband, high saturation drift velocity and high heat conductance
Property, it is suitble to manufacture high-power semiconductor devices.Silicon carbide groove MOS device has compared to conventional planar MOS device
Bigger gully density is to have lower conducting resistance.However, there are gate oxide electric field mistakes for silicon carbide groove MOS device
High and excessive saturation current problem.There is researcher to be directed to both of these problems respectively to study: by P buried layer come shield grid
Oxide layer reduces its electric field, and the area JFET resistance can be introduced by doing so；By further increasing the area the JFET resistance, to accelerate JFET
The pinch off in area realizes the reduction of saturation current.
Summary of the invention
The purpose of the present invention proposes that one kind has both high-breakdown-voltage, low on-resistance and low full aiming at the above problem
With the silicon carbide groove MOS device of electric current.
Technical solution of the present invention is as follows:
A kind of silicon carbide groove MOS device, the N-type epitaxy layer including N+ substrate layer 1 and positioned at 1 upper surface of N+ substrate layer
2；Draw drain electrode in the bottom of the N+ substrate layer 1；On 2 upper layer of N-type epitaxy layer, insertion is provided with slot grid structure；
On 2 upper layer of N-type epitaxy layer and slot grid structure region arranged side by side, successively there is P from bottom to top along device vertical direction
Type buried layer 3, the area JFET 4, P type trap zone 5 and N+ source region 6；
Device transverse cross-sectional view is defined as rectangular coordinate plane, i.e. device transverse direction is x-axis, and device vertical direction is
Y-axis, defining device longitudinal direction is third dimension direction vertical with device transverse direction and device vertical direction simultaneously, i.e.,
Z-axis, x-axis, y-axis and z-axis constitute three-dimensional system of coordinate；
Middle part along the z-axis direction has P+ body contact zone 7, and P+ body contact zone 7 sequentially passes through N+ source region along the y-axis direction
6, the bottom in P type trap zone 5 and the area JFET 4, P+ body contact zone 7 connects with p type buried layer 3；The N+ source region 6 and P+ body contact zone 7
Upper surface draw source electrode；
Along the z-axis direction, the p type buried layer 3 has bulge-structure, i.e., along the z-axis direction, the central region of p type buried layer 3 is along x
Axis direction extends, and the bulge-structure is contacted with P+ body contact zone 7；
The slot grid structure in T-shaped, i.e., by grid conducting material 8 and gate dielectric layer 9 form shallow and wide conductive trough,
The deep and narrow media slot 10 below conductive trough；The bottom of the conductive trough is in contact with the top of p type buried layer 3；It is given an account of
Matter slot 10 extends vertically through p type buried layer 3 and extends into N-type epitaxy layer 2；The grid conducting material 8 draws gate electrode.
Further, the medium filled in the media slot 10 is low-K dielectric, and the low-K dielectric refers to that K value is less than or equal to
The medium of silica K value.
Further, the medium filled in the media slot 10 is high K dielectric, and the high K dielectric refers to that K value is greater than dioxy
The medium of SiClx K value.
Further, the side and bottom surface of the media slot 10 have p-type item 11, the N-type drift region 2 and the p-type
Item 11 forms superjunction.
Beneficial effects of the present invention are, relative to Conventional silicon carbide groove MOS device, the present invention not only has higher hit
Voltage, lower conducting resistance are worn, and there is better short-circuit capacity.
Detailed description of the invention
Fig. 1 is main structural schematic diagram；
The structural schematic diagram of the position Fig. 2 embodiment 1；
The structural schematic diagram of the position Fig. 3 embodiment 2；
The structural schematic diagram of the position Fig. 4 embodiment 3,4；
What is successively provided in above-mentioned attached drawing is main view, the sectional view of AA ' line and along the section of BB ' line along main view
Figure.
Specific embodiment
The present invention is further described with reference to the accompanying drawings and examples.
Embodiment 1
As shown in Fig. 2, this example is the silicon carbide groove MOS device with low-K dielectric slot, including N+ substrate layer 1 and N
Type epitaxial layer 2；Slot grid structure is in N-type epitaxy layer 2；Draw drain electrode in the bottom of the N+ substrate layer 1；
The device transverse direction is mutually perpendicular to device vertical direction, longitudinal direction be simultaneously with device transverse direction and
The vertical third dimension direction of device vertical direction；
The top of the N-type epitaxy layer 2 sequentially forms p type buried layer 3, the area JFET 4, P along device vertical direction from bottom to top
Type well region 5 and N+ source region 6；P+ body contact zone 7 on longitudinal direction extends vertically through N+ source region 6, P type trap zone 5 and the area JFET 4,
Its bottom connects with p type buried layer 3；There are gaps in device transverse direction and longitudinal direction for the p type buried layer 3；The N+
Draw source electrode in the upper surface of source region 6 and P+ body contact zone 7；
The slot grid structure presentation is T-shaped, including the shallow and wide slot being made of grid conducting material 8 and gate dielectric layer 9
Deep and narrow media slot 10 below；The shallow slot extends vertically through N+ source region 6, P type trap zone 5 and the area JFET 4, and its bottom with
The top of p type buried layer 3 is in contact；The media slot 10 extends vertically through p type buried layer 3 and gos deep into N-type epitaxy layer 2；The grid is led
Electric material 8 draws gate electrode；Insert low-K dielectric in the media slot 10, including silica and K value it is lower than silica
Medium.
The working principle of this example is:
Media slot assisted depletion N-type drift region improves the optimization doping concentration of N-type drift region, reduces and compare electric conduction
Resistance.Meanwhile gate leakage capacitance can be effectively reduced in media slot, improves switching characteristic.
Embodiment 2
As shown in figure 3, this example is the silicon carbide groove MOS device with high K dielectric slot, including N+ substrate layer 1 and N
Type epitaxial layer 2；Slot grid structure is in N-type epitaxy layer 2；Draw drain electrode in the bottom of the N+ substrate layer 1；
The device transverse direction is mutually perpendicular to device vertical direction, longitudinal direction be simultaneously with device transverse direction and
The vertical third dimension direction of device vertical direction；
The top of the N-type epitaxy layer 2 sequentially forms p type buried layer 3, the area JFET 4, P along device vertical direction from bottom to top
Type well region 5 and N+ source region 6；P+ body contact zone 7 on longitudinal direction extends vertically through N+ source region 6, P type trap zone 5 and the area JFET 4,
Its bottom connects with p type buried layer 3；There are gaps in device transverse direction and longitudinal direction for the p type buried layer 3；The N+
Draw source electrode in the upper surface of source region 6 and P+ body contact zone 7；
The slot grid structure presentation is T-shaped, including the shallow and wide slot being made of grid conducting material 8 and gate dielectric layer 9
Deep and narrow media slot 10 below；The shallow slot extends vertically through N+ source region 6, P type trap zone 5 and the area JFET 4, and its bottom with
The top of p type buried layer 3 is in contact；The media slot 10 extends vertically through p type buried layer 3 and gos deep into N-type epitaxy layer 2；The grid is led
Electric material 8 draws gate electrode；High K dielectric is inserted in the media slot 10, refers specifically to the medium higher than silica for K value.
Compared with Example 1, high K dielectric can enhance assisted depletion N-type drift region, so that N-type drift region optimization doping is dense
Degree further increases, and further decreases than conducting resistance.
Embodiment 3
As shown in figure 4, this example is the silicon carbide superjunction groove MOS device with low-K dielectric slot, including N+ substrate layer 1
And N-type epitaxy layer 2；Slot grid structure is in N-type epitaxy layer 2；Draw drain electrode in the bottom of the N+ substrate layer 1；
The device transverse direction is mutually perpendicular to device vertical direction, longitudinal direction be simultaneously with device transverse direction and
The vertical third dimension direction of device vertical direction；
The top of the N-type epitaxy layer 2 sequentially forms p type buried layer 3, the area JFET 4, P along device vertical direction from bottom to top
Type well region 5 and N+ source region 6；P+ body contact zone 7 on longitudinal direction extends vertically through N+ source region 6, P type trap zone 5 and the area JFET 4,
Its bottom connects with p type buried layer 3；There are gaps in device transverse direction and longitudinal direction for the p type buried layer 3；The N+
Draw source electrode in the upper surface of source region 6 and P+ body contact zone 7；
The slot grid structure presentation is T-shaped, including the shallow and wide slot being made of grid conducting material 8 and gate dielectric layer 9
Deep and narrow media slot 10 below；The shallow slot extends vertically through N+ source region 6, P type trap zone 5 and the area JFET 4, and its bottom with
The top of p type buried layer 3 is in contact；The media slot 10 extends vertically through p type buried layer 3 and gos deep into N-type epitaxy layer 2；The grid is led
Electric material 8 draws gate electrode；Insert low-K dielectric in the media slot 10, including silica and K value it is lower than silica
Medium；There are p-type item 11, the N-type drift regions 2 to be formed with the p-type item 11 super for the side and bottom surface of the media slot 10
Knot；
Compared with Example 1, since assisted depletion of the p-type item 11 to N-type drift region acts on, N-type drift region optimization doping
Concentration further increases, and further decreases than conducting resistance；Compared with Example 2, it since the gate leakage capacitance of device reduces, reduces
Devices switch loss.
Embodiment 4
As shown in figure 4, this example is the silicon carbide superjunction groove MOS device with high K dielectric slot, including N+ substrate layer 1
And N-type epitaxy layer 2；Slot grid structure is in N-type epitaxy layer 2；Draw drain electrode in the bottom of the N+ substrate layer 1；
The device transverse direction is mutually perpendicular to device vertical direction, longitudinal direction be simultaneously with device transverse direction and
The vertical third dimension direction of device vertical direction；
The top of the N-type epitaxy layer 2 sequentially forms p type buried layer 3, the area JFET 4, P along device vertical direction from bottom to top
Type well region 5 and N+ source region 6；P+ body contact zone 7 on longitudinal direction extends vertically through N+ source region 6, P type trap zone 5 and the area JFET 4,
Its bottom connects with p type buried layer 3；There are gaps in device transverse direction and longitudinal direction for the p type buried layer 3；The N+
Draw source electrode in the upper surface of source region 6 and P+ body contact zone 7；
The slot grid structure presentation is T-shaped, including the shallow and wide slot being made of grid conducting material 8 and gate dielectric layer 9
Deep and narrow media slot 10 below；The shallow slot extends vertically through N+ source region 6, P type trap zone 5 and the area JFET 4, and its bottom with
The top of p type buried layer 3 is in contact；The media slot 10 extends vertically through p type buried layer 3 and gos deep into N-type epitaxy layer 2；The grid is led
Electric material 8 draws gate electrode；High K dielectric is inserted in the media slot 10, refers specifically to the medium higher than silica for K value；
There are p-type item 11, the N-type drift regions 2 to form superjunction with the p-type item 11 for the side and bottom surface of the media slot 10；
Compared with Example 3, since high K dielectric slot and superjunction jointly act on N-type drift region assisted depletion, N-type drift
Area's optimization doping concentration further increases, and further decreases and compares conducting resistance.
Claims (4)
1. a kind of silicon carbide groove MOS device, including N+ substrate layer (1) and positioned at the N-type extension of N+ substrate layer (1) upper surface
Layer (2)；Draw drain electrode in the bottom of the N+ substrate layer (1)；On N-type epitaxy layer (2) upper layer, insertion is provided with slot grid structure；
On N-type epitaxy layer (2) upper layer and slot grid structure region arranged side by side, successively there is p-type from bottom to top along device vertical direction
Buried layer (3), the area JFET (4), P type trap zone (5) and N+ source region (6)；
Device transverse cross-sectional view is defined as rectangular coordinate plane, i.e. device transverse direction is x-axis, and device vertical direction is y-axis,
Defining device longitudinal direction is the third dimension direction vertical with device transverse direction and device vertical direction, i.e. z-axis simultaneously,
X-axis, y-axis and z-axis constitute three-dimensional system of coordinate；
Middle part along the z-axis direction has P+ body contact zone (7), and P+ body contact zone (7) sequentially passes through N+ source region along the y-axis direction
(6), the bottom of P type trap zone (5) and the area JFET (4), P+ body contact zone (7) connects with p type buried layer (3)；The N+ source region (6) and
Draw source electrode in the upper surface of P+ body contact zone (7)；
Along the z-axis direction, the p type buried layer (3) has bulge-structure, i.e., along the z-axis direction, the central region of p type buried layer (3) is along x
Axis direction extends, and the bulge-structure position is contacted with P+ body contact zone (7)；
The slot grid structure in T-shaped, i.e., by grid conducting material (8) and gate dielectric layer (9) form shallow and wide conductive trough,
The deep and narrow media slot (10) below conductive trough；It is in contact at the top of the bottom of the conductive trough and p type buried layer (3)；Institute
Media slot (10) is stated to extend vertically through p type buried layer (3) and extend into N-type epitaxy layer (2)；The grid conducting material (8) draws grid
Pole electrode.
2. a kind of silicon carbide groove MOS device according to claim 1, which is characterized in that filled out in the media slot (10)
The medium filled is low-K dielectric, and the low-K dielectric refers to that K value is less than or equal to the medium of silica K value.
3. a kind of silicon carbide groove MOS device according to claim 1, which is characterized in that filled out in the media slot (10)
The medium filled is high K dielectric, and the high K dielectric refers to that K value is greater than the medium of silica K value.
4. a kind of silicon carbide groove MOS device according to claim 2 or 3, which is characterized in that the media slot (10)
Side and bottom surface have p-type item (11), and the N-type drift region (2) and the p-type item (11) form superjunction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810992057.2A CN109119462B (en) | 2018-08-29 | 2018-08-29 | Silicon carbide groove MOS device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810992057.2A CN109119462B (en) | 2018-08-29 | 2018-08-29 | Silicon carbide groove MOS device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109119462A true CN109119462A (en) | 2019-01-01 |
| CN109119462B CN109119462B (en) | 2021-10-08 |
Family
ID=64861396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810992057.2A Active CN109119462B (en) | 2018-08-29 | 2018-08-29 | Silicon carbide groove MOS device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109119462B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449757A (en) * | 2016-09-28 | 2017-02-22 | 中国科学院半导体研究所 | SiC-based groove-type field effect transistor and preparation method thereof |
| US20180040698A1 (en) * | 2016-08-05 | 2018-02-08 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
-
2018
- 2018-08-29 CN CN201810992057.2A patent/CN109119462B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20180040698A1 (en) * | 2016-08-05 | 2018-02-08 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
| CN106449757A (en) * | 2016-09-28 | 2017-02-22 | 中国科学院半导体研究所 | SiC-based groove-type field effect transistor and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109119462B (en) | 2021-10-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10818782B2 (en) | Insulated-gate bipolar transistor (IGBT) including a branched gate trench | |
| CN106024858B (en) | A kind of HK SOI LDMOS devices with three grid structures | |
| CN104201206B (en) | A kind of laterally SOI power LDMOS device | |
| JP2018186270A (en) | SiC SEMICONDUCTOR DEVICE HAVING OFFSET AT TRENCH LOWER PART | |
| CN103715238B (en) | A kind of lateral high-voltage device of Ultra-low Specific conducting resistance | |
| CN105633137B (en) | A kind of slot gate power MOSFET device | |
| CN113130627B (en) | Silicon carbide fin-shaped gate MOSFET integrated with channel diode | |
| CN107808899B (en) | Lateral power device with mixed conduction mode and preparation method thereof | |
| US10490658B2 (en) | Power semiconductor device | |
| JP2008205497A (en) | Low on-state resistance trench type mosfet with delta layer | |
| JP6356803B2 (en) | Insulated gate bipolar transistor | |
| CN104183646A (en) | SOI LDMOS device with extending gate structure | |
| CN105789314A (en) | Transverse SOI power LDMOS | |
| CN106816468B (en) | Lateral diffusion metal oxide semiconductor field effect transistor with RESURF structure | |
| CN109713041B (en) | Improved structure suitable for super junction DMOS device | |
| CN106024897A (en) | Three-gate power LDMOS | |
| CN110518065A (en) | The groove-shaped silicon carbide MOSFET device of low power consumption and high reliability | |
| CN110310983A (en) | A kind of hyperconjugation VDMOS device | |
| CN102969355A (en) | Silicon on insulator (SOI)-based metal-oxide-semiconductor field-effect transistor (PMOSFET) power device | |
| CN106024905A (en) | Low on-resistance lateral double-diffusion metal oxide semiconductor device | |
| CN103474463B (en) | There is the MOSFET in the induction net charge district in thick bottom insulator | |
| CN109920839A (en) | P+ shielded layer current potential is adjustable silicon carbide MOSFET device and preparation method | |
| CN109904220A (en) | Groove gate type silicon carbide MOSFET device and preparation method | |
| CN109148591A (en) | A kind of silicon carbide tank grate MOS device of integrated schottky diode | |
| CN109564943A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |