CN109119012B - Starting-up method and circuit - Google Patents
Starting-up method and circuit Download PDFInfo
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- CN109119012B CN109119012B CN201810978787.7A CN201810978787A CN109119012B CN 109119012 B CN109119012 B CN 109119012B CN 201810978787 A CN201810978787 A CN 201810978787A CN 109119012 B CN109119012 B CN 109119012B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
- G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
Abstract
The embodiment of the application discloses a startup method and a startup circuit, wherein the method comprises the following steps: receiving a first time sequence signal of the M frames of images output by the image enhancement chip; if the first sequence signal of the N frames of images in the first sequence signals of the M frames of images is the same as the first preset value, a first message is sent to the controller, so that the controller controls the receiving module and the signal analyzing module to reset according to the first message. Whether the signal that image enhancement chip output is stable can accurately be determined based on the first time sequence signal of image enhancement chip inside output like this, and then realize the accurate detection to the front end signal to when detecting the front end signal steady, restart signal receiving module and signal analysis module, and then avoid the problem of the display screen flower screen or black screen that causes because the signal of front end output is unstable.
Description
Technical Field
The embodiment of the application relates to the technical field of startup display, in particular to a startup method and a startup circuit.
Background
For a display provided with an SOC (System on Chip), since there is no floating point operation in the SOC, complicated standard calculations such as DICOM (Digital Imaging and Communications in Medicine) cannot be performed, and thus automatic calibration of the DICOM built in the display cannot be realized. At the moment, if signal transmission is unstable in the power-on starting stage, display problems such as screen splash, wire drawing, screen blacking and the like can occur.
In the existing method, a timing detection mechanism inside an FPGA (Field-Programmable Gate Array) is used to detect whether a signal at the front end of a display is stable. However, in the existing method, when the parameter design is not accurate, the problems of flickering or sudden screen blacking after starting up still occur.
Disclosure of Invention
The embodiment of the application provides a startup method and a startup circuit.
In a first aspect, an embodiment of the present application provides a power-on starting method, where the method is applied to a power-on starting circuit, where the power-on starting circuit includes an image enhancement chip, a signal receiving module, a signal analyzing module, a detecting module, and a controller, and the method includes:
the detection module receives a first time sequence signal of the M frames of images output by the image enhancement chip;
if the first timing signal of the N frames of images in the first timing signals of the M frames of images is the same as the first preset value, the detection module sends a first message to the controller, so that the controller controls the signal receiving module and the signal analyzing module to reset according to the first message, wherein the first message is used for indicating that the signal receiving module and the signal analyzing module are reset.
In a possible implementation manner of the first aspect, the method further includes:
if the first timing signal of the P frame image in the first timing signals of the M frame images is the same as a first preset value, the detection module determines whether a second timing signal output by the signal analysis module is the same as a second preset value, where P is greater than N, and the second timing signal is a timing signal of an M +1 th frame image output by the image enhancement chip;
if not, sending a first message to the controller so that the controller controls the signal receiving module and the signal analyzing module to reset according to the first message.
In another possible implementation manner of the first aspect, the method further includes:
if the second timing signal is the same as the second preset value, the detection module sends a second message to the controller so that the image processing module, the signal coding module and the sending module perform de-resetting;
the detection module judges whether a feedback signal output by the display screen is equal to a third preset value or not;
if not, the detection module sends a third message to the controller, so that the controller controls the signal coding module and the sending module to reset according to the third message, wherein the third message is used for indicating that the signal coding module and the sending module are reset;
and if so, the detection module sends a preparation signal to a main control chip so that the main control chip sends a display signal.
In another possible implementation manner of the first aspect, before the detecting module receives the first timing signal of the M-frame image output by the image enhancement chip, the method further includes:
the controller controls the signal receiving module and the signal analyzing module to perform initial solution and reset.
In another possible implementation manner of the first aspect, after the controller controls the signal encoding module and the sending module to reset according to the third message, the method further includes:
the detection module judges whether the response signal output by the signal analysis module is equal to a fourth preset value or not;
if not, the detection module sends the first message to the controller, so that the controller controls the signal receiving module and the signal analyzing module to reset according to the first message;
and if so, the detection module receives a first time sequence signal of the M frames of images output by the image enhancement chip.
In another possible implementation manner of the first aspect, the controlling, by the controller, the signal receiving module and the signal parsing module to reset according to the first message includes:
the controller controls the receiving module and the signal analysis module to be reset after a preset time period.
In another possible implementation manner of the first aspect, the signal receiving module, the signal analyzing module, the image processing module, the signal encoding module, and the sending module are all disposed on an editable gate array chip.
In another possible implementation manner of the first aspect, the main control chip, the image enhancement chip, and the editable gate array chip are sequentially powered on and started.
In another possible implementation manner of the first aspect, the detection module is disposed on the editable gate array chip.
In a second aspect, an embodiment of the present application provides a power-on starting circuit, including: the device comprises a controller, an image enhancement chip, and a signal receiving module, a signal analyzing module and a detection module which are respectively and electrically connected with the controller; the image enhancement chip is respectively and electrically connected with the signal receiving module and the signal detection module, and the signal receiving module is electrically connected with the signal analysis module;
the detection module is used for receiving a first time sequence signal of the M frames of images output by the image enhancement chip; if the first timing signal of the N frames of images in the first timing signals of the M frames of images is the same as a first preset value, sending a first message to the controller, wherein the first message is used for indicating that the signal receiving module and the signal analyzing module are reset;
the controller is used for controlling the signal receiving module and the signal analyzing module to reset according to the first message.
In a possible implementation manner of the second aspect, the detection module is further configured to determine whether a second timing signal output by the signal analysis module is the same as a second preset value if the first timing signal of the P-frame image is the same as the first preset value in the first timing signals of the M-frame images, and if not, send a first message to the controller; wherein, the P is larger than the N, and the second time sequence signal is the time sequence signal of the M +1 frame image output by the image enhancement chip;
the controller is used for controlling the signal receiving module and the signal analyzing module to reset according to the first message.
In another possible implementation manner of the second aspect, the power-on starting circuit further includes a main control chip, an image processing module, a signal encoding module and a sending module, which are respectively electrically connected to the controller, wherein the image processing module, the signal encoding module and the sending module are sequentially electrically connected, the image processing module is connected to the signal analyzing module, and the sending module is connected to the display screen;
the detection module is further configured to send a second message to the controller if the second timing signal is the same as the second preset value;
the controller is further used for controlling the image processing module, the signal encoding module and the sending module to perform de-resetting according to the second message;
the detection module is further configured to determine whether a feedback signal output by the display screen is equal to a third preset value, and if not, send a third message to the controller, where the third message is used to instruct to reset the signal encoding module and the sending module;
the controller is further configured to control the signal encoding module and the sending module to reset according to the third message;
the detection module is further configured to send a preparation signal to a main control chip if the feedback signal output by the display screen is equal to a third preset value, so that the main control chip sends a display signal.
In another possible implementation manner of the second aspect, the controller is further configured to control the signal receiving module and the signal analyzing module to perform initial solution resetting.
In another possible implementation manner of the second aspect, the detection module is further configured to determine whether a response signal output by the signal analysis module is equal to a fourth preset value; if not, the detection module sends the first message to the controller,
the controller is further configured to control the signal receiving module and the signal analyzing module to reset according to the first message;
the detection module is further configured to receive a first timing signal of the M-frame image output by the image enhancement chip if the response signal output by the signal analysis module is equal to a fourth preset value.
In another possible implementation manner of the second aspect, the controller is specifically configured to control resetting of the receiving module and the signal analyzing module after a preset time period.
In another possible implementation manner of the second aspect, the signal receiving module, the signal analyzing module, the image processing module, the signal encoding module, and the sending module are all disposed on an editable gate array chip.
In another possible implementation manner of the second aspect, the SOC chip, the image enhancement chip, and the editable gate array chip are sequentially powered on and started.
In another possible implementation manner of the second aspect, the detection module is disposed on the editable gate array chip.
In a third aspect, an embodiment of the present application provides a display, which includes a display screen and the power-on starting circuit of the second aspect, where the display screen is electrically connected to the power-on starting circuit.
In a fourth aspect, an embodiment of the present application provides a computer storage medium, where a computer program is stored in the storage medium, and the computer program, when executed, implements the boot method according to any one of the first aspect.
According to the startup method and the startup circuit provided by the embodiment of the application, a detection module is used for receiving a first time sequence signal of an M-frame image output by an image enhancement chip; if the first sequence signal of the N frames of images in the first sequence signals of the M frames of images is the same as the first preset value, the detection module sends a first message to the controller, so that the controller controls the receiving module and the signal analysis module to reset according to the first message. This embodiment is based on the first time sequence signal of the inside output of image enhancement chip promptly, can accurately determine whether the signal of image enhancement chip output is stable, and then realize the accurate detection to the front end signal, and when detecting that the front end signal is stable, restart signal reception module and signal analysis module, on realizing that signal reception module and signal analysis module export the stable signal of front end output to the display screen, and then avoid the problem of the display screen flower screen or black screen that causes because the signal of front end output is unstable.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
Fig. 1 is a flowchart of a boot method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a power-on circuit according to an embodiment of the present invention;
fig. 3 is a flowchart of a boot method according to a second embodiment of the present application;
FIG. 4 is a schematic diagram of a power-on start-up circuit according to a second embodiment of the present invention;
fig. 5 is a flowchart of a startup method according to a third embodiment of the present application;
fig. 6 is a schematic diagram of a display provided in an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
According to the technical scheme, when the computer is started, the time sequence signal output by the image enhancement chip is detected, whether the signal of the front end of the starting circuit is stable or not is determined according to the detection result, the detection accuracy is improved, the problem that the display screen is black or is colored when the computer is started is avoided, and the stable operation of the starting process is ensured.
The technical solution of the present application will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Fig. 1 is a flowchart of a boot method according to an embodiment of the present application, and fig. 2 is a schematic diagram of a boot circuit according to the embodiment. As shown in fig. 1 and fig. 2, the method of the present embodiment may include:
s101, a detection module receives a first time sequence signal of the M frames of images output by the image enhancement chip.
And S102, if the first timing signal of the N frames of images in the first timing signals of the M frames of images is the same as a first preset value, the detection module sends a first message to the controller.
Wherein the first message is used for indicating that the signal receiving module and the signal analyzing module are reset.
S103, the controller controls the signal receiving module and the signal analyzing module to reset according to the first message.
The power-on start-up circuit and the display screen of the embodiment form a display.
As shown in fig. 2, the power-on start-up circuit of the present embodiment includes a controller, an image enhancement chip, a signal receiving module, a signal analyzing module and a detecting module. Wherein the signal receiving module (GTP _ RX), the signal parsing module (RX _ CTR) and the detecting module (Timing _ Detect) may be hardware, software or a combination of hardware and software. The modules may be arranged on the same hardware chip, for example, on an FPGA. Optionally, the modules may also be separately arranged on different hardware chips, and the present embodiment does not limit the arrangement manner of the modules, and is specifically determined according to actual needs.
The image enhancement chip is electrically connected with the signal receiving module and the detection module respectively, and the signal analysis module is electrically connected with the signal receiving module.
The timing signals of the present embodiment may include a line sync signal (HS), a field sync signal (VS), and an active display data strobe signal (DE).
In the display, the HS is used for selecting an effective line signal interval on the display screen. VS is used for selecting the effective field signal interval on the display screen, and HS and VS are used together for selecting the effective video signal interval on the display screen.
Since the video signals inputted to the liquid crystal display, effective video signals (effective RGB signals) occupy only a part of the signal period, and the line blanking and field blanking periods of the signals do not contain effective video data. Therefore, when processing a video signal, the relevant circuits in the display must distinguish between a section containing a valid video signal and a blanking section containing no valid video signal. In order to distinguish between valid and invalid video signals, DE is provided in the display circuit.
The image enhancement chip of the present embodiment is used for image enhancement and frame rate conversion.
Optionally, the image enhancement chip of this embodiment may be an FRC chip, a TCON chip, or other types of image enhancement chips, which is not limited in this embodiment and is determined according to actual needs.
In the present embodiment, the image enhancement chip is taken as an FRC chip as an example, and other types of image enhancement chips may be referred to.
As shown in fig. 2, there are 3 first timing (timing) signals between the image enhancement chip and the detection module in this embodiment, which are HS, VS and DE respectively. For convenience of explanation, the 3 signals are denoted as Frc _ hs, Frc _ vs, and Frc _ de, respectively.
In the power-on start-up circuit of the embodiment, the detection module receives the first timing signal of the M-frame image output by the image enhancement chip when the power-on start-up circuit is started up. Then, the first timing signal of each frame of image in the received first timing signals of the M frames of images is compared with a first preset value, and whether the first timing signal of each frame of image is the same as the first preset value is judged. For example, whether the first timing signal of the 2 nd frame image is the same as the first preset value is determined, and if so, the first timing signal of the 2 nd frame image is determined to be correct.
Referring to the above example, the first timing signal of each of the M frames of images is compared with a first predetermined value. If the first timing signal of the N frames of images in the first timing signals of the M frames of images is the same as the first preset value, it is determined that the front-end signal (i.e., the first timing signal output by the image enhancement chip) at the current moment is stable, and it is determined that the signal receiving module and the signal analyzing module can be reset at this moment, so that the reset signal receiving module and the reset signal analyzing module receive the stable signal output by the front end (i.e., the image enhancement chip).
The first time sequence signal of this embodiment is the time sequence signal of image enhancement chip internal output, can accurately determine whether the signal of image enhancement chip output is stable like this based on first time sequence signal, and then realize the accurate detection to the front end signal. And then when detecting the front end signal is stable, restarting the signal receiving module and the signal analysis module to realize that the signal receiving module and the signal analysis module output the stable signal output by the front end to the display screen, and further avoiding the problem of screen splash or screen blackness of the display screen caused by the unstable signal output by the front end.
The detection module of this embodiment determines that the signal receiving module and the signal analyzing module need to be reset, and the specific process of resetting is implemented by the controller.
For example, as shown in fig. 2, the power-on start circuit of this embodiment further includes a controller and a reset module, where the controller is electrically connected to the detection module and the reset module respectively, and the reset module is electrically connected to the signal receiving module and the signal analyzing module respectively.
At this time, the resetting process of the signal receiving module and the signal analyzing module is that when the detecting module detects that the signal receiving module and the signal analyzing module need to be reset, a first message, for example, an int signal, is sent to the controller. And after receiving the first message, the controller analyzes the first message and controls the reset module according to the first message so that the reset module resets the signal receiving module and the signal analysis module.
According to the startup method provided by the embodiment of the application, a detection module is used for receiving a first time sequence signal of an M-frame image output by an image enhancement chip; if the first sequence signal of the N frames of images in the first sequence signals of the M frames of images is the same as the first preset value, the detection module sends a first message to the controller, so that the controller controls the receiving module and the signal analysis module to reset according to the first message. This embodiment is based on the first time sequence signal of the inside output of image enhancement chip promptly, can accurately determine whether the signal of image enhancement chip output is stable, and then realize the accurate detection to the front end signal, and when detecting that the front end signal is stable, restart signal reception module and signal analysis module, on realizing that signal reception module and signal analysis module export the stable signal of front end output to the display screen, and then avoid the problem of the display screen flower screen or black screen that causes because the signal of front end output is unstable.
Fig. 3 is a flowchart of a boot method according to a second embodiment of the present application, and fig. 4 is a schematic diagram of a boot circuit according to the second embodiment. On the basis of the above embodiment, the method of this embodiment further includes:
s301, if the first timing signal of the P frame image in the first timing signals of the M frame images is the same as the first preset value, the detection module determines whether the second timing signal output by the signal analysis module is the same as the second preset value, if not, S302 is executed, and if so, S303 is executed.
And the P is greater than the N, and the second time sequence signal is the time sequence signal of the M +1 frame image output by the image enhancement chip.
S302, the detection module sends a first message to the controller, so that the controller controls the signal receiving module and the signal analyzing module to reset according to the first message.
And S303, the detection module sends a second message to the controller, so that the controller controls the image processing module, the signal coding module and the sending module to perform resetting according to the second message.
S304, the detecting module determines whether the feedback signal output by the display screen is equal to a third preset value, if not, executes S305, and if so, executes S306.
S305, the detection module sends a third message to the controller, so that the controller controls the signal coding module and the sending module to reset according to the third message.
Wherein the third message is used to instruct resetting of the signal encoding module and the transmitting module.
S306, the detection module sends a preparation signal to the main control chip so that the main control chip sends a display signal.
As shown in fig. 4, the power-on start-up circuit of the present embodiment further includes a main control chip (e.g., SOC), an image processing module, a signal encoding module, and a transmitting module.
The image processing module, the signal coding module and the sending module are all electrically connected with the resetting module. The display screen is electrically connected with the detection module. The detection module may receive a feedback signal (e.g., tx _ lockn) sent by the display screen. The controller is electrically connected with the main control chip, for example, the controller is connected with the main control chip through I2C bus communication. The detection module is connected with the signal analysis module and can receive the signal output by the signal analysis module.
As shown in fig. 4, in practical use, the detection module receives a first timing signal of an M-frame image output by the image enhancement chip, and if the first timing signal of a P-frame image in the timing signals of the M-frame image is the same as a first preset value, determines whether a second timing signal output by the signal analysis module is the same as a second preset value. The second time sequence signal is the time sequence signal of the M +1 frame image output by the image enhancement chip. Namely, the detection module resets the signal receiving module and the signal analysis module when detecting that the time sequence signals of N frames of images in the images output by the image enhancement chip are the same as the first preset value. And then, continuously detecting the image output by the image enhancement chip, and when the M frame is reached, detecting that the first timing signal of the P frame image output by the image enhancement chip is the same as the first preset value, and at the moment, determining that the signal output by the front end is stable and resetting the signal receiving module and the signal analyzing module. At this time, in order to further improve the detection accuracy, the timing signal of the M +1 th frame image output by the image enhancement chip is determined.
Specifically, whether the second timing signal output by the signal analysis module is the same as the second preset value is detected. If the second timing signal is different from the second preset value, the front-end signal is determined to be unstable, and the signal receiving module and the signal analyzing module need to be reset again. And then, sending a first message to the controller so that the controller controls the signal receiving module and the signal analyzing module to reset again according to the first message.
And if the second time sequence signal is the same as the second preset value, determining that the time sequence signal of the M +1 frame image output by the image enhancement chip is stable, namely the front end is stable. At this time, a second message is sent to the controller, so that the controller controls the image processing module, the signal coding module and the sending module to perform de-resetting according to the second message, so that the signal output by the image enhancement chip can be transmitted to the display screen through the image processing module, the signal coding module and the sending module. And determining whether the signal coding module and the sending module at the rear end stabilize the voltage according to the feedback signal sent by the display screen. Optionally, the second preset value may be the same as the first preset value.
That is, the display screen sends a feedback signal (e.g., tx _ lockn signal) to the detection module after receiving the signal. The detection module receives a tx _ lockn signal sent by the display screen, compares the tx _ lockn signal with a third preset value, and determines the voltage stabilization of the front-end signal and the rear-end signal if the tx _ lockn signal is the same as the third preset value. Then, the detection module sends a ready signal to the main control chip through the controller. And after receiving the ready signal, the main control chip sends display signals such as LOGO and the like to realize normal display of the image.
If the detection module detects that the tx _ lockn signal sent by the display screen is different from the third preset value, the instability of the rear-end signal is determined, and the signal coding module and the signal sending module at the rear end need to be reset, so that the signal sent by the rear end is stable. Specifically, the detection module sends a third message to the controller, and the controller controls the signal encoding module and the sending module to reset according to the third message.
Optionally, the step S302 may further include:
the controller is used for controlling the receiving module and the signal analysis module to be reset after a preset time period.
If the signal receiving module and the signal analyzing module are reset immediately, the timing signal analyzed by the signal analyzing module still has errors. Therefore, a corresponding delay may be performed before the reset, and a certain delay time may give enough preparation time for the front-end signal to stabilize.
According to the embodiment, through multi-stage detection, whether the signals of the front end and the rear end are stabilized or not can be accurately judged, and after the signals of the front end and the rear end are determined to be stable, the main control chip is controlled to send the display signals, so that the problem that display faults such as a screen splash or a screen blackout are caused by sending the display signals when the signals of the front end module or the rear end module are unstable in the starting circuit is avoided, and the stability of starting display of the display screen is improved.
Fig. 5 is a flowchart of a boot method according to a third embodiment of the present application, where on the basis of the third embodiment, the method according to this embodiment may include:
s501, electrifying the editable gate array chip.
S502, the controller controls the signal receiving module and the signal analyzing module to perform initial solution and reset.
Optionally, the signal receiving module, the signal analyzing module, the image processing module, the signal encoding module, and the sending module of this embodiment are all disposed on an editable gate array chip (e.g., FPGA).
Optionally, the detection module is also disposed on the editable gate array chip. Since the processing speed of the editable gate array chip is faster than that of the controller, the present embodiment can increase the processing speed of the detection module compared to the case where the detection module is provided on the controller.
And after the FPGA is electrified, loading the netlist and initializing each parameter.
Then, the controller controls the signal receiving module and the signal analyzing module to perform de-resetting, so that the signal receiving module and the signal analyzing module can receive signals output by the image enhancement chip.
Optionally, in this embodiment, the main control chip (e.g., SOC), the image enhancement chip (e.g., FRC), and the editable gate array chip (e.g., FPGA) are sequentially powered on and started. Specifically, the SOC is powered on firstly, then the FRC is controlled to be powered on, and finally the FPGA is powered on. The SOC is used as a main control chip and is firstly electrified, and after the SOC is electrified and enters a working state, the FRC chip and the FPGA chip are sequentially electrified. The SOC needs the longest time to enter the working state, and the FPGA needs the shortest time. Compared with the traditional power-on mode, the power-on starting sequence can ensure that the front-end chips start to work when the FPGA starts to work.
S503, the detecting module determines whether the response signal output by the signal analyzing module is equal to a fourth preset value, if not, S504 is executed, and if so, S505 is executed.
S504, sending a first message to a controller so that the controller controls the signal receiving module and the signal analyzing module to reset according to the first message;
s505, the detection module receives a first time sequence signal of the image output by the image enhancement chip.
With continued reference to the power-on start-up circuit shown in fig. 4, the image enhancement chip is electrically connected to the signal analysis module.
After the FPGA is electrified, the netlist file is loaded, and the configuration of the parameters is completed after the loading. And entering a working state after configuration. And the signal receiving module and the signal analyzing module are sequentially reset, the default front-end clock is stable at the moment, and the front end can send stable data. The detection module detects the response signal (e.g., rx _ lockn signal) analyzed by the signal analysis module. If rx _ lockn is high, it represents either unstable front-end clock or decoding error. The signal receiving module and the signal analyzing module need to be reset for judging again. rx _ lockn is low indicating that the clock signal of the front-end has stabilized and the front-end can send a normal timing signal.
S506, the detecting module determines whether the first timing signal of the P-frame image in the received first timing signals of the images is the same as the first preset value, if not, performs S507, and if so, performs S508.
S507, the detection module judges whether the first time sequence signal of the N frames of images in the received first time sequence signals of the images is the same as the first preset value, if so, S504 is executed, and if not, S505 is returned to.
Then, the detection module detects whether the first timing signal output by the image enhancement chip is the same as a first preset value, and if so, the first timing signal of the frame image is determined to be correct.
Referring to the method, it is determined whether a first timing signal of a P frame picture is the same as a first preset value among first timing signals of received pictures (e.g., M frame pictures). If not, whether the first timing signal of the N frames of images in the received first timing signal of the image (for example, the M frames of images) is the same as the first preset value is judged, and if the first timing signal of the N frames of images in the received first timing signal of the M frames of images is the same as the first preset value, the front-end signal is determined to be stable at the moment, and the signal receiving module and the signal analyzing module can be reset. Wherein P and N are positive integers, and P is greater than N.
If the number of the images with the same number as the first preset value in the first timing signal of the image received by the detection module is less than N frames, the detection module continues to receive the first timing signal of the image output by the image enhancement chip and performs the above-mentioned determinations in S506 and S507 until the detection module determines that the first timing signal of the P-frame (or N-frame) image in the received image is the same as the first preset value.
S508, the detecting module determines whether the second timing signal output by the signal analyzing module is the same as a second preset value, if not, then S504 is executed, and if so, then S509 is executed.
S509, the detection module sends a second message to the controller, so that the controller controls the image processing module, the signal coding module and the sending module to perform resetting according to the second message.
S510, the detection module judges whether a feedback signal output by the display screen is equal to a third preset value or not, if not, S511 is executed, and if yes, S512 is executed.
S511, the detection module sends a third message to the controller, so that the controller controls the signal coding module and the sending module to reset according to the third message.
S512, the detection module sends a preparation signal to the main control chip so that the main control chip sends a display signal.
The above-mentioned S508 to S512 are the same as the description of the above-mentioned embodiments, and are not repeated herein with reference to the above-mentioned embodiments.
According to the startup method provided by the embodiment of the application, after the signal receiving module and the signal analyzing module are reset, whether the rx _ lockn signal analyzed by the signal analyzing module is correct or not is judged, and when the rx _ lockn signal is correct, the first timing signal output by the image enhancement chip is detected. And after the first time sequence signal output by the image enhancement chip is detected to pass, detecting whether the second time sequence signal analyzed by the signal analysis module is correct. If the detection result is correct, the image processing module, the signal coding module and the signal sending module are reset, whether the feedback signal of the display screen is correct is detected, and if the feedback signal of the display screen is correct, the SOC is controlled to send the display signal, so that the detection accuracy of whether the display starting signal is stable is improved through 4 layers of detection, and the starting display stability of the display is further improved.
Fig. 2 and fig. 4 are specifically shown, wherein the startup circuit of this embodiment is used for implementing the method, and the implementation principle and technical effect thereof are similar, and are not described herein again.
Fig. 6 is a schematic diagram of a display provided in the present embodiment, and as shown in fig. 6, the display of the present embodiment includes a display screen 61 and a power-on start circuit 62 shown in fig. 2 or fig. 4.
Further, when at least a part of the functions of the boot method in the embodiment of the present application are implemented by software, the embodiment of the present application further provides a computer storage medium, where the computer storage medium is used to store computer software instructions for the boot, and when the computer storage medium runs on a computer, the computer can execute various possible boot methods in the embodiment of the method. The processes or functions described in accordance with the embodiments of the present application may be generated in whole or in part when the computer-executable instructions are loaded and executed on a computer. The computer instructions may be stored on a computer storage medium or transmitted from one computer storage medium to another via wireless (e.g., cellular, infrared, short-range wireless, microwave, etc.) to another website site, computer, server, or data center. The computer storage media may be any available media that can be accessed by a computer or a data storage device, such as a server, data center, etc., that incorporates one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., SSD), among others.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (20)
1. A startup method is characterized in that the method is suitable for a startup circuit, the startup circuit comprises an image enhancement chip, a signal receiving module, a signal analyzing module, a detecting module and a controller, and the method comprises the following steps:
the detection module receives a first time sequence signal of the M frames of images output by the image enhancement chip;
if the first timing signal of the N frames of images in the first timing signals of the M frames of images is the same as the first preset value, the detection module sends a first message to the controller, so that the controller controls the signal receiving module and the signal analyzing module to reset according to the first message, wherein N is smaller than M, and the first message is used for indicating to reset the signal receiving module and the signal analyzing module.
2. The method of claim 1, wherein after resetting the signal receiving module and the signal parsing module, the method further comprises:
if the first timing signal of the P frame image in the first timing signals of the M frame images is the same as a first preset value, the detection module determines whether a second timing signal output by the signal analysis module is the same as a second preset value, where P is greater than N, and the second timing signal is a timing signal of an M +1 th frame image output by the image enhancement chip;
if not, sending a first message to the controller so that the controller controls the signal receiving module and the signal analyzing module to reset according to the first message.
3. The method of claim 2, further comprising:
if the second timing signal is the same as the second preset value, the detection module sends a second message to the controller so that the image processing module, the signal coding module and the sending module perform de-resetting;
the detection module judges whether a feedback signal output by the display screen is equal to a third preset value or not;
if not, the detection module sends a third message to the controller, so that the controller controls the signal coding module and the sending module to reset according to the third message, wherein the third message is used for indicating that the signal coding module and the sending module are reset;
and if so, the detection module sends a preparation signal to a main control chip so that the main control chip sends a display signal.
4. The method according to any one of claims 1-3, wherein before the detection module receives the first timing signal of the M frames of images output by the image enhancement chip, the method further comprises:
the controller controls the signal receiving module and the signal analyzing module to perform initial solution and reset.
5. The method of claim 3, wherein after the controller controls the signal encoding module and the sending module to reset according to the third message, the method further comprises:
the detection module judges whether the response signal output by the signal analysis module is equal to a fourth preset value or not;
if not, the detection module sends the first message to the controller, so that the controller controls the signal receiving module and the signal analyzing module to reset according to the first message;
and if so, the detection module receives a first time sequence signal of the M frames of images output by the image enhancement chip.
6. The method of claim 1, wherein the controller controls the signal receiving module and the signal analyzing module to reset according to the first message, and comprises:
the controller controls the receiving module and the signal analysis module to be reset after a preset time period.
7. The method of claim 3, wherein the signal receiving module, the signal parsing module, the image processing module, the signal encoding module, and the transmitting module are all disposed on an editable gate array chip.
8. The method of claim 7, wherein the main control chip, the image enhancement chip and the editable gate array chip are sequentially powered on.
9. The method of claim 7, wherein the detection module is disposed on the editable gate array chip.
10. A power-on start-up circuit, comprising: the device comprises a controller, an image enhancement chip, and a signal receiving module, a signal analyzing module and a detection module which are respectively and electrically connected with the controller; the image enhancement chip is respectively and electrically connected with the signal receiving module and the detection module, and the signal receiving module is electrically connected with the signal analysis module;
the detection module is used for receiving a first time sequence signal of the M frames of images output by the image enhancement chip; if the first timing signal of N frames of images in the first timing signals of M frames of images is the same as a first preset value, sending a first message to the controller, wherein N is smaller than M, and the first message is used for indicating that the signal receiving module and the signal analyzing module are reset;
the controller is used for controlling the signal receiving module and the signal analyzing module to reset according to the first message.
11. The circuit according to claim 10, wherein the detection module is further configured to, after resetting the signal receiving module and the signal analyzing module, determine whether a second timing signal output by the signal analyzing module is the same as a second preset value if a first timing signal of a P-frame image in the first timing signals of the M-frame images is the same as the first preset value, and if not, send a first message to the controller; wherein, the P is larger than the N, and the second time sequence signal is the time sequence signal of the M +1 frame image output by the image enhancement chip;
the controller is used for controlling the signal receiving module and the signal analyzing module to reset according to the first message.
12. The circuit of claim 11, wherein the power-on start-up circuit further comprises a main control chip, an image processing module, a signal encoding module and a sending module electrically connected to the controller, respectively, the image processing module, the signal encoding module and the sending module are electrically connected in sequence, the image processing module is connected to the signal analyzing module, and the sending module is connected to a display screen;
the detection module is further configured to send a second message to the controller if the second timing signal is the same as the second preset value;
the controller is further used for controlling the image processing module, the signal encoding module and the sending module to perform de-resetting according to the second message;
the detection module is further configured to determine whether a feedback signal output by the display screen is equal to a third preset value, and if not, send a third message to the controller, where the third message is used to instruct to reset the signal encoding module and the sending module;
the controller is further configured to control the signal encoding module and the sending module to reset according to the third message;
the detection module is further configured to send a preparation signal to a main control chip if the feedback signal output by the display screen is equal to a third preset value, so that the main control chip sends a display signal.
13. The circuit according to any one of claims 10-12,
the controller is further configured to control the signal receiving module and the signal analyzing module to perform initial solution and reset.
14. The circuit of claim 13,
the detection module is further used for judging whether the response signal output by the signal analysis module is equal to a fourth preset value or not; if not, the detection module sends the first message to the controller,
the controller is further configured to control the signal receiving module and the signal analyzing module to reset according to the first message;
the detection module is further configured to receive a first timing signal of the M-frame image output by the image enhancement chip if the response signal output by the signal analysis module is equal to a fourth preset value.
15. The circuit of claim 10,
the controller is specifically configured to control resetting of the receiving module and the signal analyzing module after a preset time period.
16. The circuit of claim 12, wherein the signal receiving module, the signal parsing module, the image processing module, the signal encoding module, and the transmitting module are all disposed on an editable gate array chip.
17. The circuit of claim 16, wherein the main control chip, the image enhancement chip, and the editable gate array chip are powered on in sequence.
18. The circuit of claim 16, wherein the detection module is disposed on the editable gate array chip.
19. A display comprising a display screen and the power-on startup circuit of any of claims 10-18, the display screen being electrically connected to the power-on startup circuit.
20. A computer storage medium, in which a computer program is stored, which computer program, when executed, implements a power-on startup method according to any one of claims 1-9.
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| CN112785985B (en) * | 2019-11-04 | 2022-03-11 | 海信视像科技股份有限公司 | Display device |
| CN111935478A (en) * | 2020-07-27 | 2020-11-13 | 广州汽车集团股份有限公司 | Detection method, display method and device for video signal of vehicle-mounted separation screen |
| CN113593461A (en) * | 2021-07-19 | 2021-11-02 | 深圳市华星光电半导体显示技术有限公司 | Display panel and driving method thereof |
| CN113674704A (en) * | 2021-08-17 | 2021-11-19 | 青岛信芯微电子科技股份有限公司 | Image display control method and device and display equipment |
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