CN109117301A - A kind of method that subregion is arranged using error correction code check configurable functionality for random memory - Google Patents
A kind of method that subregion is arranged using error correction code check configurable functionality for random memory Download PDFInfo
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- CN109117301A CN109117301A CN201810806774.1A CN201810806774A CN109117301A CN 109117301 A CN109117301 A CN 109117301A CN 201810806774 A CN201810806774 A CN 201810806774A CN 109117301 A CN109117301 A CN 109117301A
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- Prior art keywords
- memory
- memory storage
- unit
- subregion
- data
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
Abstract
The invention discloses a kind of random memories to use the method for error correction code check configurable functionality setting subregion, including main control chip, memory storage control module and Memory control physical layer are equipped in main control chip, writing unit and reading unit are equipped in memory storage control module, writing unit and reading unit are separately connected Memory control physical layer, Memory control physical layer connects multiple memory storage elements, the present invention uses a kind of zone configuration scheme, allow each subregion that can distinguish enable or using different check mode or data and check bit ratio, when allowing a small amount of random data and a large amount of blocky data to be written with respective subregion is read, all using individual different settings and process, reach whole best efficiency and space utilization rate.
Description
Technical field
The present invention relates to memory techniques field, specially a kind of random memory is arranged using error correction code check configurable functionality
The method of subregion.
Background technique
Memory is one of the ost important components in computer, it is the bridge linked up with CPU.All programs in computer
Operation all carry out in memory, therefore influence of the performance of memory to computer is very big.Memory is also referred to as memory
Reservoir, effect is for temporarily storing the operational data in CPU, and the data exchanged with external memories such as hard disks.Only
Want computer in operation, CPU will be transferred to the data for needing operation in memory and carry out operation, and CPU is again after the completion of operation
Result is sent out, the operation of memory also determines the stable operation of computer.Memory is by memory chip, circuit board, gold
The part such as finger composition.
Existing memory control system does verification data protection to random memory, this verification protected mode is not configured subregion and sets
It sets, for a small amount of random data and a large amount of blocky data, or the user data of different attribute, all using same protection
Configuration, this limitation cause between a small amount of random data and a large amount of blocky data, or between the user data of different attribute,
The optimization of most effective transmission and minimum check bit use space can not be reached simultaneously.
Summary of the invention
The purpose of the present invention is to provide a kind of random memories to use the side of error correction code check configurable functionality setting subregion
Method, to solve the problems mentioned in the above background technology.
To achieve the above object, the invention provides the following technical scheme: a kind of random memory can be matched using error correction code check
The method for setting function setting subregion, including main control chip, the main control chip is interior to be equipped with memory storage control module and memory control
Physical layer processed, the memory storage control module is interior to be equipped with writing unit and reading unit, said write unit and reading unit
It is separately connected Memory control physical layer, the Memory control physical layer connects multiple memory storage elements；Multiple memory storage groups
Part includes the first memory storage elements, the second memory storage elements, third memory storage elements, N memory storage elements, and N is
Integer greater than 3.
It preferably, further include that check bit generates unit and verification inspection unit, the check bit generates unit and verification inspection
Verification certificate member is arranged in memory storage control module, and the check bit generates unit and connects writing unit；The verification checks
Unit connects reading unit.
Preferably, a kind of random memory includes following step using the method for error correction code check configurable functionality setting subregion
It is rapid:
A, different configurations are done to heterogeneity user's data first, is generated using different enable settings or operation process different
Verification check bit,；
B, check bit and data are deposited into random external memory headroom simultaneously in a manner of additional or be configured to another block；
C, when reading, user data and check bit data are read simultaneously, verifies operation in carrying out user data in correction verification module.
Compared with prior art, it the beneficial effects of the present invention are: the present invention uses a kind of zone configuration scheme, allows each
Subregion can distinguish enable or using different check mode or data and check bit ratio, allow a small amount of random data and big gauge block
When the write-in of shape data is with respective subregion is read, all using individual different settings and process, reach whole best effective
It can be with space utilization rate.
Detailed description of the invention
Fig. 1 is the random memory control unit schematic diagram inside a master control of the invention；
Fig. 2 is the random memory control unit inside master control of the present invention, configures additional check bit storage and is illustrated with memory subassembly
Figure；
Fig. 3 is that the present invention does not configure additional check bit storage memory subassembly schematic diagram；
Fig. 4 is to do subregion for different attribute user data in random memory control unit of the present invention schematic diagram is arranged；
Fig. 5 is to do subregion for different attribute user data in random memory control unit of the present invention another schematic diagram is arranged.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Please refer to Fig. 1-5, the present invention provides a kind of technical solution: a kind of random memory can configure function using error correction code check
The method of subregion, including main control chip 1 can be set, are equipped with memory storage control module 2 and Memory control in the main control chip 1
Physical layer 3, the memory storage control module 2 is interior to be equipped with writing unit 4 and reading unit 5, and said write unit 4 and reading are single
Member 5 is separately connected Memory control physical layer 3, and the Memory control physical layer 3 connects multiple memory storage elements；Multiple interior storages
Depositing component includes the first memory storage elements 6, the second memory storage elements 7, third memory storage elements 8, N memory storage group
Part, N are the integer greater than 3；It further include that check bit generates unit 9 and verification inspection unit 10, the check bit generates 9 He of unit
Verification inspection unit 10 is arranged in memory storage control module 2, and the check bit generates unit 9 and connects writing unit 4；Institute
It states verification inspection unit 10 and connects reading unit 5.
In the present invention, a kind of method that subregion is arranged using error correction code check configurable functionality for random memory, including it is following
Step:
A, different configurations are done to heterogeneity user's data first, is generated using different enable settings or operation process different
Verification check bit,；
B, check bit and data are deposited into random external memory headroom simultaneously in a manner of additional or be configured to another block；
C, when reading, user data and check bit data are read simultaneously, verifies operation in carrying out user data in correction verification module.
In conclusion the present invention uses a kind of zone configuration scheme, allow each subregion that can distinguish enable or using different
Verification mode or data and check bit ratio allow a small amount of random data and a large amount of blocky data to be written and read respective subregion
When, all using individual different settings and process, reach whole best efficiency and space utilization rate.
It although an embodiment of the present invention has been shown and described, for the ordinary skill in the art, can be with
A variety of variations, modification, replacement can be carried out to these embodiments without departing from the principles and spirit of the present invention by understanding
And modification, the scope of the present invention is defined by the appended.
Claims (3)
1. a kind of random memory uses the method for error correction code check configurable functionality setting subregion, including main control chip 1, feature
It is: is equipped with memory storage control module (2) and Memory control physical layer (3), the memory storage in the main control chip (1)
Writing unit (4) and reading unit (5) are equipped in control module (2), said write unit (4) and reading unit (5) connect respectively
It connects Memory control physical layer (3), the Memory control physical layer (3) connects multiple memory storage elements；Multiple memory storage groups
Part includes the first memory storage elements (6), the second memory storage elements (7), third memory storage elements (8), N memory storage
Component, N are the integer greater than 3.
2. the method that subregion is arranged using error correction code check configurable functionality for a kind of random memory according to claim 1,
Generate unit (9) and verification inspection unit (10) it is characterized by also including check bit, check bit generation unit (9) and
Verification inspection unit (10) is arranged in memory storage control module (2), and it is single that the check bit generates unit (9) connection write-in
First (4)；The verification inspection unit (10) connects reading unit (5).
3. the method that subregion is arranged using error correction code check configurable functionality for a kind of random memory according to claim 1,
It is characterized by comprising following steps:
A, different configurations are done to heterogeneity user's data first, is generated using different enable settings or operation process different
Verification check bit,；
B, check bit and data are deposited into random external memory headroom simultaneously in a manner of additional or be configured to another block；
C, when reading, user data and check bit data are read simultaneously, verifies operation in carrying out user data in correction verification module.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810806774.1A CN109117301A (en) | 2018-07-20 | 2018-07-20 | A kind of method that subregion is arranged using error correction code check configurable functionality for random memory |
| PCT/CN2018/105893 WO2020015134A1 (en) | 2018-07-20 | 2018-09-15 | Method enabling ram to configure partition by using configurable function for error-correction code verification |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810806774.1A CN109117301A (en) | 2018-07-20 | 2018-07-20 | A kind of method that subregion is arranged using error correction code check configurable functionality for random memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109117301A true CN109117301A (en) | 2019-01-01 |
Family
ID=64863266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810806774.1A Pending CN109117301A (en) | 2018-07-20 | 2018-07-20 | A kind of method that subregion is arranged using error correction code check configurable functionality for random memory |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109117301A (en) |
| WO (1) | WO2020015134A1 (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1952869A (en) * | 2005-10-21 | 2007-04-25 | 国际商业机器公司 | Apparatus, system, and method for writing data to protected partitions of storage media |
| CN101552032A (en) * | 2008-12-12 | 2009-10-07 | 深圳市晶凯电子技术有限公司 | Method and device for constructing a high-speed solid state memory disc by using higher-capacity DRAM to join in flash memory medium management |
| CN103744744A (en) * | 2014-02-08 | 2014-04-23 | 威盛电子股份有限公司 | Data storage device and data checking method of volatile storage |
| CN105843700A (en) * | 2016-03-25 | 2016-08-10 | 中国科学院微电子研究所 | Controller |
| CN106847343A (en) * | 2016-12-08 | 2017-06-13 | 上海精密计量测试研究所 | The method of testing of the mram memory based on ATE |
| CN107894898A (en) * | 2017-11-28 | 2018-04-10 | 中科亿海微电子科技（苏州）有限公司 | Refresh device, implementation method and the fpga chip with error correction on SRAM type FPGA pieces |
-
2018
- 2018-07-20 CN CN201810806774.1A patent/CN109117301A/en active Pending
- 2018-09-15 WO PCT/CN2018/105893 patent/WO2020015134A1/en active Application Filing
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1952869A (en) * | 2005-10-21 | 2007-04-25 | 国际商业机器公司 | Apparatus, system, and method for writing data to protected partitions of storage media |
| CN101552032A (en) * | 2008-12-12 | 2009-10-07 | 深圳市晶凯电子技术有限公司 | Method and device for constructing a high-speed solid state memory disc by using higher-capacity DRAM to join in flash memory medium management |
| CN103744744A (en) * | 2014-02-08 | 2014-04-23 | 威盛电子股份有限公司 | Data storage device and data checking method of volatile storage |
| CN105843700A (en) * | 2016-03-25 | 2016-08-10 | 中国科学院微电子研究所 | Controller |
| CN106847343A (en) * | 2016-12-08 | 2017-06-13 | 上海精密计量测试研究所 | The method of testing of the mram memory based on ATE |
| CN107894898A (en) * | 2017-11-28 | 2018-04-10 | 中科亿海微电子科技（苏州）有限公司 | Refresh device, implementation method and the fpga chip with error correction on SRAM type FPGA pieces |
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| Publication number | Publication date |
|---|---|
| WO2020015134A1 (en) | 2020-01-23 |
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Application publication date: 20190101 |
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