CN109116065B - High-frequency jitter filtering test method and device - Google Patents
High-frequency jitter filtering test method and device Download PDFInfo
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Abstract
The invention relates to a test method and a device for high-frequency jitter filtration, wherein the method comprises the steps that a generated pulse signal is converted into a dry node signal through a photoelectric isolation circuit and is output and displayed; an input channel of a system to be tested collects the trunk node signals and then carries out data processing, and the signals after data processing are output through an output channel; and judging whether the signal waveform higher than the specified frequency is filtered according to the comparison between the displayed signal waveform of the trunk node and the output signal waveform after data processing, and if so, determining that the tested system realizes the function of high-frequency jitter filtering. The invention also discloses a device which belongs to the same conception with the method. By the testing method and the testing device, a conventional instrument and a simple photoelectric isolation circuit can be used for realizing the jitter removal function test of the system, and the requirements of high-frequency signal transmission and test result reliability are met.
Description
Technical Field
The invention relates to the field of instrument control system testing, in particular to a testing method and a testing device for high-frequency jitter filtering.
Background
In the existing digital instrument control system, the jitter part in the IO signal acquired on site is filtered by the IO module, so that the system is prevented from generating misoperation due to the fact that the system acquires abnormal jitter signals, and economic loss caused by the fact that normal production is influenced. But in the test process, the problem that the jitter removal capability of the IO module is high due to the existence of partial high-frequency jitter signals, the problem that the test result is unreliable due to the uncontrollable jitter frequency and the large workload of the manual injection signals, and the problem that the used related test instrument is expensive and low in use rate are also existed.
Disclosure of Invention
In view of the foregoing analysis, the present invention aims to provide a method and an apparatus for testing high-frequency jitter filtering, which solve the problems of the prior art that the requirement for jitter removal capability of an IO module is high due to the existence of a part of high-frequency jitter signals during the testing process, and the testing result is unreliable due to uncontrollable jitter frequency, and simultaneously avoid the problems of high use cost and low efficiency of related testing instruments, thereby ensuring high efficiency and reliability of the test.
The purpose of the invention is mainly realized by the following technical scheme:
on one hand, the embodiment of the invention provides a test method for high-frequency jitter filtering, which comprises the steps that a generated pulse signal is converted into a dry node signal through a photoelectric isolation circuit, and the dry node signal is output and displayed; an input channel of a system to be tested collects the trunk node signals and then carries out data processing, and the signals after data processing are output through an output channel; and judging whether the signal waveform higher than the specified frequency is filtered according to the comparison between the displayed signal waveform of the trunk node and the output signal waveform after data processing, and if so, determining that the tested system realizes the function of high-frequency jitter filtering.
In another embodiment based on the method, a pulse signal is generated by a high-frequency signal generating instrument, is displayed by a system output waveform recording instrument after being converted by a photoelectric isolation circuit, and is collected by an input channel of the system to be tested. And after the signals collected by the input channel of the input end of the system to be tested are processed by data of algorithm logic, the signals are output through the output channel of the output end and are displayed by the system output waveform recording instrument. And comparing the signal waveform of the trunk node displayed by the system output waveform recording instrument with the signal waveform output by the output channel, and judging that the signal waveform higher than the specified frequency is filtered if the signal waveform higher than the specified frequency is changed into a straight line. The method further comprises the step of monitoring the jumping times of the acquired signals of the input channel, which are recorded by a counting algorithm in the data processing process through a terminal, wherein the jumping times are consistent with the waveform number of the signals output by the output channel of the system to be tested.
The beneficial effects of the above technical scheme are as follows: the embodiment of the invention discloses a test method for high-frequency jitter filtration, which comprises the steps that a generated pulse signal is converted into a dry node signal through a photoelectric isolation circuit, and the dry node signal is output and displayed; an input channel of a system to be tested collects the trunk node signals and then carries out data processing, and the signals after data processing are output through an output channel; and judging whether the signal waveform higher than the specified frequency is filtered according to the comparison between the displayed signal waveform of the trunk node and the output signal waveform after data processing, and if so, determining that the tested system realizes the function of high-frequency jitter filtering. Compared with the prior art, the embodiment of the invention overcomes the defects of high requirement on the jitter removal capability of an IO module caused by partial high-frequency jitter signals in the system test process and unreliable test results caused by uncontrollable jitter frequency and large workload of manually injected signals aiming at practical engineering application, can be realized by using conventional instruments and meters and common electronic circuits, and solves the problems of high price and low utilization rate of related test instruments used in the prior art. Compared with the prior art, the other embodiment based on the method not only realizes the intuition of the test output result, but also carries out comprehensive judgment through a system output waveform recording instrument and an algorithm counter, thereby ensuring high reliability of the test result.
On the other hand, the embodiment of the invention provides a testing device for high-frequency jitter filtering, which comprises a testing instrument, a photoelectric module and a tested system; the test instrument comprises an instrument used for generating a pulse signal and an instrument used for displaying a dry node signal converted from the pulse signal; the photoelectric module is used for converting the pulse signal into the trunk node signal through a photoelectric isolation circuit; the system to be tested is used for realizing the function of high-frequency jitter filtering, collecting the trunk node signals through an input channel, then performing data processing, and outputting the signals after data processing through an output channel; and the signals after the output data processing are simultaneously displayed and compared by a test instrument for displaying the dry node signals, whether the signal waveforms higher than the specified frequency are filtered is judged, and if so, the tested system realizes the function of high-frequency jitter filtering.
In another embodiment based on the above device, the test instrument comprises a high-frequency signal generating instrument connected to the input end of the optoelectronic module, and a system output waveform recording instrument connected to the output end; the high-frequency signal generating instrument is used for generating pulse signals, and the pulse signals are acquired by an input channel of the system to be tested after being converted by the photoelectric module. The system to be tested comprises a data processing module for arithmetic logic operation, and an input end IO module and an output end IO module which are respectively connected with the data processing module; the system comprises a system input channel, a system output waveform recording instrument, a data processing module and a data processing module, wherein signals acquired by the system input channel are output through an output channel and displayed by the system output waveform recording instrument; the input channel is packaged in the input end IO module and is connected with the output end of the photoelectric isolation circuit; and the output channel is packaged in an output end IO module and is connected with the system output waveform recording instrument. The system output waveform recording instrument is used for simultaneously displaying the signal waveform of the trunk node and the signal waveform output by the output channel; and if the trunk node signal waveform which is higher than the specified frequency is displayed to be changed into a straight line, judging that the signal waveform which is higher than the specified frequency is filtered. The terminal is connected with a counter of the data processing module and displays the jumping times of the signals acquired by the input channel; and the jumping times are recorded by a counter of the data processing module and are consistent with the waveform number of the signal output by the output channel.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, wherein like reference numerals are used to designate like parts throughout.
FIG. 1 is a flowchart of a method for testing high frequency jitter filtering according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a pulse signal generated by a function generator according to an embodiment of the present invention;
FIG. 3 is a block diagram of a test implementation of high frequency jitter filtering according to an embodiment of the present invention;
FIG. 4 is a logic diagram of an internal algorithm of a system under test according to an embodiment of the present invention;
FIG. 5 is a logic diagram of a digital input debounce algorithm according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a system under test according to an embodiment of the present invention.
Detailed Description
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate preferred embodiments of the invention and together with the description, serve to explain the principles of the invention and not to limit the scope of the invention.
According to an embodiment of the present invention, a method for testing high frequency jitter filtering is disclosed, as shown in fig. 1, comprising the following steps:
s101, converting the generated pulse signal into a dry node signal through a photoelectric isolation circuit, and outputting and displaying the dry node signal;
s102, an input channel of a system to be tested collects the trunk node signals and then carries out data processing, and the signals after data processing are output through an output channel;
s103, judging whether the signal waveform higher than the specified frequency is filtered according to the comparison between the displayed signal waveform of the trunk node and the signal waveform after the output data processing, and if so, determining that the tested system realizes the function of high-frequency jitter filtering.
As shown in fig. 1, in the testing method for high-frequency jitter filtering according to the embodiment of the present invention, the generated pulse signal is converted into a dry node signal through the photoelectric isolation circuit, and is output and displayed; an input channel of a system to be tested collects the trunk node signals and then carries out data processing, and the signals after data processing are output through an output channel; and judging whether the signal waveform higher than the specified frequency is filtered according to the comparison between the displayed signal waveform of the trunk node and the output signal waveform after data processing, and if so, determining that the tested system realizes the function of high-frequency jitter filtering. The scheme of the invention solves the problems that the requirement on the jitter removing capability of the IO module is high due to the existence of partial high-frequency jitter signals and the test result is unreliable due to uncontrollable jitter frequency in the test process in the prior art, and simultaneously, the test output result is visual.
It should be noted here that a commonly-used function generator is adopted for generating the pulse signal, but since the function generator generates a pulse signal of 0.1 ms-500 ms/3.3VDC 3.3VDC which does not meet the signal acquisition requirement of the instrument control system, and the commonly-used signal type meeting the acquisition requirement is 24VDC or a dry node signal, the pulse signal is converted into a dry node signal meeting the acquisition requirement through a photoelectric isolation circuit. A schematic diagram of the pulse signal generated by the function generator shown in fig. 2. Taking a specific generated pulse signal as an example, in conjunction with fig. 2, it can be seen that the pulse output period T of the function generator is set to 10ms, and the duty ratio of the pulse signal is 10%, a pulse signal of 1ms is generated per period. The high frequency jitter signal is generally defined as a jitter signal of less than 3ms, that is, when it is determined whether a signal waveform higher than a specified frequency is filtered, the specified frequency is generally a frequency corresponding to the 3ms pulse signal.
After the generated pulse signal passes through the photoelectric isolation circuit, a dry node signal output by the circuit is sent to a test instrument connected with the photoelectric isolation circuit, wherein a waveform display instrument is used. Meanwhile, the output dry node signals are collected by the input channel of the system to be tested and then subjected to data processing of algorithm logic, the signals subjected to data processing are output through the output channel, the signals are sent to a test instrument connected with the output channel of the system to be tested, and the waveforms of the output signals are displayed by using the same waveform display instrument. Therefore, whether the system to be tested filters the designated high-frequency jitter signal or not can be determined by visually checking and comparing two paths of different signal waveforms displayed in the waveform display instrument.
Fig. 3 is a block diagram of a test implementation of high frequency jitter filtering according to an embodiment of the present invention.
In an embodiment of the present invention, referring to fig. 3, a pulse signal is generated by a high frequency signal generating instrument, and is displayed by a system output waveform recording instrument after being converted by a photoelectric isolation circuit, and is simultaneously collected by an input channel of the system under test.
In the implementation of the test, a high-frequency signal generator is used to generate a pulse signal, usually in the form of a function generator. And displaying the signal waveform output by the photoelectric isolation circuit by using a system output waveform recording instrument, namely the signal waveform acquired by the input channel of the tested system. Compared with the prior art, the test can be realized by using the conventional instrument and meter and the common electronic circuit, and the problems of high price and low utilization rate of the related test instrument used in the prior art are solved.
In a specific embodiment of the present invention, after the data processing of the arithmetic logic is performed on the signals collected by the input channel of the input end of the system to be tested, the signals are output through the output channel of the output end and displayed by the system output waveform recording instrument.
As shown in fig. 3, the internal structural composition of the system under test and the processing flow of the collected signals can be known. That is, the input module of the system to be tested converts the collected analog quantity signal into a digital quantity signal, and then sends the digital quantity signal to the data processing module of the arithmetic logic operation through the common communication module, and filters out the high-frequency jitter signal through the arithmetic logic operation.
Fig. 4 shows the logic diagram of the algorithm inside the system under test. With reference to fig. 4, it can be seen that the data processing module receives the digitally quantized acquisition signal and filters out the high frequency jitter signal through an arithmetic logic operation of the jitter removal function. The data processing module is used for processing the acquired data, logical operation is carried out on the actually acquired data through algorithm software of the system, namely, an input channel acquisition value is directly assigned to an output channel for waveform display and jump times recording is carried out by a counting algorithm block. It should be noted that the input channel acquisition value is a value obtained by performing digital quantization on the input module of the system under test and filtering the high-frequency jitter signal.
In an embodiment of the present invention, the waveform of the stem node signal displayed by the system output waveform recording instrument is compared with the waveform of the signal output by the output channel, and if the waveform of the stem node signal higher than the specified frequency becomes a straight line, it is determined that the waveform of the signal higher than the specified frequency is filtered.
In this embodiment, through system output waveform recording instrument visual display the stem node signal waveform with the signal waveform of output channel output, because the signal of output channel output filters through the system input module of being surveyed and is higher than the specified frequency the output behind the stem node signal, if find through the contrast of two kinds of waveforms of visual display and be higher than the specified frequency the stem node signal waveform becomes the invariable straight line of amplitude, then can judge that high frequency jitter signal is filtered to conclude that the system of being surveyed realizes the filterable function of high frequency jitter signal.
Further, in a specific embodiment, the number of transitions of the input channel acquisition signal recorded by a counting algorithm in the process of processing data is monitored by the terminal, and the number of transitions is consistent with the number of signal waveforms output by the output channel of the system under test.
In order to avoid the influence of the system acquisition period on the output module, a counter of the data processing module is used for recording the signal jump times acquired by the actual input end, namely when the input signal jump is acquired, the counter is added with 1, so that whether the system filters out the jitter signal or not can be proved. That is, when the jitter signal input waveform monitored by the oscilloscope and the output channel waveform subjected to the arithmetic logic operation are not affected by the system acquisition period, the number of transitions recorded by the counter monitored by the terminal should be consistent with the number of signal waveforms output by the output channel of the system to be tested.
Fig. 5 shows a logic diagram of a digital quantity input debounce algorithm. The following is an example of a specific application of the requirement of a digital quantity input channel in the harmonic system platform test and 3ms debounce capability.
Firstly, a test environment is set up, a function generator is used for injecting 1 ms-500 ms/3.3VDC signals into the input end of the photoelectric isolation circuit, and a digital quantity input channel of the harmonic system is accessed. And simultaneously, monitoring a jitter signal input waveform and an output channel waveform subjected to arithmetic logic operation by using an oscilloscope. Referring to fig. 5, the collected value and the quality bit of the digital input channel are split by using the algorithm configuration function of the harmonic system, i.e. the digital input debounce algorithm logic, where the collected value is 0 or 1, which represents the amplitude of the signal, and the quality bit is also 0 or 1, which respectively represents the state of the input channel as damaged or normal. And respectively sending the value and the quality bit of the acquired value to an output channel and a counter, checking the results of logical counters of an oscilloscope monitoring algorithm and a computer monitoring algorithm, and judging whether the test is passed or not. That is to say, whether the high-frequency jitter signal is filtered can be visually seen by comparing the input waveform of the oscilloscope monitoring jitter signal with the waveform of the output channel subjected to algorithm operation, and meanwhile, the result of the logic counter of the computer monitoring algorithm is adopted, and the influence of the system acquisition period on the output module is avoided by judging the test according to the consistency of the result and the waveform of the output channel monitored by the oscilloscope, so that whether the test passes or not is judged. Through the test effect, in the execution process, the digital quantity input board card of the judging and harmonious system has a high-frequency jitter removing function.
In an embodiment of the present invention, referring to the test implementation structure shown in fig. 3, a test apparatus for high frequency jitter filtering is provided, the apparatus includes a test instrument, an optoelectronic module, and a system under test; the test instrument comprises an instrument used for generating a pulse signal and an instrument used for displaying a dry node signal converted from the pulse signal; the photoelectric module is used for converting the pulse signal into the trunk node signal through a photoelectric isolation circuit; the system to be tested is used for realizing the function of high-frequency jitter filtering, collecting the trunk node signals through an input channel, then performing data processing, and outputting the signals after data processing through an output channel; and the signals after the output data processing are simultaneously displayed and compared by a test instrument for displaying the dry node signals, whether the signal waveforms higher than the specified frequency are filtered is judged, and if so, the tested system realizes the function of high-frequency jitter filtering.
It should be noted here that the test meter is a conventional meter, and is used for generating a pulse signal at the input end of the system under test, and displaying a dry node signal converted from the pulse signal and a data processed signal at the output end of the system under test. The photoelectric module converts the generated pulse signals into dry node signals, and the common signal type of the system is 24VDC or dry node signals because 1 ms-500 ms/3.3VDC pulse signals do not meet the signal acquisition requirements of the instrument control system. The embodiment of the invention adopts the commonly applied dry node signal. The output end of the photoelectric module is connected to the input module of the tested system so as to facilitate the system to collect signals. In the embodiment of the invention, the conventional instrument and meter and the common electronic circuit are used for realizing the test of the jitter removal function of the tested system, so that the problem of low efficiency due to high use cost of the related test instrument is avoided while the test reliability is ensured.
In one embodiment of the present invention, the test instrument comprises a high-frequency signal generating instrument connected to the input end of the optoelectronic module, and a system output waveform recording instrument connected to the output end; the high-frequency signal generating instrument is used for generating pulse signals, and the pulse signals are acquired by an input channel of the system to be tested after being converted by the photoelectric module.
The high-frequency signal generating device outputs a pulse signal waveform of 0.1ms to 500ms/3.3VDC using a common instrument such as a function generator. The pulse signal waveform is schematically shown in fig. 2. The input end of the photoelectric module is connected with the high-frequency signal generating instrument and transmits the pulse signal to the input channel of the tested system after being converted. The system output waveform recording instrument can use a common oscilloscope (200MHz), and is connected with the output end of the photoelectric module to display the signal waveform converted by the photoelectric module.
Fig. 6 shows a schematic structural diagram of the system under test.
In a specific embodiment of the present invention, as shown in fig. 6, the system under test includes a data processing module for arithmetic logic operation, and an input terminal IO module and an output terminal IO module respectively connected to the data processing module; the system comprises a system input channel, a system output waveform recording instrument, a data processing module and a data processing module, wherein signals acquired by the system input channel are output through an output channel and displayed by the system output waveform recording instrument; the input channel is packaged in the input end IO module and is connected with the output end of the photoelectric isolation circuit; and the output channel is packaged in an output end IO module and is connected with the system output waveform recording instrument. That is to say, the internal structure of the system to be tested mainly comprises a data processing module for arithmetic logic operation, an input end IO module and an output end IO module. The input end IO module converts analog quantity signals collected from the output end of the photoelectric isolation circuit into digital quantity signals, sends the digital quantity signals to the data processing module of arithmetic logic operation through the commonly used communication module, filters out high-frequency jitter signals through the arithmetic logic operation, and outputs the high-frequency jitter signals to the system output waveform recording instrument through the output end IO module.
It should be noted that in a specific application, the input channel is a structural part of a signal acquisition function of the input IO module, and in an actual application, a test instrument is usually inserted into the input channel. The output channel is a structural part for signal output of the output end IO module, and in practical application, a test instrument is usually inserted into the output channel. See fig. 6 for a detailed structure of the system under test in the test apparatus structure. The input channel in the input end IO module is generally used for inserting a test instrument, and is connected with the output end of the photoelectric isolation circuit to play a role of a signal acquisition channel. The output channel in the output terminal IO module is also generally used for inserting a test instrument, and is connected to a system output waveform recording instrument, so as to function as a signal waveform output channel.
In a specific embodiment of the present invention, the present invention further comprises a terminal for monitoring arithmetic logic operation, wherein the terminal is connected to the counter of the data processing module and displays the number of transitions of the signal collected by the input channel; and the jumping times are recorded by a counter of the data processing module and are consistent with the waveform number of the signal output by the output channel. That is, the operation result of the algorithm logic counter is monitored by the terminal, and whether the test is passed or not is comprehensively judged by combining the comparison of the waveforms displayed by the system output waveform recording instrument.
According to the embodiment, on the basis that the test result is visually checked through the oscilloscope, comprehensive judgment is carried out by combining algorithm counting, so that the reliability of the test result is high. When the influence of the system acquisition period is avoided, when the jumping times recorded by the counter are consistent with the signal waveform number output by the output channel, the system test can be judged to realize the jitter removal function.
Through above testing arrangement, can use conventional instrument and simple optoelectronic isolation circuit to realize the function test that removes trembling to the system, satisfy IO high frequency signal transmission and test result credibility requirement.
In summary, the invention discloses a test method and a device for high-frequency jitter filtering, the method comprises the steps that the generated pulse signal is converted into a dry node signal through a photoelectric isolation circuit, and the dry node signal is output and displayed; an input channel of a system to be tested collects the trunk node signals and then carries out data processing, and the signals after data processing are output through an output channel; and judging whether the signal waveform higher than the specified frequency is filtered according to the comparison between the displayed signal waveform of the trunk node and the output signal waveform after data processing, and if so, determining that the tested system realizes the function of high-frequency jitter filtering. The invention solves the problems of high requirement on the jitter removal capability of an IO module caused by partial high-frequency jitter signals in the system test process and unreliable test results caused by uncontrollable jitter frequency and large workload of manually injected signals, can be realized by using conventional instruments and meters and common electronic circuits, and solves the problems of high price and low utilization rate of related test instruments used in the prior art. The invention is applied to the testing of the harmony system of the nuclear security level digital instrument control platform and is used for verifying the test of the debounce function of a digital quantity input channel in the harmony instrument control system. The method and the device of the invention ensure the requirement of the test precision, reduce the purchase investment of instruments and equipment, improve the utilization rate of the existing instruments and have good actual engineering use effect.
Those skilled in the art will appreciate that all or part of the processes for implementing the methods in the above embodiments may be implemented by a computer program, which is stored in a computer-readable storage medium, to instruct associated hardware. The computer readable storage medium is a magnetic disk, an optical disk, a read-only memory or a random access memory.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (6)
1. A test method for high-frequency jitter filtering is characterized by comprising the following steps:
the generated pulse signal is converted into a dry node signal through a photoelectric isolation circuit, and is output and displayed; generating a pulse signal by a high-frequency signal generating instrument, converting the pulse signal by a photoelectric isolation circuit, displaying the pulse signal by a system output waveform recording instrument, and simultaneously acquiring the pulse signal by an input channel of the system to be tested;
an input channel of a system to be tested collects the trunk node signals and then carries out data processing, and the signals after data processing are output through an output channel; after the signals collected by the input channel of the input end of the system to be tested are processed by data of algorithm logic, the signals are output through the output channel of the output end and are displayed by the waveform recording instrument output by the system;
and judging whether the signal waveform higher than the specified frequency is filtered according to the comparison between the displayed signal waveform of the trunk node and the output signal waveform after data processing, and if so, determining that the tested system realizes the function of high-frequency jitter filtering.
2. The method according to claim 1, wherein the stem node signal waveform displayed by the system output waveform recording instrument is compared with the signal waveform output by the output channel, and the stem node signal waveform higher than the specified frequency is changed into a straight line, and then the signal waveform higher than the specified frequency is judged to be filtered.
3. The method of claim 1, further characterized by monitoring, by the terminal, a number of transitions of the input channel acquisition signal recorded by a counting algorithm during data processing, the number of transitions corresponding to a number of signal waveforms output by an output channel of the system under test.
4. A testing device for high-frequency jitter filtering is characterized by comprising a testing instrument, a photoelectric module and a tested system;
the test instrument comprises an instrument used for generating a pulse signal and an instrument used for displaying a dry node signal converted from the pulse signal;
the photoelectric module is used for converting the pulse signal into the trunk node signal through a photoelectric isolation circuit;
the system to be tested is used for realizing the function of high-frequency jitter filtering, collecting the trunk node signals through an input channel, then performing data processing, and outputting the signals after data processing through an output channel;
the signal after the output data processing is displayed and compared by a test instrument displaying the dry node signal at the same time, whether a signal waveform higher than the specified frequency is filtered is judged, and if so, the tested system realizes the function of high-frequency jitter filtering;
the test instrument comprises a high-frequency signal generating instrument connected with the input end of the photoelectric module and a system output waveform recording instrument connected with the output end;
the high-frequency signal generating instrument is used for generating a pulse signal, and the pulse signal is converted by the photoelectric module and then is collected by an input channel of the system to be tested;
the system to be tested comprises a data processing module for arithmetic logic operation, and an input end IO module and an output end IO module which are respectively connected with the data processing module;
the system comprises a system input channel, a system output waveform recording instrument, a data processing module and a data processing module, wherein signals acquired by the system input channel are output through an output channel and displayed by the system output waveform recording instrument;
the input channel is packaged in the input end IO module and is connected with the output end of the photoelectric isolation circuit;
and the output channel is packaged in an output end IO module and is connected with the system output waveform recording instrument.
5. The apparatus of claim 4, wherein said system output waveform recording instrument is configured to simultaneously display said stem node signal waveform and a signal waveform output by said output channel;
and if the trunk node signal waveform which is higher than the specified frequency is displayed to be changed into a straight line, judging that the signal waveform which is higher than the specified frequency is filtered.
6. The apparatus of claim 4, further comprising a terminal for monitoring arithmetic logic operation, wherein the terminal is connected with the counter of the data processing module and displays the number of transitions of the input channel acquisition signal;
and the jumping times are recorded by a counter of the data processing module and are consistent with the waveform number of the signal output by the output channel.
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| CN107797928B (en) * | 2017-10-26 | 2021-08-31 | 北京广利核系统工程有限公司 | Instrument control system platform logic algorithm block testing device and method |
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