CN109104192A - A kind of rail-to-rail ADC integrated circuit based on Data Fusion Structure - Google Patents

A kind of rail-to-rail ADC integrated circuit based on Data Fusion Structure Download PDF

Info

Publication number
CN109104192A
CN109104192A CN201810847076.6A CN201810847076A CN109104192A CN 109104192 A CN109104192 A CN 109104192A CN 201810847076 A CN201810847076 A CN 201810847076A CN 109104192 A CN109104192 A CN 109104192A
Authority
CN
China
Prior art keywords
rail
voltage
data fusion
adc
translation module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201810847076.6A
Other languages
Chinese (zh)
Other versions
CN109104192B (en
Inventor
张金箭
廖小海
郭亮杰
鲁文高
陈光毅
王慧
王恒彬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aerospace Long March Launch Vehicle Technology Co Ltd
Beijing Institute of Telemetry Technology
Original Assignee
Aerospace Long March Launch Vehicle Technology Co Ltd
Beijing Institute of Telemetry Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aerospace Long March Launch Vehicle Technology Co Ltd, Beijing Institute of Telemetry Technology filed Critical Aerospace Long March Launch Vehicle Technology Co Ltd
Priority to CN201810847076.6A priority Critical patent/CN109104192B/en
Publication of CN109104192A publication Critical patent/CN109104192A/en
Application granted granted Critical
Publication of CN109104192B publication Critical patent/CN109104192B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

The modules such as rail-to-rail ADC integrated circuit based on Data Fusion Structure, including AFE(analog front end), ADC, Data Fusion module, and optional analog switch, analogue buffer that the invention discloses a kind of.AFE(analog front end) signal processing and corresponding data blending algorithm based on plurality of voltages panning techniques solve the rail-to-rail acquisition scheme middle impedance matching of traditional ADC with what completely both amplitude of oscillation errors were difficult to take into account and apply bottleneck.The present invention is suitable for the input of Width funtion swing signal and high input impedance demand data acquires scene, can cope with polymorphic type multi-channel data acquisition demand, provide the solution of small size, low-power consumption, high reliability.

Description

A kind of rail-to-rail ADC integrated circuit based on Data Fusion Structure
Technical field
The invention belongs to ADC technical fields, and in particular to a kind of integrated electricity of the rail-to-rail ADC based on Data Fusion Structure Road.
Background technique
The framework of multichannel ADC cooperation sensor is widely used under a variety of scenes of internet of things, all types of sensings There are larger differences in the input amplitude of oscillation, input common-mode reference, sensor output impedance and change frequency for the signal that device is monitored It is different, therefore universal multichannel ADC need to take into account the electrical specification of all kinds of input signals and realize high Precision Processing and quantization to it. It is traditional with resistance-type PGA module for the sensor application scene of full amplitude of oscillation input signal amplitude and wide range output impedance As AFE(analog front end) signal processing ADC because input impedance it is lower, the problem of by impedance mismatch is brought, before thereby resulting in The loss of significance of grade signal.Therefore the ADC of conventional architectures will seriously limit the sensor type arranged in pairs or groups with it and number, cause to apply Bottleneck.
The above problem realizes sensing often through increase (in piece or outside piece) analogue buffer (such as operational amplifier) The impedance isolation of device and ADC are to solve, but as pre-processing module, noise perfomiance requirements are very harsh, therefore The way for increasing analogue buffer will bring huge power dissipation overhead；Meanwhile it needing to arrange in pairs or groups just when analogue buffer normal work Negative supply voltage, when number of channels is more, no matter a large amount of analogue buffer and positive-negative power voltage are in area or power consumption Aspect will all bring very big cost.Therefore, solved by the method for lower power consumption and area overhead sensor output impedance with The matching problem of multichannel ADC input impedance is multichannel ADC further key link in IoT applications.
Summary of the invention
It describes in view of the above problems, the invention proposes a kind of rail-to-rail ADC integrated circuit based on Data Fusion Structure, Using the ADC technical solution of AFE(analog front end) signal processing, parallel quantization and unified fusion based on plurality of voltages panning techniques.
The object of the invention is achieved by following technical solution:
A kind of rail-to-rail ADC integrated circuit based on Data Fusion Structure, including AFE(analog front end), ADC, data fusion are provided Processing module；
The AFE(analog front end) receives analog signal V to be collectedIN, export after boosted translation module boosting, translated through decompression It is exported after module decompression；
ADC acquires boosting translation module and the output voltage for being depressured translation module respectively, is sent to after carrying out analog-to-digital conversion Data Fusion module；
Data Fusion module according to boosting translation module and be depressured translation module output voltage quantized value respectively into Row calculates and storage, obtains input voltage final quantization value after carrying out data fusion.
Preferably, boosting translation module is by analog signal V to be collectedINX kind voltage V is exported after boosting respectivelyIN+VSP1…VIN +VSPX, 5 >=X >=1；Translation module is depressured by analog signal V to be collectedINM kind voltage V is exported after decompression respectivelyIN-VSN1…VIN- VSNM, M is natural number, 5 >=M >=1；ADC acquires X kind voltage V respectivelyIN+VSP1…VIN+VSPXWith M kind voltage VIN-VSN1…VIN- VSNM, Data Fusion module is sent to after carrying out analog-to-digital conversion.
Preferably, Data Fusion module includes arithmetic element: the X+M kind that arithmetic element receives ADC output translates electricity Quantized value is pressed, the voltage quantization value after the boosting of X kind is individually subtracted to the respective boosting shift value of storage, obtains analog signal VIN Corresponding first group of quantized value VINP1…VINPX；The respective decompression that storage is individually subtracted in voltage quantization value after the decompression of M kind is put down Shifting value obtains analog signal VINCorresponding second group of quantized value VINN1…VINNM。
Preferably, the AFE(analog front end) receives reference voltage V in initial phaseREF, receive in data acquisition phase wait adopt Collecting voltage VIN, the received voltage of institute, which is distinguished after boosted translation module is boosted, to be exported, and is exported after decompression translation module decompression； ADC acquires boosting translation module and the output voltage for being depressured translation module respectively, is sent to quantized value after carrying out analog-to-digital conversion Data Fusion module；Data Fusion module by boost translation module and be depressured translation module output voltage quantized value It is stored and processed respectively.
Preferably, in initial phase, translation module of boosting is by reference voltage VREFX kind voltage V is exported after boosting respectivelyREF +VSP1…VREF+VSPX, 5 >=X >=1；Translation module is depressured by reference voltage VREFM kind voltage V is exported after decompression respectivelyREF-VSN1… VREF-VSNM, M is natural number, 5 >=M >=1；ADC acquires X kind voltage V respectivelyREF+VSP1…VREF+VSPXWith M kind voltage VREF- VSN1…VREF-VSNM, it is sent to Data Fusion module after carrying out analog-to-digital conversion and is stored.
Preferably, Data Fusion module includes arithmetic element: receiving treating for ADC output in data acquisition phase and adopts Collecting voltage VINX+M kind translate voltage quantization value, respectively by its it is corresponding with storage translate voltage value reference voltage VREFIt is flat Move voltage quantization value make it is poor, then with reference voltage VREFTheoretical quantized value is added, and obtains analog signal VINIt is corresponding flat by boosting First group of quantized value V of shifting formwork block accessINP1…VINPXWith second group of quantized value V by decompression translation module accessINN1… VINNM。
Preferably, Data Fusion module includes data fusion control unit, by first group of quantized value, second group of quantization Take mean value as input voltage final quantization value after value excluding outlier.
Preferably, X, M are 1, and Data Fusion module includes data fusion control unit, select VINN1Or VINP1Make To judge voltage V, if V >=V1, then second group of quantized value is selected；V≤V2, then first group of quantized value is selected；If V2<V<V1, Then VINN1And VINP1It takes average as voltage final quantization value；Wherein V1Take 0.6U~0.8U, V2It is described for taking 0.2U~0.4U, U The voltage max that AFE(analog front end) can acquire.
Preferably, VSP1…VSPXValue be sequentially increased, VSN1…VSNMValue be sequentially increased, Data Fusion module includes Data fusion control unit selects VINN1Or VINP1As voltage V is judged, if V >=VREF, then second group of quantized value is selected VINN1…VINNMCalculate input voltage final quantization value；If V < VREF, then first group of quantized value V is selectedINP1…VINPXIt calculates defeated Enter voltage final quantization value.
Preferably, ifSelect VINNjAs voltage final quantization Value, 1≤j≤M；If1≤i≤X selects VINPiAs voltage final quantization value； If V=VREF, select VINN1As voltage final quantization value.
Preferably, the boost circuit structure for translation module of boosting are as follows: the drain electrode of the first NMOS tube connects positive pole, grid Input voltage is received, source electrode is grounded through first resistor and the first current source；The drain electrode of second NMOS tube connects electricity by second resistance Source anode, grid connect the output end of the first operation amplifier circuit, and source electrode is grounded through the second current source；Second current source is the The mirror current source of one current source；Two input terminals of the first operation amplifier circuit are connected to two the non-of current source and connect Ground terminal.
Preferably, it is depressured the reduction voltage circuit structure of translation module are as follows: the first PMOS tube grounded drain, grid receive input electricity Pressure, source electrode connect positive pole through 3rd resistor and third current source；The drain electrode of second PMOS tube connects through the 4th resistance eutral grounding, grid The output end of second operational amplifier circuit is connect, source electrode connects positive pole through the 4th current source；4th current source is third electricity The mirror current source in stream source；Two input terminals of second operational amplifier circuit are connected to two the non-of current source and connect power supply End.
Preferably, the first, second operation amplifier circuit forms the first, second filter circuit with RC array respectively.
Preferably, the first, second filter circuit is realized using 2 rank KRC low-pass filters.
It preferably, further include analog switch, the AFE(analog front end) is K, respectively corresponds the parallel analog signal in the road K, mould The output signal of one AFE(analog front end) of quasi- switch selection is exported to ADC.
It preferably, further include analogue buffer, analog switch selects the output signal of an AFE(analog front end) through simulated cushioned Output is to ADC after device driving.
Preferably, Data Fusion module includes memory, for storing reference voltage VREFBoosting quantized value and drop Press quantized value and VREF, boosting translational movement, be depressured translational movement theoretical value, memory use based on latch structure store battle array Column.
Preferably, reference voltage VREFIt is provided by piece a reference source or piece directly inputs outside.
A kind of rail-to-rail ADC integrated circuit progress data acquisition using described based on Data Fusion Structure is provided simultaneously Method, include the following steps:
(1) when rail-to-rail ADC integrated circuit initializes, AFE(analog front end) receives reference voltage VREF, boosted translation module It exports after boosting, is exported after decompression translation module decompression；ADC acquires boosting translation module respectively and is depressured the defeated of translation module Quantized value is sent to Data Fusion module after carrying out analog-to-digital conversion by voltage out；Data Fusion module is flat by boosting Shifting formwork block and the output voltage quantized value of decompression translation module are stored respectively；
(2) AFE(analog front end) acquires analog signal V to be collected when data acquireIN, export, pass through after boosted translation module boosting It is exported after decompression translation module decompression；ADC acquires boosting translation module and the output voltage for being depressured translation module respectively, carries out mould Data Fusion module is sent to after number conversion；Data Fusion module is according to boosting translation module and decompression translation module Output voltage quantized value calculate separately, carry out data fusion after obtain input voltage final quantization value.
The present invention has the advantage that compared with current art
(1) ADC integrated circuit of the invention does not solve in traditional ADC framework using impedance brought by PGA module not Match and expire amplitude of oscillation error etc. using bottleneck, while considerably reducing the DC power of active device, is realized under more small area Same noiseproof feature；
(2) offset error is eliminated by numeric field in channel of the present invention, avoids traditional analog disappearance tune means band DC power, the limitation of device matching precision, control logic come etc. is additional.Multichannel data is merged with the tune that disappears in same step It completes, alleviates hardware spending.
(3) data anastomosing algorithm is realized using combinational logic, and is operated and completed with simplest plus-minus.Timing is avoided to patrol Collect bring power consumption, the expense of system complexity and hardware costs.The data fusion operation of each is completed within the most fast time, And final quantized result is filtered out in real time after the completion of highest order data operation.
(4) analog portion circuit of the present invention realizes the rail-to-rail data acquisition of high input impedance by variation.
Detailed description of the invention
Fig. 1 is the rail-to-rail ADC integrated circuit schematic proposed by the present invention based on Data Fusion Structure；
Fig. 2 is that the present invention proposes boosting translation module and decompression translation module circuit diagram in AFE(analog front end)；
Fig. 3 is that the present invention proposes multichannel data fusion treatment course of work schematic diagram.
Specific embodiment
In order to balance in multichannel ADC acquisition high input impedance and full amplitude of oscillation input signal amplitude demand, and eliminate each Channel circuit inputs the problems such as dynamic range loss and interchannel consistency decline in channel caused by misalignment rate difference, this hair It is bright to propose a kind of rail-to-rail ADC integrated circuit based on Data Fusion Structure, and provide circuit implementing scheme.The present invention is first Using CMOS source follower as the input terminal of AFE(analog front end), input signal is made to boost or depressurization translation respectively, and through ADC After quantization, then by Data Fusion module by multichannel translation voltage quantized result fusion calculation obtain a final correspondence In the quantized result of original input signal.It is more using the convenience of digital domain signal processing and rich realization on this basis Function and performance boost.
In conjunction with Fig. 1, the rail-to-rail ADC integrated circuit based on Data Fusion Structure, including AFE(analog front end), ADC, data fusion Processing module etc.；The AFE(analog front end) receives analog signal V to be collectedIN, it is exported after boosted translation module boosting, it is flat through being depressured It is exported after the decompression of shifting formwork block；ADC acquires boosting translation module and the output voltage for being depressured translation module respectively, carries out analog-to-digital conversion After be sent to Data Fusion module；Data Fusion module is according to boosting translation module and the output for being depressured translation module Voltage quantization value is calculated separately and is stored, and obtains input voltage final quantization value after carrying out data fusion.
The AFE(analog front end) receives reference voltage V in initial phaseREF, voltage to be collected is received in data acquisition phase VIN, each voltage, which is distinguished after boosted translation module is boosted, to be exported, and is exported after decompression translation module decompression；ADC acquires liter respectively It presses translation module and is depressured the output voltage of translation module, quantized value is sent to Data Fusion mould after progress analog-to-digital conversion Block；Data Fusion module by boost translation module and be depressured translation module output voltage quantized value respectively carry out storage and Processing.
In one embodiment, AFE(analog front end) only receives analog signal V to be collectedIN, boosting translation module will be to be collected Analog signal VINX kind voltage V is exported after boosting respectivelyIN+VSP1…VIN+VSPX, 5 >=X >=1；Translation module is depressured by mould to be collected Quasi- signal VINM kind voltage V is exported after decompression respectivelyIN-VSN1…VIN-VSNM, M is natural number, 5 >=M >=1；ADC acquires X kind respectively Voltage VIN+VSP1…VIN+VSPXWith M kind voltage VIN-VSN1…VIN-VSNM, Data Fusion mould is sent to after carrying out analog-to-digital conversion Block.Data Fusion module includes arithmetic element: the X+M kind that arithmetic element receives ADC output translates voltage quantization value, by X The respective boosting shift value being previously stored is individually subtracted in voltage quantization value after kind boosting, obtains analog signal VINCorresponding One group of quantized value VINP1…VINPX；Voltage quantization value after the decompression of M kind is individually subtracted to the respective decompression translation being previously stored Value obtains analog signal VINCorresponding second group of quantized value VINN1…VINNM。
In another embodiment, boosting translation module is by reference voltage VREFOr analog signal V to be collectedINDivide after boosting It Shu Chu not X kind voltage VREF/VIN+VSP1…VREF/VIN+VSPX, 5 >=X >=1；Translation module is depressured by analog signal V to be collectedINDrop M kind voltage V is exported after pressure respectivelyREF/VIN-VSN1…VREF/VIN-VSNM, M is natural number, 5 >=M >=1；ADC acquires X kind electricity respectively Press VREF/VIN+VSP1…VREF/VIN+VSPXWith M kind voltage VREF/VIN-VSN1…VREF/VIN-VSNM, it is sent to after carrying out analog-to-digital conversion Data Fusion module.
Data Fusion module includes arithmetic element: arithmetic element is in initial phase reception ADC output to reference Voltage VREFThe translation of X+M kind voltage quantization value and stored, data acquisition phase receive ADC output to electricity to be collected Press VINX+M kind translate voltage quantization value, respectively by the reference voltage V of itself and storageREFTranslation voltage quantization value make it is poor, then With reference voltage VREFTheoretical quantized value is added, and obtains analog signal VINCorresponding first group by boosting translation module access Quantized value VINP1…VINPXWith second group of quantized value V by decompression translation module accessINN1…VINNM。
Data Fusion module further includes data fusion control unit, and first group of quantized value, second group of quantized value are picked Except taken after exceptional value mean value as input voltage final quantization value.
In one embodiment, work as X, when M is 1, data fusion control unit selects VINN1Or VINP1As judgement electricity V is pressed, if V >=V1, then second group of quantized value is selected；V≤V2, then first group of quantized value is selected；If V2<V<V1, then VINN1With VINP1It takes average as voltage final quantization value；Wherein V1Take 0.6U~0.8U, V2Taking 0.2U~0.4U, U is the AFE(analog front end) The voltage max that can be acquired.
In this second embodiment, V is setSP1…VSPXValue be sequentially increased, VSN1…VSNMValue be sequentially increased, data are melted It closes control unit and selects VINN1Or VINP1As voltage V is judged, if V >=VREF, then second group of quantized value V is selectedINN1…VINNMMeter Calculate input voltage final quantization value；If V < VREF, then first group of quantized value V is selectedINP1…VINPXCalculate input voltage final quantity Change value.
IfSelect VINNjAs voltage final quantization value, 1≤j≤ M；If1≤i≤X；If V=VREFSelect VINN1As voltage final quantization Value.
In conjunction with Fig. 2, the boost circuit structure of the boosting translation module are as follows: the drain electrode connection power supply of the first NMOS tube is just Pole, grid receive input voltage, and source electrode is grounded through first resistor and the first current source；The drain electrode of second NMOS tube passes through second resistance The output end of positive pole, grid the first operation amplifier circuit of connection is connected, source electrode is grounded through the second current source；Second electric current Source is the mirror current source of the first current source；Two input terminals of the first operation amplifier circuit are connected to two current sources Ungrounded end.
The reduction voltage circuit structure of the decompression translation module are as follows: the first PMOS tube grounded drain, grid receive input voltage, Source electrode connects positive pole through 3rd resistor and third current source；The drain electrode of second PMOS tube is connected through the 4th resistance eutral grounding, grid The output end of second operational amplifier circuit, source electrode connect positive pole through the 4th current source；4th current source is third electric current The mirror current source in source；Two input terminals of second operational amplifier circuit are connected to two the non-of current source and connect power supply End.
First, second operation amplifier circuit can form the first, second filter circuit with RC array respectively.
The realization of 2 rank KRC low-pass filters can be used in first, second filter circuit.
The rail-to-rail ADC integrated circuit based on Data Fusion Structure may also include analog switch, before the simulation End is K, respectively corresponds the parallel analog signal in the road K, analog switch select the output signal of an AFE(analog front end) export to ADC。
The rail-to-rail ADC integrated circuit based on Data Fusion Structure may also include analogue buffer, analog switch The output signal of an AFE(analog front end) is selected to export after analogue buffer drives to ADC.
Data Fusion module includes memory, for storing reference voltage boosting quantized value and decompression quantized value, is deposited Reservoir, which uses, is based on latch architecture memory array.
Reference voltage VREFIt can be provided by piece a reference source or piece directly inputs outside.
Rail-to-rail ADC integrated circuit based on Data Fusion Structure carries out data acquisition and includes the following steps:
(1) when rail-to-rail ADC integrated circuit initializes, AFE(analog front end) receives reference voltage VREF, boosted translation module It exports after boosting, is exported after decompression translation module decompression；ADC acquires boosting translation module respectively and is depressured the defeated of translation module Quantized value is sent to Data Fusion module after carrying out analog-to-digital conversion by voltage out；Data Fusion module is flat by boosting Shifting formwork block and the output voltage quantized value of decompression translation module are stored respectively；
(2) AFE(analog front end) acquires analog signal V to be collected when data acquireIN, export, pass through after boosted translation module boosting It is exported after decompression translation module decompression；ADC acquires boosting translation module and the output voltage for being depressured translation module respectively, carries out mould Data Fusion module is sent to after number conversion；Data Fusion module is according to boosting translation module and decompression translation module Output voltage quantized value calculate separately, carry out data fusion after obtain input voltage final quantization value.
The present invention is described in detail with reference to the accompanying drawing.
Embodiment 1
Rail-to-rail ADC integrated circuit based on Data Fusion Structure proposed by the invention is as shown in Figure 1, voltage shifts mould Block includes boosting translation module (p-type) and decompression translation module (N-type) two kinds of citation forms, be respectively used to the translation of upward current potential with Downward current potential translation, with ensure input signal close to 0V and supply voltage or other be difficult to the voltage range acquired when can be just Really acquisition quantization.For ease of understanding, described below to be reduced to carry out based on the two-way Data Fusion Structure of N-type and p-type respectively all the way Introduction, i.e. X and M are 1 N/P two-way modular structure.
ADC integrated circuit in Fig. 1 includes analog front-end module shown in 64 altogether, and each module is logical as an input Road, each channel can acquire different analog input signals respectively.To the AFE(analog front end) of each input channel, input signal is first It is handled through N/P two-way voltage shifts modular concurrent, wherein the road N module is using NMOS source follower as input stage, to input signal Carry out the downward translation of voltage；The road P module carries out the upward of voltage then using pmos source follower as input stage, to input signal Translation, translation voltage by current source export constant current process resistance string divide control, be achieved in impedance transformation with Input signal amplitude adjustment, while thus obtaining meeting the requirement of ADC quantification treatment by low-pass filter removal clutter interference Analog signal.Then, corresponding channel can be gated by analog switch, corresponding input signal to be collected is quantified；All channels Treated that output signal passes through that mutually isostructural SAR-ADC carries out analog-to-digital conversion obtains corresponding quantization number for AFE(analog front end) According to；Two groups of quantized results in last each channel are reverted to by data fusion module should corresponding to an original input signal Secondary quantization modulus of periodicity number transformation result.
Decompression translation (N-type) module and boosting translation (p-type) modular structure of each AFE(analog front end) are as shown in Fig. 2, left side For decompression translation (N-type) module in channel, right side is boosting translation (p-type) module.Its design principle is specifically explained by taking N-type as an example And the course of work.Input signal is applied to NMOS input pipe grid end, and by NMOS, resistance and the voltage-controlled common structure of type reference current source At source follower all the way, the reference data of controlled current source by chip a reference voltage (with temperature, voltage fluctuation and Technological fluctuation is unrelated) load on the resistance of same type produced by, therefore resistance two on N/P source follower branch in single channel The pressure drop at end will be determined by resistance ratios and piece internal reference voltage, when front end analogue current potential translational movement follows branch resistance by source When pressure drop is determined, it is ensured that the stability and the linearity of the translational movement.When concrete scheme is implemented, by source follower and 2 ranks KRC low-pass filter merge design, using high precision operating amplifier DC current gain realize equal potentials clamper, i.e., two Source follows the current source output current potential of branch to be consistent.And then available two branch roads source NMOS follows input pipe Drain-source voltage is also equal, can be guaranteed between the output voltage of AFE(analog front end) and input signal by dimensionally-optimised and layout design Potential difference is determined by the pressure drop of resistance both ends and process deviation completely.2 rank KRC filters also provide flat passband simultaneously The stopband of gain and -40dB/dec roll-off rate, guarantee signal effective bandwidth and noise power.
The present invention proposes that the multichannel data fusion treatment course of work is as shown in Figure 3: the main thought of algorithm is to utilize input Signal and a fixed reference current potential VREFBetween calibration of the difference as signal, and the absolute value of non-input signal.Using class CDS Treatment process eliminate the DC offset voltage in each channel.In the initialization of calibration stage, each channel first handles same ginseng Voltage input signal is examined, the available quantized data comprising each channel error information on the basis of guaranteeing SAR-ADC performance. Single channel corresponds to multichannel quantized result (road Fig. 3 Zhong Wei N/P respectively all the way example), i.e., by VREFIt is moved to V respectivelyREF+VSPWith VREF- VSNAnd quantify respectively, then this data is stored in piece, thus complete the initialization of calibration work of a cycle, this reality It applies and shares 64 input channels in example, each channel includes N/P two-way voltage shifts module, therefore has 64 groups of VREF+VSPWith VREF- VSNQuantized value, i.e. 128 reference voltage quantized values need to store, with the calibration for each channel.Quantization step is acquired in data Section, each respective input signal of channel independent process, analog switch gates corresponding acquisition channel, by corresponding channel AFE(analog front end) N/P two-way translate as a result, i.e. VIN+VSPAnd VIN- VSN, quantify through ADC, then in 64 groups of V of storageREF+VSPAnd VREF- VSN In quantized value, select one group of corresponding channel, read to bus, respectively with VIN+VSPAnd VIN- VSNQuantized value carries out subtraction behaviour Make, to obtain this difference amount of quantization periodic input signal relative to reference potential of the channel, i.e. (VIN- VREF)PWith (VIN- VREF)N, two difference amounts are summed with the theoretical quantized value of calibration phase institute input reference voltage respectively finally, are obtained By the first quantized value V of the translation module access that boostsINPWith the second quantized value V by being depressured translation accessINN；Judgement obtains The second quantized value VINNWhether in [U/2, U] voltage range, V is selected if in the sectionINNAs final quantization value, instead Then select VINPAs final quantization value；Or work as VINNWhen in the section (0.4U, 0.6U), (V is calculatedINP+VINN)/2 are as most Whole quantized value, to improve the linearity of quantized result, and when being higher or lower than the voltage range, respectively with VINNAnd VINPAs Final quantization result.Above data amalgamation mode also achieves the elimination and passage consistency calibration of channel DC imbalance: a side Face, virtual voltage translational movement may be deviated with design value, but by reference voltage do after same translation transformation again with letter to be measured Number translation measure difference, the deviation effects of voltage shifts amount can be eliminated；On the other hand, it is influenced by non-ideal effects, 64 In input channel, can be also deviated between the AFE(analog front end) in each channel, and by reference voltage by each channel analogy before Hold the quantized value after moving level with both hands to store, for calibrating, the error of each interchannel can be eliminated, improve passage consistency.Cause This, can not store the quantized value of reference voltage without initialization of calibration in implementation, and directly use VIN+VSPAnd VIN- VSN It is individually subtracted and is corrected plus the design value of translation voltage, obtain quantized result, but the precision of quantized result can be lower than process The quantized result of initialization of calibration.
Simulation process part in Fig. 3, main current potential adjustment task of completing is to adapt to wanting for power supply system signal processing range It asks.Quantization, storage and the data fusion task exported to front end processing block is completed in digital processing part.Wherein imbalance in piece Data storage cell structure uses Latch structure to realize flexible read-write operation and higher storage density.It is shown in FIG. 1 ALU is the arithmetic element of data anastomosing algorithm, including 4 cascade 4bit carry lookahead adders and a constant adder logic Unit realizes that each step operation of algorithm obtains final quantization result.
Embodiment 2
Rail-to-rail ADC integrated circuit main structure and workflow and implementation in the embodiment based on Data Fusion Structure It is essentially identical in example 1, the difference is that having 2 boosting translation module (P-Type) P1, P2 and 4 decompressions flat in each channel Shifting formwork block (N-Type) N1, N2, N3, N4, rather than each 1 in embodiment 1.Assuming that wherein the boosting translational movement of P1, P2 are distinguished For VSP1=0.1U and VSP2The decompression translational movement of=0.2U, N1, N2, N3, N4 are respectively VSN1=0.1U, VSN2=0.2U, VSN3= 0.3U and VSN4=0.4U.
First group of quantized value V will be obtained after each translation voltage quantization and fusion calculationINP1、VINP2With second group of quantized value VINN1、VINN2、VINN3、VINN4.If reference voltage VREF=0.5U, successively judges VINN1Whether fall in [0.5U, 0.625U], (0.625U, 0.75U], (0.75U, 0.875U], in the section [0.875U, U], if falling in [0.5U, 0.625U], choose VINN1 As final quantization value, if falling in other 3 sections, respectively corresponds and choose VINN2、VINN3、VINN4As final quantization value； Conversely, if VINN1Fall in [0.25U, 0.5U) or [0,0.25U) in section, then V is chosen respectivelyINP1And VINP2As final quantization Value.
The above, optimal specific embodiment only of the invention, but scope of protection of the present invention is not limited thereto, In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art, It should be covered by the protection scope of the present invention.
The content that description in the present invention is not described in detail belongs to the well-known technique of professional and technical personnel in the field.

Claims (19)

1. a kind of rail-to-rail ADC integrated circuit based on Data Fusion Structure, which is characterized in that including AFE(analog front end), ADC, number According to fusion treatment module；
The AFE(analog front end) receives analog signal V to be collectedIN, exported after boosted translation module boosting, through being depressured translation module It is exported after decompression；
ADC acquires boosting translation module and the output voltage for being depressured translation module respectively, is sent to data after carrying out analog-to-digital conversion Fusion treatment module；
Data Fusion module is counted respectively according to the output voltage quantized value of boosting translation module and decompression translation module It calculates and stores, obtain input voltage final quantization value after carrying out data fusion.
2. the rail-to-rail ADC integrated circuit based on Data Fusion Structure as described in claim 1, which is characterized in that boosting is flat Shifting formwork block is by analog signal V to be collectedINX kind voltage V is exported after boosting respectivelyIN+VSP1…VIN+VSPX, 5 >=X >=1；Decompression translation Module is by analog signal V to be collectedINM kind voltage V is exported after decompression respectivelyIN-VSN1…VIN-VSNM, M is natural number, 5 >=M >=1； ADC acquires X kind voltage V respectivelyIN+VSP1…VIN+VSPXWith M kind voltage VIN-VSN1…VIN-VSNM, it is sent to after carrying out analog-to-digital conversion Data Fusion module.
3. the rail-to-rail ADC integrated circuit based on Data Fusion Structure as claimed in claim 2, which is characterized in that data are melted Closing processing module includes arithmetic element: the X+M kind that arithmetic element receives ADC output translates voltage quantization value, after the boosting of X kind The respective boosting shift value of storage is individually subtracted in voltage quantization value, obtains analog signal VINCorresponding first group of quantized value VINP1…VINPX；Voltage quantization value after the decompression of M kind is individually subtracted to the respective decompression shift value of storage, obtains analog signal VINCorresponding second group of quantized value VINN1…VINNM。
4. the rail-to-rail ADC integrated circuit based on Data Fusion Structure as claimed in claim 2, which is characterized in that the mould Quasi- front end receives reference voltage V in initial phaseREF, voltage V to be collected is received in data acquisition phaseIN, the received voltage of institute It exports after boosted translation module boosting, is exported after decompression translation module decompression respectively；ADC acquires boosting translation module respectively With the output voltage of decompression translation module, quantized value is sent to Data Fusion module after carrying out analog-to-digital conversion；Data are melted Processing module is closed to store and process the output voltage quantized value of boost translation module and decompression translation module respectively.
5. the rail-to-rail ADC integrated circuit based on Data Fusion Structure as claimed in claim 4, which is characterized in that initial In the change stage, boosting translation module is by reference voltage VREFX kind voltage V is exported after boosting respectivelyREF+VSP1…VREF+VSPX, 5 >=X >= 1；Translation module is depressured by reference voltage VREFM kind voltage V is exported after decompression respectivelyREF-VSN1…VREF-VSNM, M is natural number, 5 ≥M≥1；ADC acquires X kind voltage V respectivelyREF+VSP1…VREF+VSPXWith M kind voltage VREF-VSN1…VREF-VSNM, carry out modulus and turn Data Fusion module is sent to after changing to be stored.
6. the rail-to-rail ADC integrated circuit based on Data Fusion Structure as claimed in claim 5, which is characterized in that data are melted Closing processing module includes arithmetic element: treating collection voltages V in data acquisition phase reception ADC outputINX+M kind translate electricity Quantized value is pressed, respectively by its reference voltage V corresponding with storageREFTranslation voltage quantization value make it is poor, then with reference voltage VREF Theoretical quantized value is added, and obtains analog signal VINCorresponding first group of quantized value V by boosting translation module accessINP1… VINPXWith second group of quantized value V by decompression translation module accessINN1…VINNM。
7. the rail-to-rail ADC integrated circuit based on Data Fusion Structure as claimed in claim 6, which is characterized in that data are melted Closing processing module includes data fusion control unit, will take mean value after first group of quantized value, second group of quantized value excluding outlier As input voltage final quantization value.
8. the rail-to-rail ADC integrated circuit based on Data Fusion Structure as claimed in claim 7, which is characterized in that X, M are 1, Data Fusion module includes data fusion control unit, selects VINN1Or VINP1As voltage V is judged, if V >=V1, Then select second group of quantized value；V≤V2, then first group of quantized value is selected；If V2<V<V1, then VINN1And VINP1Take average conduct Voltage final quantization value；Wherein V1Take 0.6U~0.8U, V2Taking 0.2U~0.4U, U is the voltage that the AFE(analog front end) can acquire Maximum value.
9. the rail-to-rail ADC integrated circuit based on Data Fusion Structure as claimed in claim 6, which is characterized in that VSP1… VSPXValue be sequentially increased, VSN1…VSNMValue be sequentially increased, Data Fusion module includes data fusion control unit, choosing Select VINN1Or VINP1As voltage V is judged, if V >=VREF, then second group of quantized value V is selectedINN1…VINNMCalculate input voltage Final quantization value；If V < VREF, then first group of quantized value V is selectedINP1…VINPXCalculate input voltage final quantization value.
10. the rail-to-rail ADC integrated circuit based on Data Fusion Structure as claimed in claim 9, which is characterized in that ifSelect VINNjAs voltage final quantization value, 1≤j≤M；If1≤i≤X selects VINPiAs voltage final quantization value；If V=VREF, selection VINN1As voltage final quantization value.
11. the rail-to-rail ADC integrated circuit based on Data Fusion Structure as described in one of claim 7~10, feature exist In the boost circuit structure for translation module of boosting are as follows: drain electrode connection positive pole, the grid of the first NMOS tube receive input electricity Pressure, source electrode are grounded through first resistor and the first current source；The drain electrode of second NMOS tube connects positive pole, grid by second resistance The output end of the first operation amplifier circuit is connected, source electrode is grounded through the second current source；Second current source is the first current source Mirror current source；Two input terminals of the first operation amplifier circuit are connected to the ungrounded end of two current sources.
12. the rail-to-rail ADC integrated circuit based on Data Fusion Structure as claimed in claim 11, which is characterized in that decompression The reduction voltage circuit structure of translation module are as follows: the first PMOS tube grounded drain, grid receive input voltage, source electrode through 3rd resistor and Third current source connects positive pole；The drain electrode of second PMOS tube is through the 4th resistance eutral grounding, grid connection second operational amplifier electricity The output end on road, source electrode connect positive pole through the 4th current source；4th current source is the mirror current source of third current source；The Two input terminals of two operation amplifier circuits are connected to two the non-of current source and connect power end.
13. the rail-to-rail ADC integrated circuit based on Data Fusion Structure as claimed in claim 12, which is characterized in that first, Second operational amplifier circuit forms the first, second filter circuit with RC array respectively.
14. the rail-to-rail ADC integrated circuit based on Data Fusion Structure as claimed in claim 13, which is characterized in that first, Second filter circuit is realized using 2 rank KRC low-pass filters.
15. the rail-to-rail ADC integrated circuit based on Data Fusion Structure as claimed in claim 11, which is characterized in that also wrap Analog switch is included, the AFE(analog front end) is K, the parallel analog signal in the road K is respectively corresponded, before analog switch selects a simulation The output signal at end is exported to ADC.
16. the rail-to-rail ADC integrated circuit based on Data Fusion Structure as claimed in claim 15, which is characterized in that also wrap Analogue buffer is included, analog switch selects the output signal of an AFE(analog front end) to export after analogue buffer drives to ADC.
17. the rail-to-rail ADC integrated circuit according to claim 11 based on Data Fusion Structure, it is characterised in that: number It include memory according to fusion treatment module, for storing reference voltage VREFBoosting quantized value and decompression quantized value and VREF、 Boosting translational movement, the theoretical value for being depressured translational movement, memory, which uses, is based on latch architecture memory array.
18. the rail-to-rail ADC integrated circuit according to claim 11 based on Data Fusion Structure, it is characterised in that: ginseng Examine voltage VREFIt is provided by piece a reference source or piece directly inputs outside.
19. a kind of rail-to-rail ADC integrated circuit based on Data Fusion Structure using described in claim 11 carries out data and adopts The method of collection, which comprises the steps of:
(1) when rail-to-rail ADC integrated circuit initializes, AFE(analog front end) receives reference voltage VREF, boosted translation module boosting After export, through decompression translation module decompression after export；ADC acquires boosting translation module and the output electricity for being depressured translation module respectively It presses, quantized value is sent to Data Fusion module after progress analog-to-digital conversion；Boosting is translated mould by Data Fusion module Block and the output voltage quantized value of decompression translation module are stored respectively；
(2) AFE(analog front end) acquires analog signal V to be collected when data acquireIN, exported after boosted translation module boosting, through being depressured It is exported after translation module decompression；ADC acquires boosting translation module and the output voltage for being depressured translation module respectively, carries out modulus and turns Data Fusion module is sent to after changing；Data Fusion module is according to boosting translation module and is depressured the defeated of translation module Voltage quantization value calculates separately out, obtains input voltage final quantization value after carrying out data fusion.
CN201810847076.6A 2018-07-27 2018-07-27 Rail-to-rail ADC integrated circuit based on data fusion structure Active CN109104192B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810847076.6A CN109104192B (en) 2018-07-27 2018-07-27 Rail-to-rail ADC integrated circuit based on data fusion structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810847076.6A CN109104192B (en) 2018-07-27 2018-07-27 Rail-to-rail ADC integrated circuit based on data fusion structure

Publications (2)

Publication Number Publication Date
CN109104192A true CN109104192A (en) 2018-12-28
CN109104192B CN109104192B (en) 2022-05-24

Family

ID=64847882

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810847076.6A Active CN109104192B (en) 2018-07-27 2018-07-27 Rail-to-rail ADC integrated circuit based on data fusion structure

Country Status (1)

Country Link
CN (1) CN109104192B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109738073A (en) * 2019-01-28 2019-05-10 北京安酷智芯科技有限公司 A kind of Nonuniformity Correction circuit and correction bias generating circuit
CN110221240A (en) * 2019-06-28 2019-09-10 深圳市锐能微科技有限公司 The detection circuit and electric energy computation chip of bleeder circuit parameter
CN113364461A (en) * 2021-06-24 2021-09-07 苏州磐启微电子有限公司 Analog-to-digital conversion calibration method and system for chip to be tested

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050237083A1 (en) * 2003-07-31 2005-10-27 Actel Corporation, A California Corporation Programmable system on a chip
US20100027379A1 (en) * 2006-10-02 2010-02-04 Gary Saulnier Ultrasonic Through-Wall Communication (UTWC) System
WO2010057900A1 (en) * 2008-11-20 2010-05-27 St Ericsson Sa Analog-to-digital conversion device, preferably for mobile telephony
EP2541775A1 (en) * 2011-06-23 2013-01-02 Università Degli Studi Roma Tre Analog pre-processing circuit for analog-to-digital converters of the folding type
CN103234689A (en) * 2013-04-24 2013-08-07 武汉航空仪表有限责任公司 Circuit of high-accuracy pressure transmitter
CN103685863A (en) * 2013-11-29 2014-03-26 青岛海信信芯科技有限公司 Video signal conversion circuit and television
CN104135273A (en) * 2014-07-28 2014-11-05 中国电子科技集团公司第二十四研究所 A BiCMOS buffer having linearity greater than 96 dB
US9154151B1 (en) * 2014-12-22 2015-10-06 Altera Corporation Analog-to-digital converter circuits and methods
CN105071806A (en) * 2015-08-28 2015-11-18 西安启微迭仪半导体科技有限公司 High-linearity input signal buffer applied to high-speed analog-digital converter
US9479188B1 (en) * 2010-05-28 2016-10-25 Maxim Integrated Products, Inc. Programmable multichannel signal selector
US9571115B1 (en) * 2015-11-13 2017-02-14 International Business Machines Corporation Analog to digital converter with high precision offset calibrated integrating comparators
CN108227813A (en) * 2016-12-12 2018-06-29 联发科技股份有限公司 Electric current huge profit circuit and electric current huge profit method

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050237083A1 (en) * 2003-07-31 2005-10-27 Actel Corporation, A California Corporation Programmable system on a chip
US20100027379A1 (en) * 2006-10-02 2010-02-04 Gary Saulnier Ultrasonic Through-Wall Communication (UTWC) System
WO2010057900A1 (en) * 2008-11-20 2010-05-27 St Ericsson Sa Analog-to-digital conversion device, preferably for mobile telephony
US9479188B1 (en) * 2010-05-28 2016-10-25 Maxim Integrated Products, Inc. Programmable multichannel signal selector
EP2541775A1 (en) * 2011-06-23 2013-01-02 Università Degli Studi Roma Tre Analog pre-processing circuit for analog-to-digital converters of the folding type
CN103234689A (en) * 2013-04-24 2013-08-07 武汉航空仪表有限责任公司 Circuit of high-accuracy pressure transmitter
CN103685863A (en) * 2013-11-29 2014-03-26 青岛海信信芯科技有限公司 Video signal conversion circuit and television
CN104135273A (en) * 2014-07-28 2014-11-05 中国电子科技集团公司第二十四研究所 A BiCMOS buffer having linearity greater than 96 dB
US9154151B1 (en) * 2014-12-22 2015-10-06 Altera Corporation Analog-to-digital converter circuits and methods
CN105071806A (en) * 2015-08-28 2015-11-18 西安启微迭仪半导体科技有限公司 High-linearity input signal buffer applied to high-speed analog-digital converter
US9571115B1 (en) * 2015-11-13 2017-02-14 International Business Machines Corporation Analog to digital converter with high precision offset calibrated integrating comparators
CN108227813A (en) * 2016-12-12 2018-06-29 联发科技股份有限公司 Electric current huge profit circuit and electric current huge profit method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109738073A (en) * 2019-01-28 2019-05-10 北京安酷智芯科技有限公司 A kind of Nonuniformity Correction circuit and correction bias generating circuit
CN110221240A (en) * 2019-06-28 2019-09-10 深圳市锐能微科技有限公司 The detection circuit and electric energy computation chip of bleeder circuit parameter
CN113364461A (en) * 2021-06-24 2021-09-07 苏州磐启微电子有限公司 Analog-to-digital conversion calibration method and system for chip to be tested
CN113364461B (en) * 2021-06-24 2024-05-03 苏州磐启微电子有限公司 Analog-to-digital conversion calibration method and system for chip to be tested

Also Published As

Publication number Publication date
CN109104192B (en) 2022-05-24

Similar Documents

Publication Publication Date Title
CN109104192A (en) A kind of rail-to-rail ADC integrated circuit based on Data Fusion Structure
US8907715B2 (en) Sampling
CN103262417B (en) A kind of circuit for capacitance touch application
Deepu et al. An ECG-on-chip with 535 nW/channel integrated lossless data compressor for wireless sensors
CN103199806B (en) To the programmable analogue unit of sensor signal process
CN101889863B (en) High-performance direct current amplification device for acquiring biological electric signals
CN103138759B (en) Share the integrating circuit of electric capacity and analog-to-digital circuit and method of operation thereof
CN104363020B (en) A kind of production line analog-digital converter and its error calibrating method
CN110750231B (en) Convolution neural network-oriented biphase coefficient adjustable analog multiplication circuit
US20050140537A1 (en) Architecture for an algorithmic analog-to-digital converter
DE102017121491B4 (en) Method and device for reducing the effect of dielectric absorption in a SAR ADC
CN108809310B (en) Passive time-interleaved SAR ADC-based band-pass Delta-Sigma modulator
DE102016117464A1 (en) Analog-digital conversion with analog filtering
CN101806630B (en) Reading circuit based on relaxor ferroelectric monocrystal pyroelectric detector
CN104168022B (en) A kind of X ray CCD read-out systems based on discrete time increment type Σ Δs ADC
US4145675A (en) Charged-coupled device filter
CN112153313A (en) High-speed column-level ADC circuit for CMOS image sensor
CN102420664B (en) Simulation system of noise signal for carrier test of low-voltage power line
DE102022134241A1 (en) Successive approximation register analog to digital converter
CN101594148B (en) Flash ADC with current inserted structure
CN107525530A (en) A kind of integrated circuit of absolute optical encoder
CN107508575A (en) Simulate finite impulse response filter
Ricci Design of a 12-bit 200-MSps SAR Analog-to-Digital converter
CN202435412U (en) Noise signal imitation system for low-voltage power line carrier test
CN102480297B (en) Successive comparison type AD converter

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant