CN109104192B - Rail-to-rail ADC integrated circuit based on data fusion structure - Google Patents

Rail-to-rail ADC integrated circuit based on data fusion structure Download PDF

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CN109104192B
CN109104192B CN201810847076.6A CN201810847076A CN109104192B CN 109104192 B CN109104192 B CN 109104192B CN 201810847076 A CN201810847076 A CN 201810847076A CN 109104192 B CN109104192 B CN 109104192B
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voltage
data fusion
rail
output
adc
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CN109104192A (en
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张金箭
廖小海
郭亮杰
鲁文高
陈光毅
王慧
王恒彬
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Beijing Research Institute of Telemetry
Aerospace Long March Launch Vehicle Technology Co Ltd
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Beijing Research Institute of Telemetry
Aerospace Long March Launch Vehicle Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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Abstract

The invention discloses a rail-to-rail ADC integrated circuit based on a data fusion structure, which comprises an analog front end, an ADC, a data fusion processing module, an optional analog switch, an analog buffer and the like. An analog front end signal processing and corresponding data fusion algorithm based on a multipath voltage translation technology solves the application bottleneck that impedance matching and full swing amplitude errors are difficult to take into account in the traditional ADC rail-to-rail acquisition scheme. The invention is suitable for the data acquisition scene with wide voltage swing signal input and high input impedance requirements, can meet the requirements of multi-type multi-channel data acquisition, and provides a solution with small size, low power consumption and high reliability.

Description

Rail-to-rail ADC integrated circuit based on data fusion structure
Technical Field
The invention belongs to the technical field of ADCs, and particularly relates to a rail-to-rail ADC integrated circuit based on a data fusion structure.
Background
The framework of the multi-channel ADC matched with the multi-type sensors is widely applied to various scenes of the Internet of things, and signals monitored by the various sensors have large differences in input swing amplitude, input common-mode reference, sensor output impedance and change frequency, so that the general multi-channel ADC needs to take into consideration the electrical specifications of various input signals and realize high-precision processing and quantification of the input signals. For the application scenario of a sensor with full-swing input signal amplitude and wide-range output impedance, the traditional ADC using a resistance-type PGA module as an analog front-end signal processing part has a problem of impedance mismatch due to low input impedance, thereby causing accuracy loss of a front-stage signal. Therefore, the ADC of the conventional architecture will severely limit the types and number of sensors to be collocated therewith, which causes application bottleneck.
The above problem is often solved by adding (on-chip or off-chip) analog buffer (e.g. operational amplifier) to realize impedance isolation between the sensor and the ADC, but as a pre-processing module, the noise performance is very demanding, so adding the analog buffer brings huge power consumption overhead; meanwhile, the analog buffers need to be matched with positive and negative power supply voltages when working normally, and when the number of channels is large, a large number of analog buffers and the positive and negative power supply voltages bring great cost in terms of area and power consumption. Therefore, the problem of matching between the output impedance of the sensor and the input impedance of the multi-channel ADC is solved by a method with low power consumption and area overhead, and the method is a further key link of the multi-channel ADC in the application of the Internet of things.
Disclosure of Invention
In view of the above description, the present invention provides a rail-to-rail ADC integrated circuit based on a data fusion structure, which adopts an ADC technical scheme based on multi-path voltage translation technology for analog front-end signal processing, parallel quantization and unified fusion.
The purpose of the invention is realized by the following technical scheme:
the rail-to-rail ADC integrated circuit based on the data fusion structure comprises an analog front end, an ADC and a data fusion processing module;
the analog front end receives an analog signal V to be acquiredINThe output is output after the voltage is boosted by the voltage boosting translation module, and the output is output after the voltage is reduced by the voltage reducing translation module;
the ADC respectively collects the output voltages of the voltage boosting translation module and the voltage reducing translation module, performs analog-to-digital conversion and then sends the converted output voltages to the data fusion processing module;
and the data fusion processing module respectively calculates and stores the quantized values of the output voltages of the voltage boosting translation module and the voltage reducing translation module, and obtains the final quantized value of the input voltage after data fusion.
Preferably, the boost translation module is used for collecting the analog signal V to be acquiredINRespectively outputting X voltages V after boostingIN+VSP1…VIN+VSPXX is more than or equal to 5 and more than or equal to 1; the voltage reduction translation module is used for collecting an analog signal VINRespectively outputting M voltages V after voltage reductionIN-VSN1…VIN-VSNMM is a natural number, and M is more than or equal to 5 and more than or equal to 1; ADC respectively collecting X kinds of voltage VIN+VSP1…VIN+VSPXAnd M voltages VIN-VSN1…VIN-VSNMAnd the data are transmitted to the data fusion processing module after analog-to-digital conversion.
Preferably, the data fusion processing module includes an arithmetic unit: the operation unit receives X + M translation voltage quantization values output by the ADC, and subtracts the stored boosting translation values from the X boosted voltage quantization values to obtain an analog signal VINCorresponding first set of quantized values VINP1…VINPX(ii) a Respectively subtracting the respective voltage reduction translation values stored from the voltage quantization values after the M types of voltage reduction to obtain an analog signal VINCorresponding second set of quantized values VINN1…VINNM。
Preferably, the analog front end receives the reference voltage V during an initialization phaseREFReceiving voltage V to be collected in data collection stageINThe received voltage is respectively output after being boosted by the boosting translation module and output after being reduced by the reducing translation module; the ADC respectively collects the output voltages of the voltage boosting translation module and the voltage reducing translation module, performs analog-to-digital conversion and then sends the quantized values to the data fusion processing module; and the data fusion processing module stores and processes the output voltage quantized values of the voltage boosting translation module and the voltage reducing translation module respectively.
Preferably, the boost translation module applies the reference voltage V during an initialization phaseREFRespectively outputting X voltages V after boostingREF+VSP1…VREF+VSPXX is more than or equal to 5 and more than or equal to 1; the voltage reduction translation module converts the reference voltage V into a voltageREFRespectively outputting M voltages V after voltage reductionREF-VSN1…VREF-VSNMM is a natural number, and M is more than or equal to 5 and more than or equal to 1; ADC respectively collecting X kinds of voltage VREF+VSP1…VREF+VSPXAnd M voltages VREF-VSN1…VREF-VSNMAnd after analog-to-digital conversion, the data are sent to a data fusion processing module for storage.
Preferably, the data fusion processing module includes an arithmetic unit: receiving voltage V to be acquired output by ADC in data acquisition stageINRespectively comparing the X + M translation voltage quantization values with the reference voltage V corresponding to the translation voltage valuesREFIs subtracted from the reference voltage VREFAdding the theoretical quantized values to obtain an analog signal VINCorresponding first set of quantized values V passing through boost shift module pathINP1…VINPXAnd a second set of quantized values V through the buck translation module pathINN1…VINNM。
Preferably, the data fusion processing module includes a data fusion control unit, and the first group of quantized values and the second group of quantized values are subjected to elimination of abnormal values and then averaged to be used as the final quantized value of the input voltage.
Preferably, X and M are both 1, the data fusion processing module comprises a data fusion control unit, and V is selectedINN1Or VINP1As the judgment voltage V, if V is more than or equal to V1Then a second set of quantized values is selected; v is less than or equal to V2Then a first set of quantized values is selected; if V2<V<V1Then V isINN1And VINP1Taking the average value as a final voltage quantization value; wherein V1Taking 0.6U-0.8U, V2And taking 0.2U-0.4U, wherein U is the maximum value of the voltage which can be collected by the analog front end.
Preferably, VSP1…VSPXAre successively increased in value of VSN1…VSNMThe data fusion processing module comprises a data fusion control unit and selects VINN1Or VINP1As the judgment voltage V, if V is more than or equal to VREFThen a second set of quantized values V is selectedINN1…VINNMCalculating a final quantized value of the input voltage; if V<VREFThen a first set of quantized values V is selectedINP1…VINPXAnd calculating a final quantized value of the input voltage.
Preferably, if
Figure BDA0001746836150000031
Selection of VINNjJ is more than or equal to 1 and less than or equal to M as the final quantized value of the voltage; if it is not
Figure BDA0001746836150000032
I is more than or equal to 1 and less than or equal to X, and V is selectedINPiAs a voltage final quantized value; if V is VREFSelecting VINN1As the final quantized value of the voltage.
Preferably, the boost circuit structure of the boost translation module is: the drain electrode of the first NMOS tube is connected with the positive electrode of the power supply, the grid electrode of the first NMOS tube receives input voltage, and the source electrode of the first NMOS tube is grounded through a first resistor and a first current source; the drain electrode of the second NMOS tube is connected with the positive electrode of the power supply through a second resistor, the grid electrode of the second NMOS tube is connected with the output end of the first operational amplifier circuit, and the source electrode of the second NMOS tube is grounded through a second current source; the second current source is a mirror current source of the first current source; two input ends of the first operational amplifier circuit are respectively connected with the non-grounding ends of the two current sources.
Preferably, the voltage reduction circuit structure of the voltage reduction translation module is as follows: the drain electrode of the first PMOS tube is grounded, the grid electrode of the first PMOS tube receives input voltage, and the source electrode of the first PMOS tube is connected with the anode of the power supply through a third resistor and a third current source; the drain electrode of the second PMOS tube is grounded through a fourth resistor, the grid electrode of the second PMOS tube is connected with the output end of the second operational amplifier circuit, and the source electrode of the second PMOS tube is connected with the positive electrode of the power supply through a fourth current source; the fourth current source is a mirror current source of the third current source; two input ends of the second operational amplifier circuit are respectively connected with the non-connected power supply ends of the two current sources.
Preferably, the first operational amplifier circuit and the second operational amplifier circuit respectively form a first filter circuit and a second filter circuit together with the RC array.
Preferably, the first and second filter circuits are implemented by 2-order KRC low-pass filters.
Preferably, the digital to analog converter further comprises K analog switches, the number of the analog front ends is K, the K analog front ends correspond to K paths of parallel analog signals respectively, and the analog switches select one output signal of the analog front end to output to the ADC.
Preferably, the analog switch further comprises an analog buffer, and the output signal of one analog front end is selected by the analog switch and is driven by the analog buffer to be output to the ADC.
Preferably, the data fusion processing module comprises a memory for storing the reference voltage VREFAnd the voltage-up quantized value and the voltage-down quantized value of VREFAnd theoretical values of the boosting translation amount and the reducing translation amount, and the memory adopts a latch structure-based memory array.
Preferably, the reference voltage VREFProvided by an on-chip reference source or directly input off-chip.
Meanwhile, a method for acquiring data by using the rail-to-rail ADC integrated circuit based on the data fusion structure is provided, which comprises the following steps:
(1) the analog front end receives a reference voltage V during initialization of the rail-to-rail ADC integrated circuitREFThe output is output after the voltage is boosted by the voltage boosting translation module, and the output is output after the voltage is reduced by the voltage reducing translation module; the ADC respectively collects the output voltages of the voltage boosting translation module and the voltage reducing translation module, performs analog-to-digital conversion and then sends the quantized values to the data fusion processing module; the data fusion processing module respectively stores the output voltage quantized values of the voltage boosting translation module and the voltage reducing translation module;
(2) analog front-end acquisition analog signal V to be acquired during data acquisitionINThe output is output after the voltage is boosted by the voltage boosting translation module, and the output is output after the voltage is reduced by the voltage reducing translation module; the ADC respectively collects the output voltages of the voltage boosting translation module and the voltage reducing translation module, performs analog-to-digital conversion and then sends the converted output voltages to the data fusion processing module; and the data fusion processing module respectively calculates according to the output voltage quantized values of the voltage boosting translation module and the voltage reducing translation module, and obtains the final quantized value of the input voltage after data fusion.
Compared with the prior art, the invention has the following advantages:
(1) the ADC integrated circuit solves the application bottlenecks of impedance mismatching, full swing amplitude error and the like caused by using a PGA module in the traditional ADC framework, simultaneously greatly reduces the direct current power consumption of an active device, and realizes the same noise performance in a smaller area;
(2) the offset error in the channel is eliminated through a digital domain, and the extra direct current power consumption, the limitation of device matching precision, control logic and the like caused by the traditional analog modulation eliminating method are avoided. The multi-path data fusion and the modulation disappearance are completed in the same step, and the hardware expense is reduced.
(3) The data fusion algorithm is realized by adopting combinational logic and is completed by the simplest addition and subtraction operation. The power consumption, the system complexity and the cost of hardware caused by sequential logic are avoided. And finishing the data fusion operation of each bit in the fastest time, and screening out the final quantization result in real time after the highest-bit data operation is finished.
(4) The analog part circuit of the invention realizes the rail-to-rail data acquisition of high input impedance through voltage deviation.
Drawings
FIG. 1 is a schematic diagram of a rail-to-rail ADC integrated circuit based on a data fusion structure according to the present invention;
FIG. 2 is a schematic diagram of a boost translation module and a buck translation module in an analog front end according to the present invention;
FIG. 3 is a schematic diagram of the multi-path data fusion process according to the present invention.
Detailed Description
In order to meet the requirements of high input impedance and full swing amplitude input signal amplitude in multi-channel ADC acquisition and eliminate the problems of in-channel dynamic range loss, channel consistency reduction and the like caused by the difference of input detuning amount of each channel circuit, the invention provides a rail-to-rail ADC integrated circuit based on a data fusion structure and provides a circuit implementation scheme. According to the invention, firstly, a CMOS source follower is used as an input end of an analog front end, an input signal is subjected to voltage boosting or voltage reducing translation respectively, and after ADC (analog to digital converter) quantization, a data fusion processing module fuses and calculates quantization results of multiple paths of translation voltages to obtain a final quantization result corresponding to an original input signal. On the basis, more functions and performance improvement are realized by using the convenience and richness of digital domain signal processing.
With reference to fig. 1, the rail-to-rail ADC integrated circuit based on the data fusion structure includes an analog front end, an ADC, a data fusion processing module, and the like; the analog front end receives an analog signal V to be acquiredINThe output is output after the voltage is boosted by the voltage boosting translation module, and the output is output after the voltage is reduced by the voltage reducing translation module; the ADC respectively collects the output voltages of the voltage boosting translation module and the voltage reducing translation module, performs analog-to-digital conversion and then sends the converted output voltages to the data fusion processing module; and the data fusion processing module respectively calculates and stores the quantized values of the output voltages of the voltage boosting translation module and the voltage reducing translation module, and obtains the final quantized value of the input voltage after data fusion.
The analog front end receives a reference voltage V at an initialization stageREFReceiving voltage V to be collected in data collection stageINEach voltage is respectively output after being boosted by the boosting translation module and output after being reduced by the reducing translation module; the ADC respectively collects the output voltages of the voltage boosting translation module and the voltage reducing translation module, performs analog-to-digital conversion and then sends the quantized values to the data fusion processing module; and the data fusion processing module stores and processes the output voltage quantized values of the voltage boosting translation module and the voltage reducing translation module respectively.
In one embodiment, the analog front end receives only the analog signal V to be acquiredINThe boost translation module is used for collecting an analog signal VINRespectively outputting X voltages V after boostingIN+VSP1…VIN+VSPXX is more than or equal to 5 and more than or equal to 1; the voltage reduction translation module is used for collecting an analog signal VINRespectively outputting M voltages V after voltage reductionIN-VSN1…VIN-VSNMM is a natural number, and M is more than or equal to 5 and more than or equal to 1; ADC respectively collecting X kinds of voltage VIN+VSP1…VIN+VSPXAnd M voltages VIN-VSN1…VIN-VSNMAnd the data are transmitted to the data fusion processing module after analog-to-digital conversion. The data fusion processing module comprises an arithmetic unit: the operation unit receives X + M translation voltage quantization values output by the ADC, and subtracts the respective boosting translation values stored in advance from the X boosted voltage quantization values to obtain an analog signal VINCorresponding first set of quantized values VINP1…VINPX(ii) a Respectively subtracting the pre-stored respective voltage reduction translation values from the voltage quantization values of the M types of reduced voltages to obtain an analog signal VINCorresponding second set of quantized values VINN1…VINNM。
In another embodiment, the boost translation module translates the reference voltage VREFOr analog signal V to be acquiredINRespectively outputting X voltages V after boostingREF/VIN+VSP1…VREF/VIN+VSPXX is more than or equal to 5 and more than or equal to 1; the voltage reduction translation module is used for collecting an analog signal VINRespectively outputting M voltages V after voltage reductionREF/VIN-VSN1…VREF/VIN-VSNMM is a natural number, and M is more than or equal to 5 and more than or equal to 1; ADC respectively collecting X kinds of voltage VREF/VIN+VSP1…VREF/VIN+VSPXAnd M voltages VREF/VIN-VSN1…VREF/VIN-VSNMAnd the data are transmitted to the data fusion processing module after analog-to-digital conversion.
The data fusion processing module comprises an arithmetic unit: the operation unit receives the reference voltage V outputted by the ADC in the initialization stageREFThe X + M translation voltage quantization values are stored and the voltage V to be collected output by the ADC is received in the data collection stageINRespectively comparing the quantized values of X + M translation voltages with the stored reference voltage VREFIs subtracted from the reference voltage VREFAdding the theoretical quantized values to obtain an analog signal VINCorresponding first set of quantized values V passing through boost shift module pathINP1…VINPXAnd a second set of quantized values V through the buck translation module pathINN1…VINNM。
The data fusion processing module also comprises a data fusion control unit which takes the average value of the first group of quantized values and the second group of quantized values after eliminating abnormal values as the final quantized value of the input voltage.
In one embodiment, when X and M are both 1, the data fusion control unit selects VINN1Or VINP1As the judgment voltage V, if V is more than or equal to V1Then a second set of quantized values is selected; v is less than or equal to V2Then a first set of quantized values is selected; if V2<V<V1Then V isINN1And VINP1Taking the average value as a final voltage quantization value; wherein V1Taking 0.6U-0.8U, V2And taking 0.2U-0.4U, wherein U is the maximum value of the voltage which can be collected by the analog front end.
In the second embodiment, V is setSP1…VSPXAre successively increased in value of VSN1…VSNMAre sequentially increased, and the data fusion control unit selects VINN1Or VINP1As the judgment voltage V, if V is more than or equal to VREFThen a second set of quantized values V is selectedINN1…VINNMCalculating a final quantized value of the input voltage; if V<VREFThen a first set of quantized values V is selectedINP1…VINPXAnd calculating a final quantized value of the input voltage.
If it is not
Figure BDA0001746836150000071
Selection of VINNjJ is more than or equal to 1 and less than or equal to M as the final quantized value of the voltage; if it is not
Figure BDA0001746836150000072
I is more than or equal to 1 and less than or equal to X; if V is VREFSelection of VINN1As the final quantized value of the voltage.
With reference to fig. 2, the boost circuit structure of the boost translation module is: the drain electrode of the first NMOS tube is connected with the positive electrode of the power supply, the grid electrode of the first NMOS tube receives input voltage, and the source electrode of the first NMOS tube is grounded through a first resistor and a first current source; the drain electrode of the second NMOS tube is connected with the positive electrode of the power supply through a second resistor, the grid electrode of the second NMOS tube is connected with the output end of the first operational amplifier circuit, and the source electrode of the second NMOS tube is grounded through a second current source; the second current source is a mirror current source of the first current source; two input ends of the first operational amplifier circuit are respectively connected with the non-grounding ends of the two current sources.
The voltage reduction circuit structure of the voltage reduction translation module is as follows: the drain electrode of the first PMOS tube is grounded, the grid electrode of the first PMOS tube receives input voltage, and the source electrode of the first PMOS tube is connected with the anode of the power supply through a third resistor and a third current source; the drain electrode of the second PMOS tube is grounded through a fourth resistor, the grid electrode of the second PMOS tube is connected with the output end of the second operational amplifier circuit, and the source electrode of the second PMOS tube is connected with the anode of the power supply through a fourth current source; the fourth current source is a mirror current source of the third current source; two input ends of the second operational amplifier circuit are respectively connected with the non-connected power supply ends of the two current sources.
The first operational amplifier circuit and the second operational amplifier circuit can respectively form a first filter circuit and a second filter circuit together with the RC array.
The first and second filter circuits can be realized by 2-order KRC low-pass filters.
The rail-to-rail ADC integrated circuit based on the data fusion structure can further comprise K analog switches, the number of the analog front ends is K, the K analog front ends correspond to K paths of parallel analog signals respectively, and the analog switches select one output signal of the analog front end to be output to the ADC.
The rail-to-rail ADC integrated circuit based on the data fusion structure can further comprise an analog buffer, and the analog switch selects an output signal of an analog front end to be driven by the analog buffer and then output to the ADC.
The data fusion processing module comprises a memory, wherein the memory is used for storing a reference voltage boosting quantization value and a reference voltage reducing quantization value, and the memory adopts a latch structure-based storage array.
Reference voltage VREFThe on-chip reference source may provide or the off-chip direct input.
The rail-to-rail ADC integrated circuit based on the data fusion structure for data acquisition comprises the following steps:
(1) the analog front end receives a reference voltage V during initialization of the rail-to-rail ADC integrated circuitREFThe output is output after the voltage is boosted by the voltage boosting translation module, and the output is output after the voltage is reduced by the voltage reducing translation module; the ADC respectively collects the output voltages of the voltage boosting translation module and the voltage reducing translation module, performs analog-to-digital conversion and then sends a quantized value to the data fusion processing module; the data fusion processing module respectively stores the output voltage quantized values of the voltage boosting translation module and the voltage reducing translation module;
(2) analog front-end acquisition analog signal V to be acquired during data acquisitionINThe output is output after the voltage is boosted by the voltage boosting translation module, and the output is output after the voltage is reduced by the voltage reducing translation module; the ADC respectively collects the output voltages of the voltage boosting translation module and the voltage reducing translation module, performs analog-to-digital conversion and then sends the converted output voltages to the data fusion processing module; the data fusion processing module is used for translating according to the boostingAnd respectively calculating the quantized values of the output voltages of the block and the voltage reduction translation module, and performing data fusion to obtain the final quantized value of the input voltage.
The present invention will be described in detail below with reference to the accompanying drawings.
Example 1
As shown in fig. 1, the voltage translation module includes two basic forms, namely a voltage boosting translation module (P-type) and a voltage reducing translation module (N-type), which are respectively used for upward potential translation and downward potential translation, so as to ensure that input signals can be correctly acquired and quantized when the input signals are close to 0V and power supply voltage or other voltage intervals which are difficult to acquire. For convenience of understanding, the following description is simplified to introduce a two-way data fusion structure based on each of N-type and P-type channels, that is, an N/P two-way module structure in which X and M are both 1.
The ADC integrated circuit in fig. 1 includes 64 analog front-end modules shown, each module is used as an input channel, and each channel can respectively collect different analog input signals. For the analog front end of each input channel, an input signal is firstly processed in parallel by an N/P voltage translation module, wherein the N module takes an NMOS source electrode follower as an input stage and carries out downward translation on the voltage of the input signal; the P-path module takes a PMOS source electrode follower as an input stage, upward translation of voltage is carried out on an input signal, translation voltage quantity is controlled through resistor string voltage division of a current source output constant current flow, so that impedance conversion and input signal amplitude adjustment are achieved, and stray interference is removed through a low-pass filter, so that an analog signal meeting the ADC quantization processing requirement is obtained. Then, the corresponding channel can be gated through the analog switch, and the corresponding input signal to be acquired is quantized; the output signals processed by the analog front ends of all the channels are subjected to analog-to-digital conversion through SAR-ADCs with the same structure to obtain corresponding quantized data; and finally, recovering the two groups of quantization results of each channel into an analog-to-digital conversion result of the quantization period corresponding to the original input signal through a data fusion module.
The structures of the buck translation (N-type) module and the boost translation (P-type) module at each analog front end are shown in fig. 2, the buck translation (N-type) module in the channel is on the left side, and the boost translation (P-type) module is on the right side. The design principle and the working process of the N-type solar cell are specifically explained by taking the N-type as an example. The input signal is applied to the gate end of an NMOS input tube, and a source follower is formed by an NMOS, a resistor and a voltage-controlled reference current source together, the reference of the controlled current source is generated by loading a reference voltage (irrelevant to temperature, voltage fluctuation and process fluctuation) in a chip on the resistor of the same type, therefore, the voltage drop of two ends of the resistor on an N/P source follower branch in a single channel is determined by the resistor ratio and the reference voltage in the chip, and when the translation amount of the analog potential at the front end is determined by the resistor drop of a source follower branch, the stability and the linearity of the translation amount can be ensured. When the specific scheme is implemented, the source follower and the 2-order KRC low-pass filter are designed in a combined mode, and the clamping of equal potential is achieved by using the direct-current gain of the high-precision operational amplifier, namely the potentials of the current source output ends of the two source follower branches are kept consistent. And the drain-source voltages of the NMOS source follow input tubes on the two branches are equal, and the potential difference between the output voltage of the analog front end and the input signal can be ensured to be completely determined by the voltage drop at two ends of the resistor and the process deviation through size optimization and layout design. Meanwhile, the 2-order KRC filter also provides flat passband gain and a-40 dB/dec stop band roll-off rate, and the effective bandwidth and the noise power of signals are ensured.
The present invention proposes a multi-path data fusion processing working process as shown in fig. 3: the main idea of the algorithm is to use the input signal and a fixed reference potential VREFThe difference between these values is taken as the scaling of the signal, not the absolute value of the input signal. And eliminating the DC offset voltage in each channel by adopting a CDS-like processing process. In the initial calibration stage, each channel processes the same reference voltage input signal, and the quantized data containing the offset information of each channel can be obtained on the basis of ensuring the performance of the SAR-ADC. A single channel corresponds to multiple quantization results (in FIG. 3, each N/P channel is illustrated), i.e., VREFRespectively translated to VREF+VSPAnd VREF－VSNAnd quantizing them respectively, and storing them in chip to complete the initialization calibration work in one period, in this embodiment, 64 input channels are shared, and each channel hasComprises N/P two-way voltage translation modules, thus 64 groups of VREF+VSPAnd VREF－VSNThe quantized values, i.e., 128 reference voltage quantized values, need to be stored for calibration of each channel. In the data acquisition and quantization stage, each channel independently processes respective input signals, the analog switch gates the corresponding acquisition channel, and the corresponding channel simulates the N/P two-path translation result of the front end, namely VIN+VSPAnd VIN－VSNQuantized by ADC and stored in 64 groups of VREF+VSPAnd VREF－VSNSelecting one group of the quantization values corresponding to the channels, reading the selected group of quantization values into a bus, and comparing the selected group of quantization values with VIN+VSPAnd VIN－VSNThe quantized value is subtracted to obtain the difference value of the input signal of the current quantization period of the channel relative to the reference potential, namely (V)IN－VREF)PAnd (V)IN－VREF)NFinally, the two difference values are respectively summed with the theoretical quantized value of the reference voltage input in the calibration stage to obtain a first quantized value V passing through the path of the boosting translation moduleINPAnd a second quantized value V via a buck shift pathINN(ii) a Judging the obtained second quantized value VINNWhether or not [ U/2, U ] is present]Within the voltage interval, if within the interval, V is selectedINNAs final quantization value, otherwise, V is selectedINPAs a final quantized value; or when VINNWhen in the interval of (0.4U, 0.6U), (V) is calculatedINP+VINN) And/2 is used as the final quantization value to improve the linearity of the quantization result, and V is used as the voltage interval above or below the voltage intervalINNAnd VINPAs a final quantization result. The data fusion mode also realizes the elimination of channel direct current offset and the calibration of channel consistency: on one hand, the actual voltage translation amount may deviate from the design value, but the difference value between the reference voltage and the translation amount of the signal to be measured after the reference voltage is subjected to the same translation transformation is measured, so that the deviation influence of the voltage translation amount can be eliminated; on the other hand, due to the non-ideal effect, the analog front ends of the 64 input channels are deviated from each other, and the reference voltage is translated through the analog front ends of the channelsThe quantized values are stored for calibration, so that errors among channels can be eliminated, and the consistency of the channels is improved. Therefore, V can be directly used without initial calibration in implementation, namely, the quantized value of the reference voltage is not storedIN+VSPAnd VIN－VSNThe design values of the translation voltage are respectively subtracted and added for correction, and the quantization result is obtained, but the precision of the quantization result is lower than that of the quantization result subjected to the initialization calibration.
The analog processing part in fig. 3 mainly performs the task of adjusting the potential to meet the requirement of the signal processing range of the power supply system. And the digital processing part is used for finishing the tasks of quantization, storage and data fusion of the output of the front-end processing module. The in-chip offset data storage unit structure adopts a Latch structure to realize flexible read-write operation and higher storage density. The ALU shown in fig. 1 is an arithmetic unit of a data fusion algorithm, and includes 4 cascaded 4-bit carry look-ahead adders and a constant addition logic unit, and each operation of the algorithm is implemented to obtain a final quantization result.
Example 2
The track-to-track ADC integrated circuit body structure and workflow based on the data fusion structure in this embodiment are substantially the same as those in embodiment 1, except that there are 2 boost translation modules (P-Type) P1, P2, and 4 buck translation modules (N-Type) N1, N2, N3, N4 in each channel, instead of 1 each in embodiment 1. Suppose that the amounts of boost shifts of P1 and P2 are VSP10.1U and VSP2The amount of the translation for lowering blood pressure was V for N1, N2, N3 and N4, respectively, at 0.2USN1＝0.1U、VSN2＝0.2U、VSN30.3U and VSN4＝0.4U。
Quantizing and fusing the translation voltages to obtain a first group of quantized values VINP1、VINP2And a second set of quantized values VINN1、VINN2、VINN3、VINN4. If the reference voltage V isREFWhen V is 0.5U, V is judged in turnINN1Whether or not it falls within [0.5U, 0.625U ]]、(0.625U，0.75U]、(0.75U，0.875U]、[0.875U，U]Within the interval, if it falls within [0.5U, 0.625U]In, select VINN1As the final quantization value, if it falls onWithin 3 intervals, selecting V respectivelyINN2、VINN3、VINN4As a final quantized value; on the contrary, if VINN1Falling in the interval of [0.25U, 0.5U) or [0, 0.25U), respectively selecting VINP1And VINP2As the final quantized value.
The above description is only for the best mode of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Those skilled in the art will appreciate that the invention may be practiced without these specific details.

Claims (18)

1. A rail-to-rail ADC integrated circuit based on a data fusion structure is characterized by comprising an analog front end, an ADC and a data fusion processing module;
the analog front end receives an analog signal V to be acquiredINThe output is output after the voltage is boosted by the voltage boosting translation module, and the output is output after the voltage is reduced by the voltage reducing translation module;
the ADC respectively collects the output voltages of the voltage boosting translation module and the voltage reducing translation module, performs analog-to-digital conversion and then sends the converted output voltages to the data fusion processing module;
the data fusion processing module respectively calculates and stores the quantized values of the output voltages of the voltage boosting translation module and the voltage reducing translation module, and obtains the final quantized value of the input voltage after data fusion;
the boost circuit structure of the boost translation module is as follows: the drain electrode of the first NMOS tube is connected with the positive electrode of the power supply, the grid electrode of the first NMOS tube receives input voltage, and the source electrode of the first NMOS tube is grounded through a first resistor and a first current source; the drain electrode of the second NMOS tube is connected with the positive electrode of the power supply through a second resistor, the grid electrode of the second NMOS tube is connected with the output end of the first operational amplifier circuit, and the source electrode of the second NMOS tube is grounded through a second current source; the second current source is a mirror current source of the first current source; two input ends of the first operational amplifier circuit are respectively connected with the non-grounding ends of the two current sources.
2. The data fusion architecture-based rail-to-rail ADC integrated circuit of claim 1, wherein the boost translation module is to collect the analog signal V to be collectedINRespectively outputting X voltages V after boostingIN+VSP1…VIN+VSPXX is more than or equal to 5 and more than or equal to 1; the voltage reduction translation module is used for collecting an analog signal VINRespectively outputting M voltages V after voltage reductionIN-VSN1…VIN-VSNMM is a natural number, and M is more than or equal to 5 and more than or equal to 1; ADC respectively collecting X kinds of voltage VIN+VSP1…VIN+VSPXAnd M voltages VIN-VSN1…VIN-VSNMAnd the data are transmitted to a data fusion processing module after analog-to-digital conversion.
3. The data fusion architecture-based rail-to-rail ADC integrated circuit of claim 2, wherein the data fusion processing module comprises an arithmetic unit: the operation unit receives X + M translation voltage quantization values output by the ADC, and subtracts the stored boosting translation values from the X boosted voltage quantization values to obtain an analog signal VINCorresponding first set of quantized values VINP1…VINPX(ii) a Respectively adding the quantized values of the M types of reduced voltages to the stored reduced voltage translation values to obtain an analog signal VINCorresponding second set of quantized values VINN1…VINNM。
4. The data fusion architecture based rail-to-rail ADC integrated circuit of claim 2, wherein the analog front end receives a reference voltage V during an initialization phaseREFReceiving voltage V to be collected in data collection stageINThe received voltage is respectively output after being boosted by the boosting translation module and output after being reduced by the reducing translation module; the ADC respectively collects the output voltages of the voltage boosting translation module and the voltage reducing translation module, performs analog-to-digital conversion and then sends the quantized values to the data fusion processing module; and the data fusion processing module stores and processes the output voltage quantized values of the voltage boosting translation module and the voltage reducing translation module respectively.
5. The data fusion architecture-based rail-to-rail ADC integrated circuit of claim 4, wherein the boost shift module shifts the reference voltage V during an initialization phaseREFRespectively outputting X voltages V after boostingREF+VSP1…VREF+VSPXX is more than or equal to 5 and more than or equal to 1; the voltage reduction translation module converts the reference voltage V into a voltageREFRespectively outputting M voltages V after voltage reductionREF-VSN1…VREF-VSNMM is a natural number, and M is more than or equal to 5 and more than or equal to 1; ADC respectively collecting X kinds of voltage VREF+VSP1…VREF+VSPXAnd M voltages VREF-VSN1…VREF-VSNMAnd after analog-to-digital conversion, the data are sent to a data fusion processing module for storage.
6. The data fusion architecture-based rail-to-rail ADC integrated circuit of claim 5, wherein the data fusion processing module comprises an arithmetic unit: receiving voltage V to be acquired output by ADC in data acquisition stageINRespectively comparing the quantized values of the X + M translation voltages with the stored corresponding reference voltages VREFIs subtracted from the reference voltage VREFAdding the theoretical quantized values to obtain an analog signal VINCorresponding first set of quantized values V passing through boost shift module pathINP1…VINPXAnd a second set of quantized values V through the buck translation module pathINN1…VINNM。
7. The data fusion architecture-based rail-to-rail ADC integrated circuit of claim 6, wherein the data fusion processing module comprises a data fusion control unit, wherein the first group of quantized values and the second group of quantized values are subjected to elimination of abnormal values and then are averaged to be used as the final quantized value of the input voltage.
8. The rail-to-rail ADC integrated circuit based on data fusion structure of claim 7, wherein X and M are both 1, the data fusion processing module comprises a data fusion control unit,selection of VINN1Or VINP1As the judgment voltage V, if V is more than or equal to V1Then a second set of quantized values is selected; v is less than or equal to V2Then a first set of quantized values is selected; if V2<V<V1Then V isINN1And VINP1Taking the average value as a final voltage quantization value; wherein V1Taking 0.6U-0.8U, V2And taking 0.2U-0.4U, wherein U is the maximum value of the voltage which can be collected by the analog front end.
9. The data fusion architecture-based rail-to-rail ADC integrated circuit of claim 6, wherein VgSP1…VSPXAre successively increased in value of VSN1…VSNMThe data fusion processing module comprises a data fusion control unit and selects VINN1Or VINP1As the judgment voltage V, if V is larger than or equal to VREFThen a second set of quantized values V is selectedINN1…VINNMCalculating a final quantized value of the input voltage; if V<VREFThen a first set of quantized values V is selectedINP1…VINPXAnd calculating a final quantized value of the input voltage.
10. The data fusion architecture-based rail-to-rail ADC integrated circuit of claim 9, wherein if
Figure FDA0003534816380000031
Selection of VINNjJ is more than or equal to 1 and less than or equal to M as the final quantized value of the voltage; if it is not
Figure FDA0003534816380000032
Selection of VINPiAs a voltage final quantized value; if V is VREFSelecting VINN1As the final quantized value of the voltage.
11. The data fusion architecture-based rail-to-rail ADC integrated circuit of claim 10, wherein the voltage reduction circuit architecture of the voltage reduction translation module is: the drain electrode of the first PMOS tube is grounded, the grid electrode of the first PMOS tube receives input voltage, and the source electrode of the first PMOS tube is connected with the anode of the power supply through a third resistor and a third current source; the drain electrode of the second PMOS tube is grounded through a fourth resistor, the grid electrode of the second PMOS tube is connected with the output end of the second operational amplifier circuit, and the source electrode of the second PMOS tube is connected with the positive electrode of the power supply through a fourth current source; the fourth current source is a mirror current source of the third current source; two input ends of the second operational amplifier circuit are respectively connected with the non-connected power supply ends of the two current sources.
12. The data fusion architecture-based rail-to-rail ADC integrated circuit of claim 11, wherein the first and second operational amplifier circuits respectively form the first and second filter circuits with the RC array.
13. The data fusion architecture-based rail-to-rail ADC integrated circuit of claim 12, wherein the first and second filtering circuits are implemented using 2 nd order KRC low pass filters.
14. The data fusion architecture based rail-to-rail ADC integrated circuit of claim 13, further comprising K analog switches, wherein the K analog front ends respectively correspond to K parallel analog signals, and the analog switch selects an output signal of one analog front end to output to the ADC.
15. The data fusion architecture-based rail-to-rail ADC integrated circuit of claim 14, further comprising an analog buffer, wherein the analog switch selects an output signal of the analog front end to be driven by the analog buffer and then output to the ADC.
16. The data fusion architecture-based rail-to-rail ADC integrated circuit of claim 15, wherein: the data fusion processing module comprises a memory for storing a reference voltage VREFAnd the voltage-up quantized value and the voltage-down quantized value of VREFAnd theoretical values of the boosting translation amount and the reducing translation amount, and the memory adopts a latch structure-based memory array.
17. According toThe data fusion architecture-based rail-to-rail ADC integrated circuit of claim 16, wherein: reference voltage VREFProvided by an on-chip reference source or directly input off-chip.
18. A method for data acquisition using the rail-to-rail ADC integrated circuit based on the data fusion structure of claim 17, comprising the steps of:
(1) the analog front end receives a reference voltage V during initialization of the rail-to-rail ADC integrated circuitREFThe output is output after the voltage is boosted by the voltage boosting translation module, and the output is output after the voltage is reduced by the voltage reducing translation module; the ADC respectively collects the output voltages of the voltage boosting translation module and the voltage reducing translation module, performs analog-to-digital conversion and then sends the quantized values to the data fusion processing module; the data fusion processing module respectively stores the output voltage quantized values of the voltage boosting translation module and the voltage reducing translation module;
(2) analog front-end acquisition analog signal V to be acquired during data acquisitionINThe output is output after the voltage is boosted by the voltage boosting translation module, and the output is output after the voltage is reduced by the voltage reducing translation module; the ADC respectively collects the output voltages of the voltage boosting translation module and the voltage reducing translation module, performs analog-to-digital conversion and then sends the converted output voltages to the data fusion processing module; and the data fusion processing module respectively calculates according to the output voltage quantized values of the voltage boosting translation module and the voltage reducing translation module, and obtains the final quantized value of the input voltage after data fusion.
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