CN109103250A - Semiconductor devices and its manufacturing method - Google Patents
Semiconductor devices and its manufacturing method Download PDFInfo
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- CN109103250A CN109103250A CN201810333608.4A CN201810333608A CN109103250A CN 109103250 A CN109103250 A CN 109103250A CN 201810333608 A CN201810333608 A CN 201810333608A CN 109103250 A CN109103250 A CN 109103250A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 179
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 230000004888 barrier function Effects 0.000 claims abstract description 126
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 64
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 23
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 32
- 230000007704 transition Effects 0.000 claims description 23
- 238000002955 isolation Methods 0.000 claims description 4
- 230000005684 electric field Effects 0.000 abstract description 23
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910021334 nickel silicide Inorganic materials 0.000 abstract description 7
- 150000001875 compounds Chemical class 0.000 abstract description 6
- 238000004891 communication Methods 0.000 abstract description 3
- 230000002829 reductive effect Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 403
- 239000000463 material Substances 0.000 description 25
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 20
- 230000008569 process Effects 0.000 description 16
- 239000010936 titanium Substances 0.000 description 16
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 14
- 238000010586 diagram Methods 0.000 description 14
- 229910052581 Si3N4 Inorganic materials 0.000 description 13
- 239000010931 gold Substances 0.000 description 13
- 238000001259 photo etching Methods 0.000 description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 13
- 229910002601 GaN Inorganic materials 0.000 description 12
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 12
- 239000010948 rhodium Substances 0.000 description 12
- 229910052782 aluminium Inorganic materials 0.000 description 10
- 239000004411 aluminium Substances 0.000 description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 239000000758 substrate Substances 0.000 description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 8
- 229910052719 titanium Inorganic materials 0.000 description 8
- 229910052738 indium Inorganic materials 0.000 description 7
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 7
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 6
- 229910000480 nickel oxide Inorganic materials 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052703 rhodium Inorganic materials 0.000 description 6
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 6
- 238000001755 magnetron sputter deposition Methods 0.000 description 5
- 238000007738 vacuum evaporation Methods 0.000 description 5
- 230000000903 blocking effect Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000003292 glue Substances 0.000 description 4
- 229910052697 platinum Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- GNRSAWUEBMWBQH-UHFFFAOYSA-N oxonickel Chemical compound [Ni]=O GNRSAWUEBMWBQH-UHFFFAOYSA-N 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 238000005036 potential barrier Methods 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- IWBUYGUPYWKAMK-UHFFFAOYSA-N [AlH3].[N] Chemical compound [AlH3].[N] IWBUYGUPYWKAMK-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000012010 growth Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 238000004549 pulsed laser deposition Methods 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 206010010144 Completed suicide Diseases 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000000875 corresponding effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- -1 gallium class compound Chemical class 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 230000007773 growth pattern Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009776 industrial production Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- GQYHUHYESMUTHG-UHFFFAOYSA-N lithium niobate Chemical compound [Li+].[O-][Nb](=O)=O GQYHUHYESMUTHG-UHFFFAOYSA-N 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000010606 normalization Methods 0.000 description 1
- 230000005501 phase interface Effects 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910001404 rare earth metal oxide Inorganic materials 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
- H01L29/475—Schottky barrier electrodes on AIII-BV compounds
Abstract
The present invention provides a kind of semiconductor devices and its manufacturing method.The semiconductor devices includes: semiconductor layer；Source electrode and drain electrode positioned at the semiconductor layer side；It is located remotely from the barrier layer of the semiconductor layer side, the barrier layer includes silicide；The barrier layer is 10nm or more close to the distance of the interface distance semiconductor layer of semiconductor layer side；Grid between the source electrode and drain electrode, the grid runs through the barrier layer, the grid includes the first conductting layer and the second conductting layer, first conductting layer is close to the semiconductor layer, second conductting layer is located at the side far from the semiconductor layer of first conductting layer, and first conductting layer includes nickel.The semiconductor devices realizes the electric field strength reduced at nickel silicide generation position by the distance for increasing siliceous compound barrier layer interface to semiconductor layer, has low electric leakage of the grid, high reliability, and is not in the phenomenon that current collapse deteriorates, and is suitable for communication system.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its manufacturing method.
Background technique
The dielectric breakdown field of third generation semiconductor material gallium nitride (GaN) be significantly larger than first generation semiconductor silicon (Si) or
The dielectric breakdown field of second generation Semiconductor GaAs (GaAs), value are up to 3MV/cm, and the electronic device of the material is enable to hold
By very high electric field strength.Meanwhile gallium nitride (GaN) can be with other gallium class compound semiconductors (for example, group III-nitride
Semiconductor) form heterojunction structure.Since III nitride semiconductor has strong piezoelectricity and spontaneous polarization effect,
It can form the very high two-dimensional electron gas of electron concentration (2DEG) channel near the interface of hetero-junctions, and this heterogeneous
Ionized impurity scattering can be also effectively reduced in junction structure, therefore the electron mobility in channel greatly promotes.In this heterojunction structure
On the basis of manufactured GaN high electron mobility transistor can high-frequency be connected high current, and have very low electric conduction
Resistance.Above-mentioned characteristic makes GaN high electron mobility transistor big suitable for manufacture high-frequency high-power radio-frequency devices and high voltage
The switching device of electric current.
In GaN high electron mobility transistor manufacture craft, the grid of GaN high electron mobility transistor is
Have schottky metal-semiconductor contact of rectification characteristic, metal used needs higher work function, as nickel (Ni), platinum (Pt),
Golden (Au).Because nickel (Ni) and the adhesiveness of semiconductor material are preferable, it is ensured that grid metal will not fall off in stripping technology, lead to
Often nickel (Ni) is contacted as the underlying metal of grid with semiconductor material.In device work, born between grid and drain electrode
High pressure, in grid, close to the fringe region of drain electrode, there are peak electric fields, cause device grids electric current to increase, so as to cause reliability
It reduces.In T-type gate fabrication process, barrier layer is used as usually using silicon nitride (SiN).In above-mentioned device manufacture method, Xiao
Special Base Metal-semiconductor contact edge contacts the nickel silicide (NiSi) that will form compared with low work function, nickel with silicon nitride barrier
The region that silicide (NiSi) is contacted with semiconductor material forms the Schottky contacts of high reverse leakage characteristic.When high-pressure work,
Nickel silicide (NiSi), which generates, becomes leak channel because bearing high electric field at position, so that electric leakage of the grid increases, then causes
The problem of reliability.
The existing method for inhibiting HEMT devices to form nickel silicide (NiSi) is on the side nickel (Ni)
Edge makes nickel oxide (NiO), avoids nickel (Ni) from contacting with silicon nitride (SiN) by using nickel oxide (NiO), to avoid nisiloy
Compound (NiSi) generates.Although this method can reduce the electric leakage of the grid of device, nickel oxide (NiO) manufacture craft can increase
Add the current collapse of device, [application No. is 201410486993.8 for ginseng using additional technique to inhibit current collapse also to need
And application No. is two patents of 201010226347.X], increase process complexity.
Summary of the invention
In view of this, the purpose of the present invention is to provide a kind of semiconductor devices and its manufacturing method, to solve above-mentioned ask
Topic.
To achieve the above object, the invention provides the following technical scheme:
A kind of semiconductor devices, comprising:
Semiconductor layer；
Source electrode and drain electrode positioned at the semiconductor layer side；
It is located remotely from the barrier layer of the semiconductor layer side, the barrier layer includes silicide；
Grid between the source electrode and drain electrode, the grid run through the barrier layer, and the grid includes first
Conductting layer and the second conductting layer, first conductting layer are located at described first close to the semiconductor layer, second conductting layer
The side far from the semiconductor layer of conductting layer, first conductting layer includes nickel；
The barrier layer is 10nm or more close to the distance of the interface distance semiconductor layer of semiconductor layer side.
Preferably, the barrier layer is 110nm or less close to the distance of the interface distance semiconductor layer of semiconductor layer side.
Preferably, cap layer is equipped between the barrier layer and semiconductor layer, and to directly overlay cap layer remote on barrier layer
Side from semiconductor layer, the cap layer with a thickness of 10nm or more.
Preferably, the cap layer with a thickness of 90nm or less.
Preferably, interval is pre- between the surface and the barrier layer far from the semiconductor side of first conductting layer
If distance, contact first conductting layer not with the barrier layer.
Preferably, the grid further includes the transition zone between first conductting layer and the second conductting layer, described
First conductting layer is isolated by the transition zone with the barrier layer.
Preferably, a part on the surface of the separate semiconductor layer side on the barrier layer is covered with first conducting
Layer.
Preferably, the grid through the barrier layer and extends to the cap layer inside or the semiconductor layer.
A kind of manufacturing method of semiconductor devices, which comprises
Semi-conductor layer is provided；
Source electrode and drain electrode is formed in the semiconductor layer side；
The barrier layer including silicide is being formed far from the semiconductor layer side, and is making the barrier layer is close partly to lead
The distance of the interface distance semiconductor layer of body layer side is 10nm or more；
The grid including the first conductting layer and the second conductting layer is formed between the source electrode and drain electrode；
Wherein, the grid runs through the barrier layer, and first conductting layer is led close to the semiconductor layer, described second
Logical layer is located at the side far from the semiconductor layer of first conductting layer, and first conductting layer includes nickel.
Preferably, the barrier layer is 110nm or less close to the distance of the interface distance semiconductor layer of semiconductor layer side.
Preferably, cap layer is made between the barrier layer and semiconductor layer, and barrier layer directly overlays cap layer
Far from semiconductor layer side, the cap layer with a thickness of 10nm or more.
Preferably, interval is pre- between the surface and the barrier layer far from the semiconductor side of first conductting layer
If distance, contact first conductting layer not with the barrier layer.
Preferably, described that the grid including the first conductting layer and the second conductting layer is formed between the source electrode and drain electrode
Step includes:
Transition zone is formed between first conductting layer and the second conductting layer, first conductting layer passes through the transition
Layer is isolated with the barrier layer.
Semiconductor devices provided by the invention and its manufacturing method, by increasing siliceous compound barrier layer interface to semiconductor
The distance of layer realizes the electric field strength reduced at nickel silicide (NiSi) generation position, reduces grating of semiconductor element electric leakage, mentions
The reliability of high device.Semiconductor devices provided by the invention has low electric leakage of the grid, high reliability, and is not in that electric current collapses
It collapses the phenomenon that deteriorating, is suitable for communication system.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be to needed in the embodiment attached
Figure is briefly described.It should be appreciated that the following drawings illustrates only certain embodiments of the present invention, therefore it is not construed as pair
The restriction of range for those of ordinary skill in the art without creative efforts, can also be according to this
A little attached drawings obtain other relevant attached drawings.
Fig. 1 is a kind of structural schematic diagram for semiconductor devices that the embodiment of the present invention one provides.
Fig. 2 is that the nickel silicide for the semiconductor devices that the embodiment of the present invention one provides generates electric field strength and resistance at position
Relational graph of the barrier close to the distance of the interface distance semiconductor layer of semiconductor layer.
Fig. 3 is a kind of structural schematic diagram of semiconductor devices provided by Embodiment 2 of the present invention.
Fig. 4 is a kind of structural schematic diagram for semiconductor devices that the embodiment of the present invention three provides.
Fig. 5 is a kind of structural schematic diagram for semiconductor devices that the embodiment of the present invention four provides.
Fig. 6 is a kind of flow chart of the manufacturing method of semiconductor devices provided in an embodiment of the present invention.
Fig. 6-1 is the structural schematic diagram for implementing the semiconductor layer manufactured after step S101 shown in fig. 6.
Fig. 6-2 is to implement step S102 shown in fig. 6 to form the structural schematic diagram after cap layer.
Fig. 6-3 is to implement step S103 shown in fig. 6 to form the structural schematic diagram after source electrode and drain electrode.
Fig. 6-4 is to implement step S104 shown in fig. 6 to form the structural schematic diagram behind barrier layer.
Fig. 6-5 is the flow chart for the sub-step that step S105 shown in fig. 6 includes.
Fig. 6-5-1 is to implement sub-step S1051 shown in Fig. 6-5 to form the structural schematic diagram after grid slot.
Fig. 7 is a kind of structural schematic diagram for semiconductor devices that the embodiment of the present invention five provides.
Icon: 100- semiconductor devices；110- semiconductor layer；120- cap layer；130- source electrode；140- drain electrode；150- resistance
Barrier；160- grid；111- substrate；112- buffer layer；113- channel layer；114- barrier layer；The first conductting layer of 161-；163-
Two conductting layers；165- transition zone；167- grid slot.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description.Obviously, described embodiment is only a part of the embodiments of the present invention, instead of all the embodiments.It is logical
The component for the embodiment of the present invention being often described and illustrated herein in the accompanying drawings can be arranged and be designed with a variety of different configurations.
Therefore, the detailed description of the embodiment of the present invention provided in the accompanying drawings is not intended to limit below claimed
The scope of the present invention, but be merely representative of selected embodiment of the invention.Based on the embodiment of the present invention, those skilled in the art
Member's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
It should also be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, does not then need that it is further defined and explained in subsequent attached drawing.In description of the invention
In, term " first ", " second " etc. are only used for distinguishing description, and should not be understood as only or imply relative importance.
Embodiment one
Referring to Fig. 1, the embodiment of the present invention one provides a kind of semiconductor devices 100.The semiconductor devices 100 includes:
Semiconductor layer 110, cap layer 120, source electrode 130, drain electrode 140, barrier layer 150 and grid 160.
Semiconductor layer 110 can be the single, double or multi-layer structure being made of one or more semiconductor materials.One
In kind embodiment, the semiconductor layer 110 includes: substrate 111, buffer layer 112, channel layer 113 and barrier layer 114.Ying Li
Solution, in other embodiments or other semiconductor structures, the semiconductor layer 110 can also include more or fewer levels.
Substrate 111 plays a part of to support buffer layer 112.Substrate 111 can be by sapphire (Sapphire), silicon carbide
(SiC), silicon (Si), lithium niobate, rare earth oxide, gallium nitride (GaN) or any other suitable material are made.For example, substrate
111 can be made of the good silicon carbide of heat dissipation characteristics (SiC).
The buffer layer 112 is located at 111 side of substrate.Buffer layer 112 plays a part of to bond channel layer 113, and
Substrate 111 is protected not invaded by some metal ions.The buffer layer 112 is by aluminium gallium nitrogen (InAlGaN), aluminum gallium nitride
(AlGaN), at least one of indium aluminium nitrogen (InAlN), aluminium nitrogen (AlN), gallium nitride (GaN) and other semiconductor materials material system
At.For example, the buffer layer 112 is gallium nitride (GaN) layer or controllable aluminum gallium nitride (AlGaN) layer of aluminium content.
The channel layer 113 is located at separate 111 side of substrate of the buffer layer 112, to provide Two-dimensional electron
The channel of gas (Two Dimensional Electron Gas, 2DEG) movement.The channel layer 113 can be mixed for undoped, N-shaped
GaN, Al that miscellaneous or N-shaped locally adulteratesxGa1-xN、InxAl1-xOne of N or AlN or a variety of, 0 < x < 1.For example, the ditch
Channel layer 113 is the GaN layer of unintentional doping.
The barrier layer 114 is located at the side far from the buffer layer 112 of the channel layer 113, plays the work of potential barrier
With the carrier in blocking channel layer 113 flows to barrier layer 114.The barrier layer 114 can be AlyGa1-yN、InyAl1-yN or
One of AlN or a variety of, 0 < y < 1.For example, the barrier layer 114 is aluminum gallium nitride (AlGaN) layer of unintentional doping.Institute
It states channel layer 113 and the combination of barrier layer 114 forms heterojunction structure.
Cap layer 120 is made based on the semiconductor layer 110, positioned at the one of the separate channel layer 113 of the barrier layer 114
Side.Cap layer 120 can reduce the ohmic contact resistance of source electrode 130 and drain electrode 140, improve the electron transfer of 2DEG in channel
Rate, the contact berrier for increasing by 160 Schottky of grid, in addition cap layer 120 can also play the role of insulation and passivation.In one kind
In embodiment, the cap layer 120 is gallium nitride (GaN) layer or aluminum gallium nitride (AlGaN) layer.
Source electrode 130 and drain electrode 140 are located at 110 side of semiconductor layer, such as can be located at the semiconductor layer 110
The side of the separate channel layer 113 of barrier layer 114.Optionally, in the present embodiment, source electrode 130 and drain electrode 140 are made in respectively
The opposite sides of barrier layer 114.The contact type of source electrode 130 and barrier layer 114 is Ohmic contact, drain electrode 140 and barrier layer 114
Contact type be Ohmic contact.The source electrode 130 and drain electrode 140 can be by nickel (Ni), aluminium (Al), titanium (Ti), golden (Au)
It is made etc. one or more metal materials.
The barrier layer 150 is located at separate 110 side of semiconductor layer of the cap layer 120, plays and realizes T-type grid
The effect of pole 160 and passivation 120 surface state of cap layer.The barrier layer 150 includes silicide, such as silicon nitride (SiN).It is described
The thickness on barrier layer 150 may be, but not limited to, greater than 20nm.Preferably, the barrier layer 150 is the silicon nitride of 50nm thickness
(SiN) layer.
In example 1, as described in Figure 1, cap layer 120 is made based on the semiconductor layer 110, is located at the potential barrier
The side of the separate channel layer 113 of layer 114, the cap layer and barrier layer 150 directly contact.Cap layer 120 can reduce source
The ohmic contact resistance of pole 130 and drain electrode 140 improves the electron mobility of 2DEG in channel, increases connecing for 160 Schottky of grid
Potential barrier is touched, in addition cap layer 120 can also play the role of insulation and passivation.In example 1, the barrier layer 150 is direct
Cap layer 120 is covered on far from semiconductor layer side, the cap layer 120 can be gallium nitride (GaN) layer or aluminum gallium nitride
(AlGaN) layer.
The grid 160 is located between the source electrode 130 and drain electrode 140, and the grid 160 runs through the barrier layer 150
Extend to 120 inside of cap layer or the semiconductor layer 110.In example 1, the grid 160 extends to institute
Semiconductor layer 110 is stated, i.e., the described grid 160 extends to the semiconductor layer 110 through the cap layer 120.The grid
160 can be T-type grid structure.In the present embodiment, the grid 160 includes the first conductting layer 161 and the second conductting layer 163, institute
The first conductting layer 161 is stated close to the semiconductor layer 110, first conductting layer 161 includes nickel (Ni).First conductting layer 161
The adhesiveness that metal and semiconductor material can be improved is made or is all made using nickel (Ni) using the material of nickeliferous (Ni), so that
Grid 160 is not easy to fall off in stripping technology.In the present embodiment, first conductting layer 161 uses the metal material of nickeliferous (Ni)
Material is made, and forms the underlying metal structure of grid 160.The contact type of the grid 160 is schottky metal-semiconductor interface
Touching.Second conductting layer 163 is located at the side far from the semiconductor layer 110 of first conductting layer 161.Described
Two conductting layers 163 can be to be made of one of golden (Au), rhodium (Rh), indium (In), aluminium (Al), titanium (Ti) or multiple material.
Second conductting layer 163 can reduce the resistance of grid 160, improve the electric conductivity of grid 160.
When silicon nitride (SiN) in first conductting layer 161 in nickel (Ni) and barrier layer 150 contacts, contact position will form compared with
The nickel silicide (NiSi) of low work function.The region that the nickel silicide (NiSi) is contacted with semiconductor material forms high reversed leakage
The Schottky contacts of electrical characteristics, the size of Schottky contacts reverse leakage and the electric field strength in this region are positively correlated herein.Nisiloy
Compound (NiSi) generates the electric field strength formula at position are as follows:
In formula, E is the electric field strength at nickel silicide (NiSi) generation position；For barrier layer 114 and 120 interface of cap layer
The electric field at place, size are related with the polarized electric field intensity in barrier layer 114；T is the close semiconductor layer 110 on barrier layer 150
Interface distance semiconductor layer 110 distance (i.e. nickel silicide (NiSi) generate positional distance semiconductor layer distance)；A is
The value of equation coefficient, different process flow a is different.
The electric field that nickel silicide (NiSi) generates at position when to different distance T is emulated, the nisiloy after normalization
The electric field strength that compound (NiSi) generates at position is as shown in Figure 2 with the variation of distance T.As seen from Figure 2, when distance T is
When 10nm, nickel silicide (NiSi) generates 10% that the electric field E at position is, and electric field strength at this time has been not enough to cause bright
Aobvious grid 160 leaks electricity.When distance T is 90nm, nickel silicide (NiSi) generates 1% that the electric field E at position is, continues to increase
Distance T greatly, the electric field change that nickel silicide (NiSi) generates at position are slow.
Preferably, the distance T of the interface distance semiconductor layer 110 of the close semiconductor layer 110 on barrier layer 150 is in 10nm-
Between 110nm, technology difficulty and device manufacture area can reduce in this way, to be more advantageous to industrial production and manufacturing.More preferably
Ground, the distance of the interface distance semiconductor layer 110 of the close semiconductor layer 110 on barrier layer 150 is between 15nm-55nm, in this way
The electric field E that nickel silicide (NiSi) can be made to generate at position is approximately less than E05%, further increase device reliability.
In example 1, the barrier layer 150 of siliceous compound directly overlays in cap layer 120, at this point, barrier layer 150
Close semiconductor layer 110 interface distance semiconductor layer 110 distance be equal to cap layer 120 thickness.It is preferred that cap layer
120 thickness are in 10nm between 110nm.In addition, on the basis of giving full play to cap layer effect, from reduction electric leakage and technique
From the point of view of manufacture, preferably the thickness of cap layer 120 is in 10nm between 90nm.It is further preferred that cap layer 120 with a thickness of
The cap layer 120 of 20nm to 40nm, the thickness can not only sufficiently reduce electric leakage, and be easier to technique realization.Such as work as lid
Cap layers 120 with a thickness of 28nm when, nickel silicide (NiSi) generates 3.5% that the electric field strength E at position is, and 28nm is thick
The cap layer 120 of degree is easier to technique realization.
In example 1, as described in Figure 1, cap layer 120 is provided between barrier layer 150 and semiconductor layer 110, and
Barrier layer 150 directly overlays in cap layer 120, and still, barrier layer can not also directly overlay in cap layer 120, that is, exists
One or more layers other layer, such as dielectric layer can also be set between cap layer 120 and barrier layer 150.
Alternatively, it is also possible to be not provided with cap layer 120, one layer or more is arranged between barrier layer 150 and semiconductor layer 110
It is scheduled to leave semiconductor layer 110 to ensure barrier layer 150 close to the interface of semiconductor layer 110 for other layers of layer, such as dielectric layer
Distance.
Embodiment two
Fig. 3 is the structural schematic diagram of semiconductor devices 100 provided by Embodiment 2 of the present invention.As shown in figure 3, the present embodiment
It is similar with embodiment one, the difference is that, in embodiment two, the separate semiconductor side of first conductting layer 161
Surface and the barrier layer 150 between be spaced pre-determined distance, connect first conductting layer 161 not with the barrier layer 150
Touching.Pre-determined distance flexible setting according to the actual situation, this is not restricted.In other words, the upper table of the first conductting layer 161
Face is lower than the lower surface on the barrier layer 150.
Compared with embodiment one, pass through the separate institute of the first conductting layer 161 in semiconductor devices 100 shown in embodiment two
It states and is spaced pre-determined distance between the surface of semiconductor side and the barrier layer 150, so that the first conductting layer 161 and the blocking
Layer 150 does not contact, to avoid the silicide on barrier layer 150 from contacting with the nickel (Ni) of the first conductting layer 161 and generate nickel suicide
Object (NiSi), reduces semiconductor devices at the problem of causing nickel silicide (NiSi) to become leak channel because bearing high electric field
The electric leakage of 100 grids 160, the reliability for improving semiconductor devices 100.
3rd embodiment
Fig. 4 is the structural schematic diagram for the semiconductor devices 100 that the embodiment of the present invention three provides.As shown in figure 4, the present embodiment
It is similar with embodiment two, the difference is that, in embodiment three, the grid 160 further includes being located at first conductting layer 161
And the second transition zone 165 between conductting layer 163, first conductting layer 161 pass through the transition zone 165 and the barrier layer
150 isolation.The transition zone 165 can be to be made of the metal of higher work function, such as gold (Au), platinum (Pt).Preferably, exist
In the present embodiment, the transition zone 165 is made of platinum (Pt).
Compared with embodiment one, semiconductor devices 100 shown in embodiment three in the first conductting layer 161 and second by leading
Increase transition zone 165 between logical layer 163, so that first conductting layer 161 passes through the transition zone 165 and the barrier layer
150 isolation, because avoiding and nickel silicide (NiSi) occur and become to leak because bearing high electric field without generation nickel silicide (NiSi)
The problem of electric channel, the reliability for reducing the electric leakage of 100 grid 160 of semiconductor devices, improving semiconductor devices 100.
Example IV
Fig. 5 is the structural schematic diagram for the semiconductor devices 100 that the embodiment of the present invention four provides.As shown in figure 5, the present embodiment
It is similar with embodiment one, the difference is that, in example IV, a part on the barrier layer 150 is covered with described first
Conductting layer 161.In detail, first conductting layer 161 from the barrier layer 114 toward extend to the barrier layer 150 far from
Then one side surface of cap layer 120 up extends shape respectively from the barrier layer 150 close to the both ends of the first conductting layer 161
At the two sidewalls of a part for covering the barrier layer 150 so that a part of the second conductting layer 163 be located at the two sidewalls it
Between, another part is covered on the two sidewalls.
Compared with embodiment one, the realization simple process of semiconductor devices 100 shown in example IV, and nickel silicide
(NiSi) generating the electric field strength at position is not enough to cause apparent grid 160 to leak electricity, and can be improved semiconductor devices 100 can
By property.
Embodiment five
Fig. 7 is the structural schematic diagram for the semiconductor devices 100 that the embodiment of the present invention five provides.As shown in fig. 7, the present embodiment
It is similar with embodiment one, the difference is that, in embodiment five, the grid 160 is not through the cap layer 120, i.e., described
Grid 160 does not extend to the semiconductor layer 110.
Referring to Fig. 6, the embodiment of the invention also provides a kind of 100 manufacturing methods of semiconductor devices, which comprises
Step S101, step S102, step S103, step S104 and step S105.
Step S101 provides semi-conductor layer 110.
As in Figure 6-1, semiconductor layer 110 can be the single layer being made of one or more semiconductor materials, bilayer or
Multilayered structure.For example, the semiconductor layer 110 can be by the substrate 111, buffer layer 112, channel layer 113 and the gesture that stack gradually
Barrier layer 114 is made.Step S102 forms the cap layer 120 with a thickness of 10nm or more in 110 side of semiconductor layer.
As in fig. 6-2, cap layer 120, the nut cap are formed far from the side of the channel layer 113 in barrier layer 114
Layer 120 can be made of gallium nitride (GaN) or aluminum gallium nitride (AlGaN) layer.Preferably, the thickness of the cap layer 120 is in 10nm
To between 110nm.Preferably, the cap layer 120 with a thickness of 10nm to 90nm, more preferably 20nm to 40nm.
Step S103 forms source electrode 130 and drain electrode 140 in the side of the semiconductor layer 110.
As shown in Fig. 6-3, in the present embodiment, source electrode 130 and drain electrode 140, and source can be formed in the two sides of cap layer 120
Pole 130 and drain electrode 140 are electrically connected with the 2DEG formation in channel layer 113.Source electrode 130 and the production method of drain electrode 140 have more
Kind.In the present embodiment, the production method of source electrode 130 and drain electrode 140 are as follows: bottom-up deposit titanium (Ti), aluminium (Al), nickel
(Ni), golden (Au) four layers of metal, form ohm using rapid thermal annealing (Rapid Thermal Annealing, RTA) technique
Characteristic.The meaning of rapid thermal anneal process is, on the one hand forms low resistance nitride in metal semiconductor interface, on the other hand
So that intermetallic phase counterdiffusion, occurs solid phase interface and reacts to form a series of low resistances, low work function and heat-staple metal
Between alloy.
Step S104 forms the barrier layer including silicide far from 110 side of semiconductor layer in the cap layer 120
150, and make the barrier layer close to the interface distance semiconductor layer of semiconductor layer side distance be 10nm or more.
As shown in Fig. 6-4, the barrier layer 150 including silicide is being formed far from 110 side of semiconductor layer, and make
The barrier layer is 10nm or more close to the distance of the interface distance semiconductor layer of semiconductor layer side.Preferably, the blocking
Layer 150 be silicon nitride (SiN), the barrier layer 150 close to 110 side of semiconductor layer interface distance semiconductor layer 110 away from
From for 110nm or less.The growth pattern on barrier layer 150 may be, but not limited to, metallo-organic compound chemical gaseous phase deposition
(Metal-organic Chemical Vapor Deposition, MOCVD), plasma enhanced chemical vapor deposition method
(Plasma Enhanced Chemical Vapor Deposition, PECVD), pulse laser deposit (Pulsed Laser
Deposition, PLD), molecular beam epitaxy (Molecular Beam Epitaxy, MBE) and thermally grown.The barrier layer 150
It can be the medium of single-step process growth, can also be the medium of multi-step process growth.It is highly preferred that the barrier layer 150 is close to half
The distance of the interface distance semiconductor layer 110 of 110 side of conductor layer is 15nm to 55nm.
Step S105, being formed between the source electrode 130 and drain electrode 140 includes the first conductting layer 161 and the second conductting layer
163 grid 160.
It please refers to shown in Fig. 6-5, step S105 includes sub-step S1051 and sub-step S1052.
Sub-step S1051, the barrier layer 150 and cap layer 120 etched between the source electrode 130 and drain electrode 140 form grid
Slot 167.
As shown in Fig. 6-5-1, the barrier layer 150 between the source electrode 130 and drain electrode 140 and the formation of cap layer 120 are etched
Wet etching or dry etching can be used in grid slot 167, etching technics, and 167 etching depth of grid slot is controllable, deep according to design etching
The degree control etching technics time.Preferably, the depth of the grid slot 167 is equal to the thickness of cap layer 120 and the thickness on barrier layer 150
The sum of degree.
Sub-step S1052, deposit includes the grid of the first conductting layer 161 and the second conductting layer 163 on the grid slot 167
160。
In the embodiment shown in fig. 6, barrier layer 150 is directly formed in cap layer 120, at this point, barrier layer 150 is leaned on
The distance of the interface distance semiconductor layer 110 of nearly semiconductor layer 110 is equal to the thickness of cap layer 120.In addition, barrier layer 150
It can not directly form in cap layer 120, i.e., can also form one or more layers between cap layer 120 and barrier layer 150
Other layers, such as dielectric layer.
Alternatively, it is also possible to not form cap layer 120, and between barrier layer 150 and semiconductor layer 110 formed one layer or
Other layers of multilayer, such as dielectric layer are made a reservation for ensuring that semiconductor layer 110 is left close to the interface of semiconductor layer 110 in barrier layer 150
Distance.
It is corresponding with embodiment one, embodiment two, embodiment three, example IV and embodiment five, it is deposited on grid slot 167
The structure of the grid 160 arrived at least can there are five types of, as shown in Fig. 1, Fig. 3, Fig. 4, Fig. 5 and Fig. 7.
A kind of production method of grid 160 shown in FIG. 1 are as follows: form photoetching on grid slot 167 using a step photoetching process
Glue opening area, opening area length are equal to 167 flute length of grid slot, and deposit forms the first conductting layer 161 on grid slot 167, described
First conductting layer 161 is made of the material including nickel (Ni).The upper surface of first conductting layer 161 is higher than the cap layer
120 upper surface is contacted with the barrier layer 150.It reuses a step photoetching process and forms photoresist aperture area on grid slot 167
Domain, opening area length are greater than 167 flute length of grid slot, form the second conductting layer 163 on the first conductting layer 161.Described second leads
Logical layer 163 can be to be made of one of golden (Au), rhodium (Rh), indium (In), aluminium (Al), titanium (Ti) or multiple material.It is described
The forming method of first conductting layer 161 and the second conductting layer 163 can be vacuum evaporation, magnetron sputtering etc..
A kind of production method of grid 160 shown in Fig. 3 are as follows: form photoetching on grid slot 167 using a step photoetching process
Glue opening area, opening area length are equal to 167 flute length of grid slot, form the first conductting layer 161 on grid slot 167, and described first
Conductting layer 161 is made of the material including nickel (Ni).The upper surface of first conductting layer 161 is lower than the barrier layer 150
Lower surface is not contacted with the barrier layer 150.It reuses a step photoetching process and forms photoresist opening area on grid slot 167, open
Porose area length of field is greater than 167 flute length of grid slot, and the second conductting layer 163 is formed on the first conductting layer 161.Second conductting layer
163 can be and be made of one of golden (Au), rhodium (Rh), indium (In), aluminium (Al), titanium (Ti) or multiple material.Described first
The forming method of conductting layer 161 and the second conductting layer 163 can be vacuum evaporation, magnetron sputtering etc..
Grid 160 shown in Fig. 4 further includes the transition between first conductting layer 161 and the second conductting layer 163
Layer 165, first conductting layer 161 are isolated by the transition zone 165 with the barrier layer 150.Therefore sub-step S1052
Further include: transition zone 165 is formed between the first conductting layer 161 and the second conductting layer 163 stating, first conductting layer 161 is logical
The transition zone 165 is crossed to be isolated with the barrier layer 150.A kind of production method of grid 160 shown in Fig. 4 are as follows: use a step
Photoetching process forms photoresist opening area on grid slot 167, and opening area length is equal to 167 flute length of grid slot, on grid slot 167
The first conductting layer 161 is formed, first conductting layer 161 is made of the material including nickel (Ni).First conductting layer 161
Upper surface be lower than the barrier layer 150 lower surface, do not contacted with the barrier layer 150.It was formed on the first conductting layer 161
Cross layer 165.Preferably, the transition zone 165 is made of platinum (Pt) or golden (Au).A step photoetching process is reused in grid slot 167
Upper formation photoresist opening area, opening area length are greater than 167 flute length of grid slot, form the second conductting layer on transition zone 165
163.Second conductting layer 163 can be by one of golden (Au), rhodium (Rh), indium (In), aluminium (Al), titanium (Ti) or a variety of
Material is made.The forming method of first conductting layer 161, transition zone 165 and the second conductting layer 163 can be vacuum evaporation,
Magnetron sputtering etc..
A kind of production method of grid 160 shown in fig. 5 are as follows: form photoetching on grid slot 167 using a step photoetching process
Glue opening area, opening area length are greater than 167 flute length of grid slot, and deposit forms the first conductting layer 161 on grid slot 167, described
First conductting layer 161 is made of the material including nickel (Ni).Since photoresist opening area is greater than 167 flute length of grid slot, the resistance
First conductting layer 161 can be covered in barrier 150, and forms the side wall of first conductting layer 161 in 167 two sides of grid slot.
The second conductting layer 163 is formed on the first conductting layer 161.Second conductting layer 163 can be by gold (Au), rhodium (Rh), indium
(In), one of aluminium (Al), titanium (Ti) or multiple material are made.First conductting layer 161 and the second conductting layer 163
Forming method can be vacuum evaporation, magnetron sputtering etc..
A kind of production method of grid 160 shown in Fig. 7 are as follows: form photoetching on grid slot 167 using a step photoetching process
Glue opening area, opening area length are equal to 167 flute length of grid slot, and deposit forms the first conductting layer 161 on grid slot 167, described
First conductting layer 161 is made of the material including nickel (Ni).The upper surface of first conductting layer 161 is higher than the cap layer
120 upper surface is contacted with the barrier layer 150.The lower surface of first conductting layer 161 has no through the cap layer
120, it is contacted with the cap layer 120.It reuses a step photoetching process and forms photoresist opening area, aperture area on grid slot 167
Length of field is greater than 167 flute length of grid slot, and the second conductting layer 163 is formed on the first conductting layer 161.Second conductting layer 163 can
To be made of one of golden (Au), rhodium (Rh), indium (In), aluminium (Al), titanium (Ti) or multiple material.First conductting layer
161 and second the forming method of conductting layer 163 can be vacuum evaporation, magnetron sputtering etc..
Semiconductor devices 100 provided by the invention, the thickness by improving cap layer 120, which is realized, reduces nickel silicide
(NiSi) electric field strength at position, or surface and blocking by making the separate semiconductor side of the first conductting layer 161 are generated
Layer 150 between be spaced pre-determined distance or between the first conductting layer 161 and the second conductting layer 163 increase transition zone 165 to avoid
The mode for generating nickel silicide (NiSi) reduces the electric leakage of 100 grid 160 of semiconductor devices, improves semiconductor devices 100
Reliability, and be not in the phenomenon that current collapse deteriorates, it is suitable for communication system.
In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, term " setting ", " phase
Even ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected.It can
To be mechanical connection, it is also possible to be electrically connected.It can be directly connected, can also indirectly connected through an intermediary, it can be with
It is the connection inside two elements.For the ordinary skill in the art, it can understand that above-mentioned term exists with concrete condition
Concrete meaning in the present invention.
In the description of the present invention, it is also necessary to explanation, the orientation of the instructions such as term " on ", "lower", "inner", "outside" or
Positional relationship be based on the orientation or positional relationship shown in the drawings or the invention product using when the orientation usually put or
Positional relationship is merely for convenience of description of the present invention and simplification of the description, rather than the device or element of indication or suggestion meaning must
There must be specific orientation, be constructed and operated in a specific orientation, therefore be not considered as limiting the invention.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (12)
1. a kind of semiconductor devices characterized by comprising
Semiconductor layer；
Source electrode and drain electrode positioned at the semiconductor layer side；
Positioned at the barrier layer of the semiconductor layer side, the barrier layer includes silicide；
Grid between the source electrode and drain electrode, the grid run through the barrier layer, and the grid includes the first conducting
Layer and the second conductting layer, for first conductting layer close to the semiconductor layer, second conductting layer is located at first conducting
The side far from the semiconductor layer of layer, first conductting layer includes nickel；
The distance of semiconductor layer described in interface distance of the barrier layer close to the semiconductor layer side is 10nm or more.
2. semiconductor devices according to claim 1, which is characterized in that the barrier layer is close to the semiconductor layer side
Interface distance described in semiconductor layer distance be 110nm or less.
3. semiconductor devices according to claim 1, which is characterized in that set between the barrier layer and the semiconductor layer
There is cap layer, and the barrier layer directly overlays side of the cap layer far from the semiconductor layer, the cap layer
With a thickness of 10nm or more.
4. semiconductor devices according to claim 3, which is characterized in that the cap layer with a thickness of 90nm or less.
5. -4 described in any item semiconductor devices according to claim 1, which is characterized in that first conductting layer it is separate
It is spaced pre-determined distance between the surface and the barrier layer of the semiconductor side, makes first conductting layer and the barrier layer
It does not contact.
6. -4 described in any item semiconductor devices according to claim 1, which is characterized in that the grid further includes being located at institute
The transition zone between the first conductting layer and the second conductting layer is stated, first conductting layer passes through the transition zone and the barrier layer
Isolation.
7. -4 described in any item semiconductor devices according to claim 1, which is characterized in that the barrier layer far from described
The a part on the surface of semiconductor layer side is covered with first conductting layer.
8. semiconductor devices described in -4 according to claim 1, which is characterized in that the grid is through the barrier layer and extends
To the cap layer inside or the semiconductor layer.
9. a kind of manufacturing method of semiconductor devices, which is characterized in that the described method includes:
Semi-conductor layer is provided；
Source electrode and drain electrode is formed in the semiconductor layer side；
The barrier layer including silicide is being formed far from the semiconductor layer side, and the barrier layer is partly led close to described
The distance of semiconductor layer described in the interface distance of body layer side is 10nm or more；
The grid including the first conductting layer and the second conductting layer is formed between the source electrode and drain electrode；
Wherein, the grid runs through the barrier layer, and first conductting layer is close to the semiconductor layer, second conductting layer
Positioned at the side far from the semiconductor layer of first conductting layer, first conductting layer includes nickel.
10. manufacturing method according to claim 9, which is characterized in that between the barrier layer and the semiconductor layer
Cap layer is made, and the barrier layer directly overlays side of the cap layer far from semiconductor layer, the thickness of the cap layer
Degree is 10nm or more.
11. according to described in any item manufacturing methods of claim 9-10, which is characterized in that first conductting layer it is separate
It is spaced pre-determined distance between the surface and the barrier layer of the semiconductor side, makes first conductting layer and the barrier layer
It does not contact.
12. according to described in any item manufacturing methods of claim 9-10, which is characterized in that described in the source electrode and drain electrode
Between formed and include the steps that the grid of the first conductting layer and the second conductting layer includes:
Form transition zone between first conductting layer and the second conductting layer, first conductting layer by the transition zone with
The barrier layer isolation.
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