CN109100635B - Circuit and method for detecting integrity of multi-channel metal shielding wiring layer - Google Patents
Circuit and method for detecting integrity of multi-channel metal shielding wiring layer Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31719—Security aspects, e.g. preventing unauthorised access during test
Abstract
The invention discloses a circuit and a method for detecting the integrity of a multi-channel metal shielding wiring layer. The circuit comprises a random number generation circuit and a signal comparison circuit. The random number generating circuit is used for generating a random number sequence, each random number is transmitted through two transmission channels, and the two transmission channels are the multi-channel metal shielding wiring layer and the lower metal wire of the chip respectively; and the signal comparison circuit compares the random number signals output to the signal comparison circuit by the two transmission channels, and when the number of times of comparison failure exceeds a certain numerical value, the multi-channel metal shielding wiring layer of the chip is considered to be attacked and an alarm signal is generated. The circuit and the method for detecting the integrity of the multi-channel metal shielding wiring layer can accurately detect whether the multi-channel metal shielding wiring layer is attacked or not, and avoid misjudgment caused by signal interference in wiring.
Description
Technical Field
The invention relates to the field of safety chip design, in particular to a circuit and a method for detecting the integrity of a multi-channel metal shielding wiring layer.
Background
In recent years, in the field of integrated circuits, security protection of chips is more and more emphasized. One common protection means is to construct a dense metal protection network on the top metal layer of the chip, and detect the integrity state of the metal network to determine whether the chip is attacked. Therefore, how to quickly and accurately detect the integrity of the metal shielding network has important research and application values in the field of chip security.
At present, the methods for detecting the integrity of the metal shielding network are generally classified into a passive detection method and an active detection method. The passive detection mode passively detects the change of electrical parameters such as capacitance and resistance of the metal protection structure by using a signal amplification circuit, and then judges physical attack. The active detection mode adopts a mode of injecting stream passwords into a sensor network layer for protection, and open circuit of the protection layer are judged through equivalence check of signals so as to detect physical attack. The active detection mode can be realized by full digit, the process mobility is good, and the noise tolerance and the robustness are high, so the method is widely applied.
The metal shielding network covers the top metal layer of the chip, and the metal routing is longer. When the space electromagnetic field changes more violently, the signal pole in the metal wire is easy to be interfered by the space electromagnetic field and errors occur. The existing active detection technology is mostly characterized in that a single bit code value is compared, and once a signal in a wiring line is interfered, a false alarm condition occurs, so that a chip executes a security protection action by mistake.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a circuit and a method for detecting the integrity of a multi-channel metal shielding wiring layer, which can accurately detect whether the multi-channel metal shielding wiring layer is attacked or not and avoid misjudgment caused by signal interference in wiring.
In order to achieve the above object, the present invention provides a circuit for integrity detection of a multi-channel metal shielding wiring layer, which includes a random number generation circuit and a signal comparison circuit. The random number generating circuit is used for generating a random number sequence, each path of random numbers in the random number sequence are transmitted through two transmission channels, and the two transmission channels are the multi-channel metal shielding wiring layer and the lower metal wire of the chip respectively; the signal comparison circuit is connected with the two transmission channels and used for comparing random number signals input to the signal comparison circuit by the two transmission channels, if a certain path of random number generated by the random number generation circuit is identical to two signals output to the signal comparison circuit by the two transmission channels, the comparison is considered to be successful, otherwise, if the two signals are different, the comparison is considered to be failed, and when the number of times of the comparison failure exceeds a certain numerical value, the multi-channel metal shielding wiring layer of the chip is considered to be attacked and generates an alarm signal.
In a preferred embodiment, the random number generating circuit includes a feedback shift register, the feedback shift register is composed of a plurality of D flip-flops connected in series, an input terminal of the 1 st-stage D flip-flop is connected to a positive output terminal of the last-stage D flip-flop, input signals of a part of D flip-flops of the remaining D flip-flops are provided by positive output terminals of the last-stage D flip-flop, input signals of another part of D flip-flops of the remaining D flip-flops are provided by exclusive-or of the positive output terminals of the last-stage D flip-flop and the positive output terminals of the last-stage D flip-flop, the number of the another part of D flip-flops is the same as the number of channels of the multi-channel metal-shielding wiring layer, and each path of random number output by each flip-flop of the another part of D.
In a preferred embodiment, the signal comparison circuit includes a plurality of comparison modules, the number of the comparison modules is the same as the number of the channels of the multi-channel metal shielding wiring layer, each comparison module includes two input ends and an output end, a certain path of random number is output to each input end of a certain comparison module through the two transmission channels for comparison, and if the comparison result is abnormal, the comparison module outputs an alarm signal.
In a preferred embodiment, each alignment module further comprises: a group of D triggers, an exclusive-OR gate, an accumulator and a threshold judgment module. A group of D flip-flops is used for sampling random numbers output by the two transmission channels; the input end of the exclusive-OR gate is connected with the output end of the group of D triggers and is used for carrying out exclusive-OR on the sampled random numbers; the input end of the accumulator is connected with the output end of the exclusive-OR gate and is used for accumulating the exclusive-OR result; the input end of the threshold value judging module is connected with the output end of the accumulator and is used for judging whether the accumulation result exceeds the threshold value or not, and if the accumulation result exceeds the threshold value, an alarm signal is output.
In a preferred embodiment, the signal comparison circuit further includes an and gate, the output terminals of all comparison modules are used as the input terminals of the and gate, and when a comparison module outputs an alarm signal, the and gate outputs the alarm signal.
The invention also provides a method for detecting the integrity of the multi-channel metal shielding wiring layer. The method comprises the following steps: generating a random number sequence; each path of random number in the random number sequence is transmitted through two transmission channels, wherein the two transmission channels are the multi-channel metal shielding wiring layer and the lower metal wire of the chip respectively; and comparing a group of random number signals output by the same random number through the two transmission channels, if the group of signals are the same, the comparison is successful, otherwise, if the group of signals are different, the comparison is failed, and if the number of times of the comparison failure exceeds a threshold value, the multi-channel metal shielding wiring layer of the chip is attacked and an alarm signal is generated.
In a preferred embodiment, the method further comprises: before generating a random number sequence, providing a random number generation circuit, wherein the random number generation circuit comprises a feedback shift register, the feedback shift register is formed by connecting a plurality of D triggers in series, the input end of the 1 st-stage D trigger is connected with the positive output end of the last-stage D trigger, the input signals of a part of D triggers of the rest D triggers are provided by the positive output end of the last-stage D trigger, the input signals of the other part of D triggers of the rest D triggers are provided by the exclusive OR of the positive output end of the last-stage D trigger and the positive output end of the last-stage D trigger, the number of the other part triggers is the same as that of the channels of the multi-channel metal shielding wiring layer, and each path of random numbers output by each trigger of the other part triggers form the random number sequence.
In a preferred embodiment, the method further comprises: after providing the random number generation circuit and before generating the random number sequence, all D flip-flops in the random number generation circuit are set, so that all flip-flop outputs are 1.
In a preferred embodiment, comparing the random number signals output by the same random number through the two transmission channels includes: providing a plurality of comparison modules, wherein the number of the comparison modules is the same as that of channels of the multi-channel metal shielding wiring layer, each comparison module comprises a group of D triggers, an exclusive-OR gate, an accumulator and a threshold judgment module, the input ends of the group of D triggers are connected with the output ends of the two transmission channels, the two input ends of the exclusive-OR gate are connected with the two output ends of the group of D triggers, the input end of the accumulator is connected with the output end of the exclusive-OR gate, and the input end of the threshold judgment module is connected with the output end of the accumulator; the D trigger of each comparison module samples a group of output signals of two corresponding transmission channels in a comparison period consisting of a plurality of clock periods, if the sampled group of output signals are the same, the XOR gate outputs 0, the comparison is successful, otherwise, the XOR gate outputs 1, the comparison fails, the accumulator accumulates the comparison result, the threshold judgment module judges whether the accumulation result exceeds the threshold, and if the accumulation result exceeds the threshold, the comparison module outputs an alarm signal.
In a preferred embodiment, the D flip-flops of the random number generating circuit are all triggered by a clock falling edge, the D flip-flops of the comparison module are all triggered by a clock rising edge, and the clock half-period time is greater than the holding time t of the random number generating circuitholdTime delay t of routingdealyEstablishing time t with the signal comparison circuitsetupThe sum of the three.
Compared with the prior art, the circuit and the method for detecting the integrity of the multi-channel metal shielding wiring layer are used for designing a multi-channel active detection circuit for a metal shielding protection network formed by a plurality of wirings, the circuit structure injects a random number sequence into the starting point of the metal network through a random number generating circuit, and the consistency of the random number sequence is monitored at the end point of the metal network through a signal comparison circuit. By setting the redundancy safety threshold, when the comparison failure times in a certain period exceed the redundancy safety threshold, the alarm behavior is triggered, so that the accuracy of the alarm signal is ensured.
Drawings
FIG. 1 is a schematic diagram of a subject circuit for integrity testing of a multi-channel metal shield wiring level in accordance with an embodiment of the present invention;
FIG. 2 is a schematic diagram of a random number generating circuit according to an embodiment of the invention;
FIG. 3 is a diagram of an alignment module according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a detection cycle of the comparison module according to an embodiment of the invention.
Detailed Description
The following detailed description of the present invention is provided in conjunction with the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.
The invention designs a multi-channel active detection circuit aiming at a metal shielding protection network formed by a plurality of wires, wherein the circuit structure injects random code streams into the starting point of the metal network and monitors and compares the consistency of the code streams at the end point. By setting the redundancy safety threshold, when the comparison failure times in a certain period exceed the redundancy safety threshold, the alarm behavior is triggered, so that the accuracy of the alarm signal is ensured.
FIG. 1 is a schematic diagram of a subject circuit for integrity testing of a multi-channel metal shield wiring level in accordance with an embodiment of the present invention. The main circuit structure comprises a random number generation circuit and a signal comparison circuit.
The random number generating circuit is used for generating a plurality of paths of pseudo random numbers, and each path of pseudo random numbers is different. Each path of pseudo-random number is transmitted to the signal comparison circuit in two modes, one mode is used for transmitting the signal to the comparison circuit through top metal wiring to be detected, and the other mode is used for directly transmitting the signal to the comparison circuit through lower metal wiring. The signal comparison circuit comprises a plurality of comparison modules, and each comparison module respectively compares and analyzes the pseudo random numbers transmitted by the two modes.
The following description will be given by taking a 32-channel metal shielding wiring layer to be detected as an example.
FIG. 2 is a diagram of a random number generating circuit according to an embodiment of the invention. Alternatively, the random number generation circuit is constituted by a Linear Feedback Shift Register (LFSR). The LFSR consists of 64D flip-flops in series, each stage of D flip-flops being triggered by the falling edge of the clock signal Clk. The input of the 1 st D flip-flop D1 is connected with the positive output Q64 of the last D flip-flop D64, and the input of the 2 nd to the 64 th D flip-flops is provided by two ways: mode 1, provided by the positive output terminal of the previous stage D flip-flop; mode 2 is provided by xoring the positive output terminal of the previous stage D flip-flop with the positive output terminal Q64 of the 64 th stage D flip-flop. Mode 1 and mode 2 can be freely combined, but it is guaranteed that the total number of D flip-flops with mode 2 as an input is 32. In the specific embodiment shown in fig. 2, the 2 nd stage D flip-flop uses mode 2 as an input, and the signal obtained by xoring the positive output Q1 of the 1 st stage D flip-flop with the positive output Q64 of the 64 th stage D flip-flop is used as an input signal. The 3 rd stage D flip-flop adopts mode 1 as an input, and a signal of a positive output end Q2 of the 2 nd stage D flip-flop is used as an input signal. The 4 th and 63 th stages take mode 2 as input. And generating a 1-path random sequence at the positive output end of each stage of D flip-flops taking the mode 2 as the input, wherein 32 paths of pseudo-random sequences without obvious correlation properties are generated in total because the total number of the D flip-flops taking the mode 2 as the input is 32, and the 32 paths of pseudo-random sequences are represented by Channel1, Channel2 to Channel32 respectively. And each path of random sequence is transmitted to the corresponding comparison module through the top layer metal wire and the lower layer metal wire to be detected respectively. In practical applications, the LFSR random number generator can adjust the total number of D flip-flops and the number of D flip-flops input by the method 2 according to actual requirements. Only the output of the D flip-flop with the mode 2 input can be used for signal comparison, so the number of metal shielding wiring channels should be the same as the number of D flip-flops with the mode 2 input. The period of the pseudo random number generated by the LFSR random number generator is positively correlated with the total number of D triggers, so that in order to realize better randomness, the total number of D triggers is required to be ensured to be more than or equal to the number of D triggers input by the mode 2.
Correspondingly, the comparison circuit is composed of 32 comparison modules with the same structure and a 32-input AND gate. Each comparison module is provided with two input ends and an output end. And each of the 32 paths of pseudo-random sequences generated by the random number generation circuit is transmitted to two input ends of the corresponding comparison module through the top metal wire and the lower metal wire to be detected respectively. The output ends of all the comparison modules are connected to the input ends of the 32-input AND gates. The output end of the AND gate is the comparison result. In the embodiment shown in FIG. 2, the comparison channel1 is illustrated. The 1 st alignment path is composed of a pseudorandom sequence Channel1, a top metal line 1, a lower metal line 1 and an alignment module 1. The positive output end Q2 of the second stage D flip-flop generates a pseudo-random sequence Channel1, which is connected to two input ends COM1_0 and COM1_1 of the comparison module 1 through a top metal wire 1 and a lower metal wire 1, respectively, and the output end ALARM1 of the comparison module 1 is connected to one input end of the 32-input AND gate. The other alignment path structures are similar to the 1 st alignment path.
The 32 alignment modules have the same structure. The structure of the comparison module 1 shown in fig. 3 is taken as an example to be described. The comparison module 1 comprises two D flip-flops which are triggered by the rising edge of a clock CLK, positive output ends D _ COM1_0 and D _ COM1_1 of the two D flip-flops are respectively connected to two input ends of a two-input XOR gate, an output end XOUT of the XOR gate is connected to an input end of an accumulator, the output of the accumulator is connected to a threshold judgment module, and an output ALARM1 of the threshold judgment module is the comparison result output of the comparison module. On the rising edge of the clock CLK, the two D flip-flops sample the pseudo-random numbers input from the top metal line 1 and the bottom metal line 1, respectively, and output to the XOR gate. If the top level metal line 1 is not modified completely, the pseudo random number passed over it is the same as the pseudo random number in the lower level metal line 1, and the xor gate keeps outputting 0 at all times. If the top metal line 1 is modified, the pseudo-random number passed over it will not be the same as the pseudo-random number in the lower metal line 1, and the xor gate will output 1. The number of the output 1 is counted by adopting an accumulator, and when the output of the accumulator reaches a threshold value, the threshold value judging module outputs an ALARM1 high-level ALARM signal.
Based on the circuit structure, the invention also provides an integrity detection method of the chip multi-channel metal shielding wiring layer. Two ends of the metal network to be detected in the chip are respectively connected to one output of the random number generating circuit and one input of the comparison module in the signal comparison circuit. The same output of the random number generating circuit is transmitted to the other input end of the same comparison circuit through the lower metal branch. In one embodiment, the specific detection method is as follows:
in the initial working stage, all D triggers in the LFSR random number generator are set, so that the output of all D triggers in the LFSR random number generator is 1, and dead cycle caused by zero input and output of an exclusive-OR gate feedback circuit is avoided. The LFSR then generates a sequence of random numbers.
The random number sequence is transmitted to an input end of the comparison circuit through the lower metal branch, and the random number sequence is transmitted through the metal network to be detectedThere will be a delay and some time before the rising edge of the clock will arrive at the input of the comparison circuit. To ensure the validity of the detection signal, the clock half-period time needs to be longer than the holding time t of the random number generation circuitholdTime delay t of routingdealyEstablishing time t with signal comparison circuitsetupThe sum of the three, i.e. T/2>thold+tdealy+tsetup. As shown in fig. 4, taking Channel1 as an example, the process is described by comparison. And each detection channel is used for carrying out signal comparison independently. And the comparison module samples two input end signals at the rising edge of each clock period, each 8 clock periods are one comparison period, and 8bit data are obtained by sampling. Three comparison periods are continuously carried out to form a detection period, and 3 x 8bit data are obtained by sampling in one detection period. And in each comparison period, respectively and sequentially comparing the consistency of the pseudo random signals passing through the lower layer metal wire and the top layer metal wire to be detected for each 8bit, wherein if the top layer metal wire is intact and not modified, the pseudo random numbers passing through the top layer metal wire are the same as those in the lower layer metal wire, and if the top layer metal wire is modified, the pseudo random numbers are different. If the signals are the same, the comparison is successful, the exclusive-OR gate outputs 0, otherwise, the comparison is failed, and 1 is output. Accumulating the comparison result by adopting an accumulator, and if the accumulated value exceeds 2, considering that the comparison period is attacked; if the accumulated value is equal to 1 or 2, the external interference is considered; if the accumulated value is equal to 0, it is considered normal. And (4) continuously comparing for 3 times, if all the comparison periods are considered to be attacked, judging that the comparison period is attacked, outputting a high-level alarm signal by the comparison circuit, and otherwise, outputting a low-level normal signal.
In the embodiment shown in fig. 4, in the 1 st alignment period, the 1bit alignment failure occurs, and is considered to be interfered, and in the last 3 alignment periods, the alignment failure of more than 3 bits occurs, and is considered to be attacked. The detection period 1 formed by the comparison periods 1, 2 and 3 does not generate an alarm signal because the comparison period 1 is normal. And in the detection period 2 formed by the comparison periods 2, 3 and 4, an alarm signal is generated because the attack is considered to be received.
The system and the method for detecting the integrity of the multi-channel metal shielding wiring layer are suitable for accurately and quickly detecting the integrity of a large-scale metal shielding network of a chip and outputting a digital detection result, so that the chip can conveniently perform corresponding protection measures against attacks. And the full-digital realization and the good process mobility are realized. In addition, the system also has a fault-tolerant mechanism, and can avoid false alarms caused by some external interference.
The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (8)
1. A circuit for integrity testing a multi-channel metal shielded wiring layer, the circuit comprising:
the random number generating circuit is used for generating a random number sequence, each path of random numbers in the random number sequence are transmitted through two transmission channels, and the two transmission channels are the multi-channel metal shielding wiring layer and the lower metal wire of the chip respectively; and
a signal comparison circuit connected with the two transmission channels for comparing the random number signals input to the signal comparison circuit by the two transmission channels, if two signals output to the signal comparison circuit by a certain path of random number generated by the random number generation circuit via the two transmission channels are the same, the comparison is successful, otherwise, if the two signals are different, the comparison is failed, and if the number of comparison failures exceeds a certain value, the multi-channel metal shielding wiring layer of the chip is attacked and generates an alarm signal,
wherein, the signal comparison circuit includes a plurality of modules of comparing, the module of comparing includes:
a group of D triggers used for sampling random numbers output by the two transmission channels;
the input end of the exclusive-OR gate is connected with the output ends of the D flip-flops and is used for carrying out exclusive-OR on the sampled random numbers;
the input end of the accumulator is connected with the output end of the exclusive-OR gate and is used for accumulating the exclusive-OR result; and
a threshold judging module, the input end of which is connected with the output end of the accumulator and is used for judging whether the accumulation result exceeds the threshold value or not, if so, an alarm signal is output,
the comparison method of the comparison module comprises the following steps: the D trigger samples a group of output signals of two corresponding transmission channels in a comparison period consisting of a plurality of clock periods, if the sampled group of output signals are the same, the exclusive-OR gate outputs 0, the comparison is successful, otherwise, the exclusive-OR gate outputs 1, the comparison fails, the accumulator accumulates the comparison result, the threshold judgment module judges whether the accumulation result exceeds a threshold, and if the accumulation result exceeds the threshold, the comparison module outputs an alarm signal.
2. The circuit for integrity checking of a multi-channel metal shielding wiring layer according to claim 1, wherein the random number generating circuit includes a feedback shift register, the feedback shift register is formed by serially connecting a plurality of D flip-flops, an input of a 1 st-stage D flip-flop is connected to a positive output terminal of a last-stage D flip-flop, input signals of a part of the remaining D flip-flops are provided by positive output terminals of a previous-stage D flip-flop, input signals of another part of the remaining D flip-flops are provided by exclusive-or between the positive output terminals of the previous-stage D flip-flop and the positive output terminal of the last-stage D flip-flop, the number of the another part of D flip-flops is the same as the number of channels of the multi-channel metal shielding wiring layer, and each path of random number output by each D flip-flop of the another part of D flip-flops forms the random number sequence.
3. The circuit for detecting the integrity of a multi-channel metal shielding wiring layer according to claim 2, wherein the number of the comparing modules is the same as the number of the channels of the multi-channel metal shielding wiring layer, each comparing module includes two input terminals and an output terminal, a random number is output to each input terminal of a comparing module via the two transmission channels for comparison, and if the comparison result is abnormal, the comparing module outputs an alarm signal.
4. The circuit for integrity detection of a multi-channel metal shielding wiring layer as claimed in claim 1, wherein said signal comparison circuit further comprises an and gate, wherein the output terminals of all comparison modules are used as the input of said and gate, and when one comparison module outputs an alarm signal, said and gate outputs an alarm signal.
5. The circuit for integrity-testing a multi-channel metal-shield wiring level of claim 1 wherein said method for testing said circuit for integrity-testing a multi-channel metal-shield wiring level comprises:
generating a random number sequence;
each path of random number in the random number sequence is transmitted through two transmission channels, wherein the two transmission channels are the multi-channel metal shielding wiring layer and a lower metal wire of the chip respectively; and
comparing a group of random number signals output by the same random number through the two transmission channels, if the group of signals are the same, the comparison is successful, otherwise, if the group of signals are different, the comparison is failed, and if the number of times of the comparison failure exceeds a threshold value, the multi-channel metal shielding wiring layer of the chip is attacked and generates an alarm signal,
wherein, the comparing the random number signals output by the same random number through the two transmission channels comprises:
providing a plurality of comparison modules, wherein the number of the comparison modules is the same as that of channels of the multi-channel metal shielding wiring layer, each comparison module comprises a group of D triggers, an exclusive-OR gate, an accumulator and a threshold judgment module, the input ends of the group of D triggers are connected with the output ends of the two transmission channels, the two input ends of the exclusive-OR gate are connected with the two output ends of the group of D triggers, the input end of the accumulator is connected with the output end of the exclusive-OR gate, and the input end of the threshold judgment module is connected with the output end of the accumulator; and
the D trigger of each comparison module samples a group of output signals of two corresponding transmission channels in a comparison period consisting of a plurality of clock periods, if the sampled group of output signals are the same, the XOR gate outputs 0, the comparison is successful, otherwise, the XOR gate outputs 1, the comparison fails, the accumulator accumulates the comparison result, the threshold judgment module judges whether the accumulation result exceeds the threshold, and if the accumulation result exceeds the threshold, the comparison module outputs an alarm signal.
6. The circuit for integrity testing a multi-channel metal shielded wiring level of claim 5 wherein said testing method further comprises:
before generating a random number sequence, providing a random number generation circuit, wherein the random number generation circuit comprises a feedback shift register, the feedback shift register is formed by connecting a plurality of D triggers in series, the input end of the 1 st-stage D trigger is connected with the positive output end of the last-stage D trigger, the input signals of a part of D triggers of the rest D triggers are provided by the positive output end of the last-stage D trigger, the input signals of the other part of D triggers of the rest D triggers are provided by the exclusive OR of the positive output end of the last-stage D trigger and the positive output end of the last-stage D trigger, the number of the other part of D triggers is the same as that of the channels of the multi-channel metal shielding wiring layer, and each path of random numbers output by each D trigger of the other part of D triggers form the random number sequence.
7. The circuit for integrity testing a multi-channel metal shielded wiring level of claim 6 wherein said testing method further comprises:
after providing the random number generation circuit and before generating the random number sequence, setting all D flip-flops in the random number generation circuit so that all D flip-flop outputs are 1.
8. The circuit for integrity testing of a multi-channel metal shielding wiring layer as claimed in claim 6, wherein the D flip-flops of said random number generating circuit are each triggered by a falling clock edge, the D flip-flops of said match module are each triggered by a rising clock edge, and the half-cycle time of the clock is longer than the holding time t of the random number generating circuitholdTime delay t of routingdealyEstablishing time t with the signal comparison circuitsetupThe sum of the three.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201810756556.1A CN109100635B (en) | 2018-07-11 | 2018-07-11 | Circuit and method for detecting integrity of multi-channel metal shielding wiring layer |
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| CN201810756556.1A CN109100635B (en) | 2018-07-11 | 2018-07-11 | Circuit and method for detecting integrity of multi-channel metal shielding wiring layer |
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| CN109100635A CN109100635A (en) | 2018-12-28 |
| CN109100635B true CN109100635B (en) | 2021-06-29 |
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| CN109782154A (en) * | 2019-02-27 | 2019-05-21 | 大唐微电子技术有限公司 | A kind of tamper detection protection circuit, implementation method and tamper chip |
| CN112699420A (en) * | 2020-12-31 | 2021-04-23 | 广州万协通信息技术有限公司 | Active shielding protection device and method for security chip |
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