CN210403694U - Chip anti-attack protection structure - Google Patents
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- CN210403694U CN210403694U CN201921302600.8U CN201921302600U CN210403694U CN 210403694 U CN210403694 U CN 210403694U CN 201921302600 U CN201921302600 U CN 201921302600U CN 210403694 U CN210403694 U CN 210403694U
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Abstract
The embodiment of the utility model provides a chip prevent attack protection architecture is related to, include: the first shielding protection layer is paved on a top metal wiring layer and comprises a plurality of first logic processing modules and a plurality of groups of first metal wire groups, and the second shielding protection layer is paved on a designated metal wiring layer below the top metal wiring layer and comprises a plurality of second logic processing modules and a plurality of groups of second input metal wire groups; the data input end of the 1 st group of second input metal wire group is accessed with a low 2-bit code word of the initial value of the pseudo random sequence; the n +1 th group of second input metal wire groups is connected with the n th group of first output metal wire groups for pseudo-random code transmission; two ends of the nth group of first input metal wire groups are respectively connected with the data output end of the nth second logic processing module and the data input end of the nth first logic processing module for pseudo-random code transmission; and outputting the anti-attack check code word through the first output metal wire group of the Nth first logic processing module.
Description
Technical Field
The utility model relates to a chip design technical field especially relates to an attack prevention protection architecture of chip.
Background
The invasive attack of the chip, also called physical attack, refers to snooping and malicious destructive behavior of an attacker on information developed inside the chip by physical means (e.g., by means of a special instrument, device), including stripping, probe, Focused Ion Beam (FIB), and the like.
In particular, the probe tip may be brought into physical contact with a generally FIB-derived test site or a laser-cut test site. Probes may be placed on the bus of the memory module for obtaining, for example, memory contents or other information. When the chip is in operation, signals passing through the bus can be collected by a logic analyzer or oscilloscope through the probe, and the captured signals or data are analyzed, so that information passing through the bus is recovered. The chip is attacked from the bottom layer by invasive attack, and the storage information and the secret key of the chip can be obtained by a certain means, so that the safety of the chip is greatly influenced.
Aiming at the invasive attack, the design requirement of the chip is also improved, for example, an active protective layer is distributed on the top layer of the chip, the storage and management of the key are perfected, and the invasive attack difficulty can be increased to a certain extent through the defense means.
One of the solutions to physical attacks at this stage is top-level metal detection. When the chip is physically attacked, the top metal is damaged, and the detection device can detect that the top metal is damaged and send an alarm signal. However, the existing chip top layer coverage integrity protection method can only judge whether the metal wire is broken, the attack prevention is single, and the attack prevention capability is weak.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a chip prevent attack protection architecture can pass through the utility model discloses prevent attack protection architecture is distinctive has the top layer metal of logic function and the wiring structure of appointed layer metal under the top layer, accurately judges the chip and whether suffer the attack.
In order to achieve the above object, the utility model provides a chip prevent attacking protection architecture, prevent attacking protection architecture includes:
the first shielding protection layer is paved on a top metal wiring layer, and the second shielding protection layer is paved on a designated metal wiring layer below the top metal wiring layer;
the first shielding protection layer comprises a plurality of first logic processing modules and a plurality of groups of first metal wire groups which are arranged in parallel at equal intervals; each group of first metal wire groups comprises a first input metal wire group and a first output metal wire group which are respectively connected with the data input end and the data output end of the first logic processing module;
the second shielding protective layer comprises a plurality of second logic processing modules and a plurality of groups of second input metal wire groups which are arranged in parallel at equal intervals; the second input metal wire group is connected to the data input end of the second logic processing module;
the number of the second logic processing modules is equal to that of the first logic processing modules, and is N, wherein N is a positive integer, and each second logic processing module is arranged corresponding to one first logic processing module; the data input end of the 1 st group of second input metal wire group is accessed with a low 2-bit code word of the initial value of the pseudo random sequence; the n +1 th group of second input metal wire groups is connected with the n group of first output metal wire groups and used for transmitting the pseudo-random sequence code from the nth first logic processing module to the n +1 th second logic processing module; the two ends of the nth group of first input metal wire groups are respectively connected with the data output end of the nth second logic processing module and the data input end of the nth first logic processing module, and the transmission of the pseudo-random sequence code from the nth second logic processing module to the nth first logic processing module is used; outputting an anti-attack check code word through the first output metal wire group of the Nth first logic processing module; the N is a natural number, and N is [1, N-1 ].
Preferably, the first input metal wire group comprises two metal wires; the first output metal wire group comprises two metal wires; the first input metal wire group and the metal wires of the first output metal wire group are respectively arranged in parallel.
Preferably, the second input metal wire group includes two metal wires, each metal wire is L-shaped, and includes a first segment and a second segment, one end of the first segment is connected to the first output metal wire group, the first segment is perpendicular to the first output metal wire group, and the second segment is parallel to the first output metal wire group.
Preferably, the plurality of first logic processing modules and the plurality of second logic processing modules respectively have a selection control signal input terminal for receiving a selection logic control signal.
Further preferably, the data input terminal comprises a first input terminal and a second input terminal, and the data output terminal comprises a first output terminal and a second output terminal;
when the selection logic control signal is 1, the output data of the first output end is the input data of the first input end, and the output data of the second output end is the input data of the second input end;
when the selection logic control signal is 0, the output data of the first output terminal is the input data of the second input terminal, and the output data of the second output terminal is the input data of the first input terminal.
Further preferably, the data input terminal comprises a first input terminal and a second input terminal, and the data output terminal comprises a first output terminal and a second output terminal;
when the selection logic control signal is 0, the output data of the first output end is the input data of the first input end, and the output data of the second output end is the input data of the second input end;
when the selection logic control signal is 1, the output data of the first output end is the input data of the second input end, and the output data of the second output end is the input data of the first input end.
Further preferably, the inversion frequency of the selection logic control signal is configured based on a system clock of the chip.
Further preferably, according to the inversion frequency of the selection logic control signal and the set value of N, a correct logic relationship between the attack-prevention check code word and a low-order 2-bit code word of the initial value of the pseudorandom sequence is determined, the actually output attack-prevention check code word is checked according to the correct logic relationship, and whether the chip is attacked or not is determined.
Preferably, N ═ 31; the first metal wire group comprises 124 metal wires; the second metal wire group comprises 64 metal wires.
Preferably, the designated metal wiring layer is a metal layer of two layers below the top metal layer.
The embodiment of the utility model provides a chip prevent attacking protection architecture can pass through the utility model discloses prevent attacking the wiring structure of assigned layer metal under the distinctive top layer metal that has logic function of protection architecture and the top layer, accurately judge the chip and whether suffer the attack.
Drawings
Fig. 1 is a schematic view of an anti-attack protection structure provided by an embodiment of the present invention;
fig. 2 is a schematic diagram of logic executed by the logic processing module according to an embodiment of the present invention.
Detailed Description
The technical solution of the present invention is further described in detail by the accompanying drawings and examples.
The embodiment of the utility model provides a chip prevent attacking protection architecture is particularly useful for the protection of preventing attacking of safe chip.
The utility model discloses the anti-attack protection architecture of chip is shown in fig. 1, and the following combines fig. 1 as an example, explains the anti-attack protection architecture of chip of the utility model.
The utility model discloses an attack prevention protection architecture includes:
a first shielding protection layer 1 which is paved on a top metal wiring layer and a second shielding protection layer 2 which is paved on a designated metal wiring layer below the top metal wiring layer;
preferably, the metal wiring layer is a metal layer of two layers below the top metal layer. For example, the top metal layer is the 8 th metal layer, the first shielding protection layer 1 is located on the 8 th metal layer, and the second shielding protection layer 2 is located on the 6 th metal protection layer, which need to be communicated with each other through the through holes between the metal layers.
The first shielding protection layer 1 comprises a plurality of first logic processing modules 11 and a plurality of groups of first metal wire groups which are arranged in parallel at equal intervals; each group of the first metal wire groups includes a first input metal wire group 12_1 and a first output metal wire group 12_2, which are respectively connected to the data input end and the data output end of the first logic processing module 11;
the second shielding protection layer 2 comprises a plurality of second logic processing modules 21 and a plurality of groups of second input metal wire groups 22 which are arranged in parallel at equal intervals; the second input metal wire group 22 is connected to the data input end of the second logic processing module 21;
the number of the second logic processing modules 21 is equal to the number of the first logic processing modules 11, and is N, where N is a positive integer; each second logic processing module 21 is arranged corresponding to one first logic processing module 11; the data input end of the 1 st group of second input metal wire group 22 is accessed with the low 2-bit code word of the initial value of the pseudo random sequence; the (n + 1) th group of second input metal wire groups 22 is connected to the (n) th group of first output metal wire groups 12_2 for transmitting the pseudo random sequence code from the (n) th first logic processing module to the (n + 1) th second logic processing module; both ends of the nth group of first input metal wire group 12_1 are respectively connected to the data output end of the nth second logic processing module 21 and the data input end of the nth first logic processing module 11, so as to transmit the pseudo random sequence code between the nth second logic processing module 21 and the nth first logic processing module 11; moreover, the anti-attack check code word is output through the first output metal wire group 12_2 of the nth first logic processing module 11; n is a natural number, and N ═ 1, N-1.
Specifically, the first input metal wire group 12_1 includes two metal wires; the first output metal wire group 12_2 includes two metal wires; the metal lines of the first input metal line group 12_1 and the first output metal line group 12_2 are respectively disposed in parallel.
The second input metal wire group 22 includes two metal wires, each metal wire is L-shaped and includes a first section and a second section, one end of the first section is connected to the first output metal wire group 12_2, and they are connected through a through hole of the metal layer; the first segment is disposed perpendicular to the first output metal line group 12_2, and the second segment is disposed parallel to the first output metal line group 12_ 2.
In the present embodiment, it is preferable to set N to 31; the first metal wire group comprises 124 metal wires; the second metal wire group comprises 64 metal wires.
The plurality of first logic processing modules 11 and the plurality of second logic processing modules 21 each have a selection control signal input Sel for receiving a selection logic control signal.
Specifically, the data input end of each first logic processing module 11 and the data input end of each second logic processing module 21 include a first input end and a second input end, and the data output end thereof includes a first output end and a second output end;
the logic executed by the first logic processing module 11 and the second logic processing module 21 is a multiplexer, and the specific logic may be that, as shown IN fig. 2, when the selection logic control signal Sel is 1, the output data OUT1 at the first output end is the input data IN1 at the first input end, and the output data OUT2 at the second output end is the input data IN2 at the second input end; when the select logic control signal is 0, the output data OUT1 of the first output terminal is the input data IN2 of the second input terminal, and the output data OUT2 of the second output terminal is the input data IN1 of the first input terminal.
Of course, it can also be set according to the configuration that when the selection logic control signal is 0, the output data of the first output terminal is the input data of the first input terminal, and the output data of the second output terminal is the input data of the second input terminal; when the selection logic control signal is 1, the output data of the first output terminal is the input data of the second input terminal, and the output data of the second output terminal is the input data of the first input terminal.
The utility model discloses select logic control signal's upset frequency can dispose based on the system clock of chip. Therefore, according to the inversion frequency of the selection logic control signal and the set value of N, the correct logic relation between the anti-attack check code word and the low 2-bit code word of the initial value of the pseudorandom sequence can be determined, and whether the chip is attacked or not can be determined.
Of course, the initial value of the pseudo-random sequence can be inverted according to the inversion frequency, and the logic control signal is constantly selected, so that the correct logic relationship between the anti-attack check code word and the low 2-bit code word of the initial value of the pseudo-random sequence can be determined according to the inversion frequency of the initial value of the random sequence and the set value of N, and whether the chip is attacked or not can be determined.
In a preferred embodiment, the flipping frequency can be configured as one of four cases: 31.25ms,125ms,500ms,1 s.
For the case of flipping the initial value of the pseudorandom sequence, for example, according to logic determination, in each flipping frequency cycle, the correct logical relationship between the attack-prevention check code word and the low-2-bit code word of the initial value of the pseudorandom sequence is that the attack-prevention check code word is the same as the low-2-bit code word of the initial value of the pseudorandom sequence, then several flipping frequency cycles may be monitored, if in one or more cycles, the finally output attack-prevention check code word is different from the low-2-bit code word of the initial value of the pseudorandom sequence (the low-2-bit code word of the initial value of the pseudorandom sequence varies with the frequency cycle), then the chip may be considered to be attacked, and if the finally output attack-prevention check code word does not vary with the low-2-bit code word of the initial value of the pseudorandom sequence in different frequency cycles, then the chip is considered to be attacked.
For the case of selecting the logic control signal by flipping, for example, according to logic determination, several flipping frequency cycles may be monitored, in a first flipping frequency cycle, the correct logical relationship between the attack-prevention check code word and the low 2-bit code word of the initial value of the pseudorandom sequence is that the attack-prevention check code word is the same as the low 2-bit code word of the initial value of the pseudorandom sequence, and in a second flipping frequency cycle, the correct logical relationship between the attack-prevention check code word and the low 2-bit code word of the initial value of the pseudorandom sequence is that the attack-prevention check code word is opposite to the low 2-bit code word of the initial value of the pseudorandom sequence, so that the chip does not receive an attack, otherwise, the chip may be considered to be attacked. And if the finally output anti-attack check code word does not change along with the frequency period, the chip is considered to be under the break attack.
The embodiment of the utility model provides a pair of chip prevent attack protection architecture can pass through the utility model discloses the wiring structure of appointed layer metal under the distinctive top layer metal that has logic function of prevent attack protection architecture and the top layer accurately judges whether the chip suffers the attack.
The above-mentioned embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above description is only the embodiments of the present invention, and is not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (9)
1. An attack protection architecture for a chip, the attack protection architecture comprising:
the first shielding protection layer is paved on a top metal wiring layer, and the second shielding protection layer is paved on a designated metal wiring layer below the top metal wiring layer;
the first shielding protection layer comprises a plurality of first logic processing modules and a plurality of groups of first metal wire groups which are arranged in parallel at equal intervals; each group of first metal wire groups comprises a first input metal wire group and a first output metal wire group which are respectively connected with the data input end and the data output end of the first logic processing module;
the second shielding protective layer comprises a plurality of second logic processing modules and a plurality of groups of second input metal wire groups which are arranged in parallel at equal intervals; the second input metal wire group is connected to the data input end of the second logic processing module;
the number of the second logic processing modules is equal to that of the first logic processing modules, and is N, wherein N is a positive integer, and each second logic processing module is arranged corresponding to one first logic processing module; the data input end of the 1 st group of second input metal wire group is accessed with a low 2-bit code word of the initial value of the pseudo random sequence; the n +1 th group of second input metal wire groups is connected with the n group of first output metal wire groups and used for transmitting the pseudo-random sequence code from the nth first logic processing module to the n +1 th second logic processing module; the two ends of the nth group of first input metal wire groups are respectively connected with the data output end of the nth second logic processing module and the data input end of the nth first logic processing module, and the transmission of the pseudo-random sequence code from the nth second logic processing module to the nth first logic processing module is used; outputting an anti-attack check code word through the first output metal wire group of the Nth first logic processing module; the N is a natural number, and N is [1, N-1 ].
2. The structure of claim 1, wherein the first set of input wires comprises two wires; the first output metal wire group comprises two metal wires; the first input metal wire group and the metal wires of the first output metal wire group are respectively arranged in parallel.
3. The structure of claim 1, wherein the second set of input metal lines comprises two metal lines, each metal line is L-shaped and includes a first segment and a second segment, one end of the first segment is connected to the first set of output metal lines, the first segment is disposed perpendicular to the first set of output metal lines, and the second segment is disposed parallel to the first set of output metal lines.
4. The structure of claim 1, wherein the first and second plurality of logic processing modules each have a select control signal input for receiving a select logic control signal.
5. The structure of claim 4, wherein the data input comprises a first input and a second input, and the data output comprises a first output and a second output;
when the selection logic control signal is 1, the output data of the first output end is the input data of the first input end, and the output data of the second output end is the input data of the second input end;
when the selection logic control signal is 0, the output data of the first output terminal is the input data of the second input terminal, and the output data of the second output terminal is the input data of the first input terminal.
6. The structure of claim 4, wherein the data input comprises a first input and a second input, and the data output comprises a first output and a second output;
when the selection logic control signal is 0, the output data of the first output end is the input data of the first input end, and the output data of the second output end is the input data of the second input end;
when the selection logic control signal is 1, the output data of the first output end is the input data of the second input end, and the output data of the second output end is the input data of the first input end.
7. The anti-attack protection architecture according to claim 4, wherein the flip frequency of the selection logic control signal is configured based on a system clock of the chip.
8. The structure of claim 1, wherein N-31; the first metal wire group comprises 124 metal wires; the second input metal wire group comprises 64 metal wires.
9. The structure of claim 1, wherein the designated metal routing layer is a metal layer of two layers below a top metal layer.
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| CN201921302600.8U CN210403694U (en) | 2019-08-12 | 2019-08-12 | Chip anti-attack protection structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110391187A (en) * | 2019-08-12 | 2019-10-29 | 兆讯恒达微电子技术(北京)有限公司 | A kind of attack protection protection structure of chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110391187A (en) * | 2019-08-12 | 2019-10-29 | 兆讯恒达微电子技术(北京)有限公司 | A kind of attack protection protection structure of chip |
| CN110391187B (en) * | 2019-08-12 | 2024-03-08 | 兆讯恒达科技股份有限公司 | Anti-attack protection structure of chip |
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Address after: 100080, Beijing, Suzhou Street, Haidian District No. 20, building 2, on the north side of the four floor Patentee after: Zhaoxun Hengda Technology Co., Ltd Address before: 100080, Beijing, Suzhou Street, Haidian District No. 20, building 2, on the north side of the four floor Patentee before: MEGAHUNT MICROELECTRONIC TECH. (BEIJING) Co.,Ltd. |
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