CN109087913B - Electrostatic discharge protection structure and forming method thereof - Google Patents

Electrostatic discharge protection structure and forming method thereof Download PDF

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CN109087913B
CN109087913B CN201710450005.8A CN201710450005A CN109087913B CN 109087913 B CN109087913 B CN 109087913B CN 201710450005 A CN201710450005 A CN 201710450005A CN 109087913 B CN109087913 B CN 109087913B
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doped
substrate
electrostatic discharge
forming
doped epitaxial
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CN109087913A (en
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赵猛
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

An electrostatic discharge protection structure and a forming method thereof are provided, wherein the forming method comprises the following steps: forming a base, wherein the base comprises a substrate, a grid structure positioned on the substrate, and a first doped region and a second doped region which are respectively positioned in the substrate at two sides of the grid structure; forming at least two doped epitaxial layers arranged at intervals in the substrate of the first doped region; and forming a first plug electrically connected with the doped epitaxial layer and a second plug electrically connected with the second doped region. The drain electrode of the electrostatic discharge protection structure is formed by the first doping area and the at least two doping epitaxial layers, so that the gradient of the concentration of doped ions of the drain electrode of the electrostatic discharge protection structure can be effectively improved, and the trigger voltage of electrostatic discharge protection can be reduced.

Description

Electrostatic discharge protection structure and forming method thereof
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to an electrostatic discharge protection structure and a forming method thereof.
Background
In addition, as the technological capability of semiconductor processes is continuously improved, the size of semiconductor devices is continuously reduced. The more significant the damage to semiconductor integrated circuits by Electrostatic Discharge (ESD) becomes. Moreover, with the widespread use of semiconductor chips, the factors causing electrostatic damage to the semiconductor chips are increasing. Statistically, 35% of the products with integrated circuit failures are due to electrostatic discharge problems.
In order to solve the ESD problem of a semiconductor chip and reduce the occurrence of the damage phenomenon of a semiconductor device, an ESD (Electrostatic Discharge) protection structure is often adopted in the conventional chip design to reduce the chip damage. The design and application of the existing electrostatic discharge protection structure include: a Gate Grounded N-type field effect Transistor (GGNMOS) protection structure, a shallow trench isolation diode (STI diode) protection structure, a Gate controlled diode (Gated diode) protection structure, a Lateral Diffused MOS (LDMOS) protection structure, a Bipolar Junction Transistor (BJT) protection structure, and the like.
However, the trigger voltage of the conventional electrostatic discharge protection structure is often too high, so that the electrostatic discharge protection structure is difficult to exert the protection function, and the requirement of the electrostatic discharge protection function of the chip is difficult to meet.
Disclosure of Invention
The invention provides an electrostatic discharge protection structure and a forming method thereof, which aim to reduce trigger voltage and meet the requirement of electrostatic discharge protection function of a chip.
In order to solve the above problems, the present invention provides a method for forming an esd protection structure, comprising: forming a base, wherein the base comprises a substrate, a grid structure positioned on the substrate, and a first doped region and a second doped region which are respectively positioned in the substrate at two sides of the grid structure; forming at least two doped epitaxial layers in the substrate of the first doped region, wherein the at least two doped epitaxial layers are arranged at intervals; and forming a first plug electrically connected with the doped epitaxial layer and a second plug electrically connected with the second doped region.
Optionally, the material of the doped epitaxial layer is different from the material of the substrate.
Optionally, the substrate material is silicon; the doped epitaxial layer is made of doped silicon germanium or doped silicon carbon.
Optionally, the doping concentration of the doped epitaxial layer is 1E19atom/cm3To 1E21atom/cm3Within the range.
Optionally, the doped epitaxial layer is a Σ -shaped epitaxial layer.
Optionally, the step of forming the doped epitaxial layer includes: forming at least two grooves in the substrate of the first doping area; and forming the doped epitaxial layer in the groove.
Optionally, the doped epitaxial layer is formed in the groove in an epitaxial growth mode.
Optionally, in the process of forming the doped epitaxial layer by epitaxial growth, in-situ ion doping is performed.
Optionally, the forming method further includes: after the doped epitaxial layers are formed and before the first plug and the second plug are formed, performing electrostatic discharge injection, and forming an electrostatic discharge doped region in the substrate, wherein the electrostatic discharge doped region is positioned below the at least two doped epitaxial layers.
Optionally, the forming method further includes: after the at least two epitaxial layers are formed and before the electrostatic discharge injection is carried out, a patterned mask layer is formed on the substrate, and an opening with the bottom exposing the doped epitaxial layers is formed in the mask layer; and carrying out the electrostatic discharge injection on the substrate with the mask layer.
Optionally, the step of forming the at least two doped epitaxial layers includes: forming a patterned mask layer on the substrate, wherein the mask layer is provided with at least two openings, and the bottom of each opening exposes the substrate of the first doping region; forming at least two grooves in the substrate by taking the mask layer as a mask; forming the doped epitaxial layer in the groove; and carrying out the electrostatic discharge injection on the substrate with the mask layer.
Optionally, the mask layer is a hard mask layer.
Optionally, the mask layer is made of silicon oxide.
Optionally, the implanted ions injected by electrostatic discharge include: one or more of group V element ions.
Optionally, the implanted ions injected by electrostatic discharge further include: one or two of N or C.
Optionally, the number of the first plugs is at least two, and the at least two first plugs are connected with the at least two doped epitaxial layers in a one-to-one correspondence manner.
Correspondingly, the invention also provides an electrostatic discharge protection structure, which comprises: the substrate comprises a substrate, a grid structure positioned on the substrate, and a first doped region and a second doped region which are respectively positioned in the substrate at two sides of the grid structure; at least two doped epitaxial layers which are positioned in the first doped region and are arranged at intervals; a first plug electrically connected to the doped epitaxial layer; and the second plug is electrically connected with the second doping region.
Optionally, the material of the doped epitaxial layer is different from the material of the substrate.
Optionally, the doping concentration of the doped epitaxial layer is 1E19atom/cm3To 1E21atom/cm3Within the range.
Optionally, the doped epitaxial layer is a Σ -shaped epitaxial layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the first doped region and the at least two doped epitaxial layers in the first doped region are used as a drain electrode of the electrostatic discharge protection structure, and the second doped region is used as a source electrode of the electrostatic discharge protection structure; through the first doping area and the drain electrode of the electrostatic discharge protection structure is formed by the at least two doping epitaxial layers, the gradient of the doping ion concentration of the drain electrode of the electrostatic discharge protection structure can be effectively improved, the probability that the electrostatic discharge protection structure is broken down can be effectively increased, the trigger voltage of electrostatic discharge protection is favorably reduced, the protection function of the electrostatic discharge protection structure is favorably exerted, and the requirement of the electrostatic discharge protection function of the chip is favorably met.
In an alternative scheme of the invention, the materials of the at least two doped epitaxial layers are different from the material of the substrate, so that the electric field density between the source electrode and the drain electrode of the electrostatic discharge protection structure can be effectively increased, the trigger voltage of electrostatic discharge protection can be favorably reduced, and the protection function of the electrostatic discharge protection structure can be favorably exerted.
In the alternative of the invention, the substrate is made of silicon; the material of the doped epitaxial layer is doped germanium silicon or doped carbon silicon. The application range of the germanium-silicon or carbon-silicon material is wider, and the material of the doped epitaxial layer is set to be doped germanium-silicon or doped carbon-silicon, so that the process compatibility of the electrostatic discharge protection structure can be effectively improved, the yield can be improved, and the cost can be reduced.
In an alternative aspect of the invention, the doped epitaxial layer is a "Σ" shaped doped epitaxial layer. The sigma-shaped doped epitaxial layer is provided with a sharp corner which is back to the center of the doped epitaxial layer and protrudes, the electric field density of the doped epitaxial layer at the sharp corner is higher, the probability of point discharge can be effectively improved, the reduction of trigger voltage is facilitated, and the protection function of the electrostatic discharge protection structure is exerted.
In an alternative scheme of the invention, after the at least two doped epitaxial layers are formed, an electrostatic discharge doped region can be formed in the substrate below the at least two doped epitaxial layers through electrostatic discharge injection; the electrostatic discharge doped region can modulate the trigger voltage, so that the formed electrostatic discharge protection structure meets the requirements of the electrostatic discharge protection function of the chip.
In an alternative scheme of the invention, before the electrostatic discharge injection, a patterned mask layer is formed on the substrate, and an opening with the bottom exposing the doped epitaxial layer is formed in the mask layer; performing the electrostatic discharge injection on the substrate with the mask layer; therefore, the concentration distribution of the doped ions in the electrostatic discharge doped region is not uniform, and the non-uniform electrostatic discharge doped region can further reduce the trigger voltage of the electrostatic discharge protection structure, thereby being beneficial to the exertion of the electrostatic discharge protection function.
In an alternative scheme of the invention, the patterned mask layer is used as a mask to form a groove in the substrate in the process of forming the at least two doped epitaxial layers; the graphical mask layer is used for shielding part of the substrate in the electrostatic discharge injection process so as to form an electrostatic discharge doping area which is non-uniformly distributed; the formation of the doped epitaxial layer and the electrostatic discharge injection are carried out by adopting the same graphical mask layer, so that the use of the mask layer can be reduced, the process complexity can be reduced, the alignment problem can be avoided, the process difficulty can be reduced, and the yield and the performance of the formed electrostatic discharge protection structure can be improved.
Drawings
FIG. 1 is a schematic cross-sectional view of an ESD protection structure;
fig. 2 to 9 are schematic diagrams corresponding to steps in an embodiment of a method for forming an esd protection structure according to the invention.
Detailed Description
As can be seen from the background art, the esd protection structure in the prior art has a problem of too high trigger voltage. The reason for the problem of the over-high trigger voltage is analyzed by combining an electrostatic discharge protection structure:
referring to fig. 1, a schematic cross-sectional structure of an esd protection structure is shown.
The electrostatic discharge protection structure includes: a substrate 11, wherein the substrate 11 is provided with a P-type well region 12; a gate structure 13 located on the substrate 11; a source region 14 and a drain region 15 which are respectively positioned in the P-type well region 12 in the substrate 11 at two sides of the gate structure 13; and the electrostatic discharge doping region 16 is positioned in the P-type well region 12 in the substrate 11 below the drain region 15.
The ESD doped region 16 is typically formed by ESD implantation to implant B or BF into the P well 12 in the substrate 11 below the drain region 152(ii) a And the adjustment of trigger voltage (trigger voltage) of the electrostatic discharge protection structure is realized through the modulation of the process parameters such as the injection depth, the injection energy, the injection dosage and the like.
However, due to the problem of leakage current control (junction leakage control issue), the esd injection method cannot further reduce the trigger voltage of the formed esd protection structure, thereby affecting the performance of the formed esd protection structure, which is difficult to exert its protection effect and meet the requirements of the esd protection function of the chip.
To solve the above-mentioned problems, the present invention provides a method for forming an electrostatic discharge protection structure,
the drain electrode of the electrostatic discharge protection structure is formed by the first doping area and the at least two doping epitaxial layers, so that the gradient of the concentration of doped ions of the drain electrode of the electrostatic discharge protection structure can be effectively improved, and the trigger voltage of electrostatic discharge protection can be reduced.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 2 to 9, schematic diagrams corresponding to steps in an embodiment of a method for forming an esd protection structure according to the invention are shown.
Referring to fig. 2, a base (not labeled) is formed, and the base includes a substrate 110, a gate structure 120 located on the substrate 110, and a first doped region 131 and a second doped region 132 located in the substrate 110 at two sides of the gate structure 120, respectively.
The substrate provides a process operation basis for subsequent steps.
The substrate 110 can provide a process platform.
In this embodiment, the substrate 110 is made of monocrystalline silicon. In other embodiments of the present invention, the material of the substrate may also be selected from polysilicon, amorphous silicon, or other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In other embodiments of the present invention, the substrate may also be a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate, or other types of substrates. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the formed esd protection structure is a planar device, so the substrate 110 is a planar substrate. In other embodiments of the present invention, the formed esd protection structure may also be a three-dimensional device with a fin structure; when the formed esd protection structure is a three-dimensional device, the substrate may include a planar substrate and a fin protruding from the planar substrate.
The gate structure 120 is a gate structure of the formed esd protection structure, and can control the conduction and the cut-off of the channel of the formed esd protection structure. The gate structure 120 includes: a gate dielectric layer (not shown) on the substrate 110 and a gate electrode on the gate dielectric layer.
The gate dielectric layer is used for realizing the electrical isolation between the gate electrode and the channel in the substrate 110; the gate electrode is used to make a connection to an external circuit. In this embodiment, the gate structure 120 is a polysilicon gate structure; therefore, the gate dielectric layer is made of silicon oxide, and the gate electrode is made of polysilicon.
In other embodiments of the present invention, the formed esd protection structure may also have a metal gate structure formed by a gate last process, and the gate structure may also be a dummy gate structure, which is used to occupy a spatial position for a subsequently formed metal gate structure.
The forming step of the gate structure 120 includes: forming an oxide layer on the substrate 110; forming a gate material layer on the oxide layer; forming a gate mask layer on the gate material layer, wherein the gate mask layer is used for defining the size and the position of the gate structure 120; and etching the gate material layer and the oxide layer by taking the gate mask layer as a mask to expose the surface of the substrate 110, thereby forming the gate structure 120.
As shown in fig. 2, in this embodiment, the forming method further includes: after the gate structure 120 is formed, a sidewall spacer (not shown) is formed on the sidewall of the gate structure 120 to protect the gate structure 120 and to define the positions of the first doped region and the second doped region formed subsequently.
The side wall can be made of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride, and can be of a single-layer structure or a laminated structure. In this embodiment, the sidewall is of a single-layer structure, and the material of the sidewall is silicon nitride.
The first doped region 131 is used as a part of a drain region of the formed electrostatic discharge protection structure; the second doped region 132 serves as a source region of the formed esd protection structure for inputting an electrostatic current.
In this embodiment, the formed esd protection structure is an N-type esd protection structure (NSD); therefore, the first doped region 131 and the second doped region 132 are N-type doped regions, that is, the doped ions in the first doped region 131 and the second doped region 132 are N-type ions, such as P, As or Sb.
In this embodiment, the first doping region 131 and the second doping region 132 may be formed simultaneously, and the step of forming the first doping region 131 and the second doping region 132 includes: with the gate structure 120 as a mask, ion implantation is performed on the substrate 110 at two sides of the gate structure 120 to form the first doped region 131 and the second doped region 132.
Specifically, the doping ions in the first doping region 131 are P; the concentration of the doped ions is 5E19atom/cm3To 5E22atom/cm3Within the range; the second doping region 132 has P-doped ions; the concentration of the doped ions is 5E19atom/cm3To 5E22atom/cm3Within the range.
Referring to fig. 3 to 5, at least two doped epitaxial layers 140 (as shown in fig. 5) are formed in the substrate 110 of the first doped region 131, and the at least two doped epitaxial layers 140 are spaced apart from each other.
The at least two doped epitaxial layers 140 disposed at intervals are used as the drain of the formed esd protection structure together with the first doped region 131 to output an electrostatic current.
The first doping area 131 and the at least two doping epitaxial layers 140 form the drain of the electrostatic discharge protection structure, so that the gradient of the concentration of doped ions in the drain of the electrostatic discharge protection structure can be effectively improved, the probability of breakdown of the electrostatic discharge protection structure can be effectively increased, the trigger voltage of electrostatic discharge protection can be reduced, the protection function of the electrostatic discharge protection structure can be exerted, and the requirement of the electrostatic discharge protection function of a chip can be met.
In this embodiment, the material of the doped epitaxial layer 140 is different from the material of the substrate 110, which can effectively increase the electric field density between the source and the drain of the esd protection structure, thereby facilitating the reduction of the trigger voltage of the esd protection and the exertion of the protection function of the esd protection structure.
Specifically, the substrate 110 is made of silicon; the material of the doped epitaxial layer 140 may be doped silicon germanium or doped silicon carbon. The application range of the germanium-silicon or carbon-silicon material is wider, and the material of the doped epitaxial layer is set to be doped germanium-silicon or doped carbon-silicon, so that the process compatibility of the electrostatic discharge protection structure can be effectively improved, the yield can be improved, and the cost can be reduced.
The number of the doped epitaxial layers 140 is at least two, and as shown in fig. 3 to 5, in this embodiment, two doped epitaxial layers 140 are formed in the first doped region 131. In other embodiments of the present invention, the number of the doped epitaxial layer 140 in the first doped region 131 may also be 3, 4, or 5, which is greater than 2. In this way, an electric field can be formed between the adjacent doped epitaxial layers 140, so that the trigger voltage of the formed electrostatic discharge protection structure can be effectively reduced, and the purpose of suppressing the leakage current can be achieved.
And the number of the doped epitaxial layers 140 is set to be at least two, and the at least two doped epitaxial layers 140 can be connected with different potentials, so that the formed electrostatic discharge protection structure can be broken down under different voltages, that is, the function of multiple trigger voltages can be realized, and the performance of the formed electrostatic discharge protection structure can be effectively improved.
It should be noted that, in this embodiment, 2 doped epitaxial layers 140 are formed in the first doped region 131 as an example. In other embodiments of the present invention, the number of the doped epitaxial layers may also be more than 2.
The doping types of the at least two doped epitaxial layers 140 are the same as the doping type of the first doped region 131, in this embodiment, the formed electrostatic discharge protection structure is an N-type electrostatic discharge protection structure (NSD), and the first doped region 131 is an N-type doped region; the at least two doped epitaxial layers 140 are N-type doped epitaxial layers 140 and the dopant ions may be one or more of P, As or Sb. Specifically, the doping concentration of the doped epitaxial layer 140 is 1E19atom/cm3To 1E21atom/cm3Within the range.
In the present embodiment, the doped epitaxial layer 140 is a "Σ" shaped epitaxial layer. Therefore, the doped epitaxial layer 140 has a sharp corner protruding away from the center of the doped epitaxial layer 140, and at the sharp corner, the electric field density of the doped epitaxial layer 140 is high, so that the probability of point discharge can be effectively improved, the reduction of trigger voltage is facilitated, and the protection function of the electrostatic discharge protection structure can be exerted.
It should be noted that, the at least two adjacent doped epitaxial layers 140 are disposed at intervals, that is, in a plane parallel to the surface of the substrate 110, the at least two epitaxial doped layers 140 are arranged along a direction away from the gate structure 120, and a certain gap exists between the adjacent epitaxial doped layers 140.
The distance between adjacent doped epitaxial layers 140 is related to the trigger voltage of the formed electrostatic discharge protection structure: the smaller the distance between the adjacent doped epitaxial layers 140 is, the greater the electric field density of 140 between the adjacent doped epitaxial layers is, the more easily the breakdown phenomenon occurs, so as to obtain a lower trigger voltage, i.e. the smaller the distance between the adjacent doped epitaxial layers 140 is, the lower the trigger voltage of the formed electrostatic discharge protection structure 140 is; in the present embodiment, the doped epitaxial layers 140 are "Σ" shaped epitaxial layers, and the smaller the distance between adjacent doped epitaxial layers 140, the smaller the distance between the sharp corners of the "Σ" shaped epitaxial layers, the easier the tip discharge phenomenon is caused, i.e. the lower the trigger voltage of the formed esd protection structure is. Therefore, the electrostatic discharge protection structure with unequal trigger voltages can be formed by adjusting the spacing distance between the adjacent doped epitaxial layers 140, thereby being beneficial to reducing the difficulty of the forming process and improving the yield.
In addition, the distance between adjacent doped epitaxial layers 140 cannot be too small, if the distance between adjacent doped epitaxial layers 140 is too small, it is difficult to achieve isolation between adjacent doped epitaxial layers, and the adjacent doped epitaxial layers 140 may communicate with each other, thereby affecting the reduction of the trigger voltage of the formed electrostatic discharge protection structure.
In this embodiment, the at least two doped epitaxial layers 140 are formed simultaneously. Specifically, the step of forming the at least two doped epitaxial layers 140 includes: referring to fig. 3 to 4, at least two recesses 143 are formed in the substrate 110 of the first doping region 131; referring to fig. 5, the doped epitaxial layer 240 is formed within the recess 143.
Specifically, the step of forming the groove 143 includes: as shown in fig. 3, a patterned mask layer 141 is formed on the substrate, the mask layer 141 has at least two openings 142 therein, and the bottom of the openings 142 exposes the substrate 110 of the first doping region 131; as shown in fig. 4, at least two grooves 143 are formed in the substrate 110 by using the mask layer 141 as a mask.
The patterned mask layer 141 is used to define the size and position of the doped epitaxial layer 140.
In this embodiment, the step of forming the patterned mask layer 141 includes: forming a mask material layer on the substrate; the mask material layer is patterned to form the patterned mask layer 141 and the opening 142.
In this embodiment, the patterned mask layer 141 is a hard mask layer, and may be formed by photolithography. The patterned mask layer 141 covers the second doped region 132, the gate structure 131 and a portion of the first doped region 131 of the substrate, and the opening 142 penetrates through the mask layer 141 to expose a portion of the surface of the first doped region 131.
The opening 142 in the mask layer 141 is used to expose the substrate 110 of the first doped region 131, and provides an operation surface for forming the groove 143. The number of openings 142 is equal to the number of doped epitaxial layers 140 formed. In this embodiment, 2 doped epitaxial layers 140 are formed as an example, so that the number of the openings 142 in the mask layer 141 is 2.
The recess 143 is used to provide a process space for the formation of the doped epitaxial layer 240.
In this embodiment, the doped epitaxial layer 140 is a "Σ" shaped epitaxial layer, so the groove 143 is a "Σ" shaped groove having a sharp corner protruding away from the center. Specifically, the substrate 110 exposed by the opening 142 (as shown in fig. 3) is etched by wet etching, and the groove 143 is formed in the substrate 110.
In this embodiment, the process parameters for forming the groove 143 by wet etching include: the etching solution is tetramethylammonium hydroxide (TMAH) solution, the temperature of the etching solution is in the range of 15-70 ℃, and the etching time is in the range of 20-500 s. It should be noted that, in other embodiments of the present invention, the etching solution may also be a potassium hydroxide solution or an ammonia solution.
As shown in fig. 5, the step of forming the doped epitaxial layer 140 in the recess 143 (shown in fig. 4) includes: semiconductor material is filled into the groove 143 to form the doped epitaxial layer 140.
In this embodiment, the doped epitaxial layer 140 is formed in the groove 143 by epitaxial growth. Specifically, the material of the doped epitaxial layer 140 is different from the material of the substrate 110, and the material of the doped epitaxial layer 140 is doped silicon germanium or doped silicon carbon, so that silicon germanium or silicon carbon is epitaxially grown in the groove 143 to form the doped epitaxial layer 140.
In this embodiment, in the process of forming the doped epitaxial layer 140 by epitaxial growth, in-situ ion doping is performed, so that the doped epitaxial layer 140 has conductivity to serve as a drain region of the formed electrostatic discharge protection structure. The doped epitaxial layer 140 is an N-type doped epitaxial layer, so that in-situ N ion doping is performed during the process of filling the semiconductor material into the groove 143.
Referring to fig. 6, in the present embodiment, the forming method further includes: after the doped epitaxial layers 140 are formed, an electrostatic discharge implantation 144 is performed to form an electrostatic discharge doped region 145 in the substrate 110, wherein the electrostatic discharge doped region 145 is located below the at least two doped epitaxial layers 140.
The ESD implant 144 is used to form the ESD doped region 145; the formation of the esd doping region 145 is used to adjust the trigger voltage so that the trigger voltage of the formed esd protection structure meets the requirement of the esd protection function of the chip.
The implanted ions of the electrostatic discharge implant 144 include: one or more of group V elements. The V-group elements with different types, different dosages and different energies are injected, so that the function of modulating the trigger voltage of the formed electrostatic discharge protection structure can be realized, and the formed electrostatic discharge protection structure can meet the requirement of chip protection.
In this embodiment, the implanting ions of the esd implantation 144 may further include: one or two of N or C. The injection of N or C can also adjust the trigger voltage of the formed esd protection structure, and N or C reacts with the material of the substrate 110, which can improve the accuracy of trigger voltage adjustment.
In this embodiment, as shown in fig. 3 to 5, in the process of forming the doped epitaxial layer 140, a patterned mask layer 141 is formed on the substrate; the mask layer 141 is used as an etching mask in the process of forming the doped epitaxial layer 140; the step of electrostatic discharge injection 144 therefore includes: the electrostatic discharge implantation is performed on the substrate on which the mask layer 141 is formed.
Since the mask layer 141 is formed on the substrate, the distribution of the esd implantation 144 in the esd doping region 145 formed in the substrate 110 is not uniform, i.e. the distribution of the esd doping region 145 is not uniform in a plane parallel to the surface of the substrate 110. The non-uniform ESD doped region 145 can further reduce the trigger voltage of the ESD protection structure, which is beneficial to the ESD protection function.
Referring to fig. 7, a voltage-current characteristic curve of the esd protection structure formed by different processes is shown.
The horizontal axis in the figure represents the voltage between the source region and the drain region of the electrostatic discharge protection structure, and the unit is V; the vertical axis represents the current density between the source and drain regions of the ESD protection structure in A/μm2。
A graph 711 shows a voltage-current characteristic curve of the esd protection structure, in which the esd injection is performed on the substrate without the mask layer, i.e., the esd doping regions are uniformly distributed; a graph 712 shows a current-voltage characteristic of an esd protection structure with a non-uniform distribution of esd doping regions, which is an esd implant performed on the substrate with the mask layer formed thereon.
When the current density is increased sharply, the electrostatic discharge protection structure is broken down, so that when the current density is increased sharply, the voltage between the source region and the drain region corresponding to the current density is the trigger voltage of the electrostatic discharge protection structure.
As shown in fig. 7, the breakdown voltage of the esd protection structure with the non-uniform distribution of esd doping regions represented by the graph 712 is lower than the breakdown voltage of the esd protection structure with the uniform distribution of esd doping regions represented by the graph 711, i.e. the trigger voltage of the esd protection structure with the non-uniform distribution of esd doping regions is lower than the trigger voltage of the esd protection structure with the uniform distribution of esd doping regions. Specifically, in this embodiment, the trigger voltage of the esd protection structure shown by the graph 711 is 9.66V, and the trigger voltage of the esd protection structure shown by the graph 712 is 9.12V.
In this embodiment, as shown in fig. 3 to 5, the patterned mask layer 141 is used as an etching mask to form a groove 143 in the substrate 110 during the process of forming the at least two doped epitaxial layers 140; as shown in fig. 6, the patterned mask layer 141 is used to shield a portion of the substrate during the esd implantation process to form an esd doping region 145 with non-uniform distribution; the formation of the doped epitaxial layer 140 and the electrostatic discharge implantation 144 are performed by using the same patterned mask layer 141, so that the use of the mask layer can be reduced, the process complexity can be reduced, the alignment problem can be avoided, the process difficulty can be reduced, and the yield and the performance of the formed electrostatic discharge protection structure can be improved.
In other embodiments of the present invention, after the groove is formed, the patterned mask layer may also be removed, so as to avoid adverse effects of the patterned mask layer on the formation of the doped epitaxial layer; after the doped epitaxial layer is formed and before the electrostatic discharge injection is carried out, a graphical mask layer is formed on the substrate again, and an opening with the bottom exposing the doped epitaxial layer is formed in the mask layer; and performing the electrostatic discharge injection on the substrate with the mask layer, and forming an electrostatic discharge injection region in non-uniform distribution. By the method, the influence of the patterned mask layer on the formation of the doped epitaxial layer can be reduced, and the yield is improved.
In other embodiments of the present invention, after forming the substrate and before forming the at least two doped epitaxial layers, the forming method includes: forming an oxide layer, wherein the oxide layer covers the substrate and the grid structure on the substrate; in the process of forming the doped epitaxial layer, the oxide layer is etched, and the oxide layer at the position of the doped epitaxial layer is removed, so that the oxide layer is also a graphical oxide layer, and an opening for exposing the doped epitaxial layer is formed in the oxide layer; therefore, after the grooves are formed and the patterned mask layer is removed, the oxide layer can also be used as the mask for electrostatic discharge implantation, so that the electrostatic discharge implantation regions which are not uniformly distributed are formed. When the oxide layer is used as a mask for the electrostatic discharge injection, the mask layer is made of silicon oxide.
Referring to fig. 8 and 9, a first plug 161 electrically connected to the doped epitaxial layer 140 and a second plug 162 electrically connected to the second doped region 132 are formed.
The first plug 161 is electrically connected with the doped epitaxial layer 140 serving as a drain region, and serves as a drain electrode of the formed electrostatic discharge protection structure for discharging electrostatic current; the second plug 162 is electrically connected to the second doped region 132 serving as a source region, and serves as a source electrode of the formed esd protection structure for inputting an electrostatic current.
The number of the first plugs 161 is at least two, and the at least two first plugs 161 are connected to the at least two doped epitaxial layers 140 in a one-to-one correspondence manner. In this embodiment, the number of the doped epitaxial layers 140 is 2, so the number of the first plugs 161 is also 2, and the 2 first plugs 161 are respectively connected to the 2 doped epitaxial layers 140 in a one-to-one correspondence manner. The formation of the first plugs 161 connected to the at least two doped epitaxial layers 140 in a one-to-one correspondence enables the at least two doped epitaxial layers 140 to be connected to different potentials, so that the formed electrostatic discharge protection structure can be broken down at different voltages, that is, a function of multiple trigger voltages can be realized, and thus the performance of the formed electrostatic discharge protection structure can be effectively improved.
The first plug 161 and the second plug 162 may be simultaneously formed. Specifically, the step of forming the first plug 161 and the second plug 162 includes: as shown in fig. 8, the mask layer 141 (shown in fig. 6) is removed to expose the substrate and the at least two doped epitaxial layers 140; as shown in fig. 9, an interlayer dielectric layer 150 is formed on the substrate; forming a second contact hole (not shown) and at least two first contact holes (not shown) in the interlayer dielectric layer 150, wherein the first contact hole and the second contact hole both penetrate through the interlayer dielectric layer 150, the doped epitaxial layer 140 is exposed at the bottom of the first contact hole, and the substrate 110 of the second doped region 132 is exposed at the bottom of the second contact hole; the second plug 162 is located in the second contact hole after the first plug 161 located in the first contact hole is formed.
The step of removing the mask layer 141 is to expose the substrate and the doped epitaxial layer 140. In this embodiment, the mask layer 141 is removed by wet etching. In other embodiments of the present invention, other suitable methods may be adopted to remove the mask layer 141 according to the material thereof, so as to reduce the influence of the removal process on the performance of the formed esd protection structure.
The interlevel dielectric layer 150 is used to achieve electrical isolation between adjacent semiconductor structures. In this embodiment, the interlayer dielectric layer 150 is made of silicon oxide. In other embodiments of the present invention, the material of the interlayer dielectric layer 150 may also be other dielectric materials.
It should be noted that, in order to prevent the first contact hole forming process and the second contact hole forming process from damaging the doped epitaxial layer 140 and the second doped region 132, in this embodiment, the forming method further includes: before the interlayer dielectric layer 150 is formed, a contact hole etching stop layer is formed.
The first contact hole and the second contact hole may be simultaneously formed. Specifically, the step of forming the first contact hole and the second contact hole includes: and etching the interlayer dielectric layer in a mask etching mode to form the first contact hole and the second contact hole.
The material of the first plug 161 and the second plug 162 is metal. Specifically, the material of the first plug 161 and the second plug 162 may be selected from one or more of tungsten, aluminum, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum, or copper.
The step of forming the first and second plugs 161 and 162 includes: filling a metal material into the first contact hole and the second contact hole, wherein the metal material covers the top of the interlayer dielectric layer 150; the metal material on the top of the interlayer dielectric layer 150 is removed by a planarization process to form the first plug 161 and the second plug 162.
Correspondingly, the invention also provides an electrostatic discharge protection structure. Referring to fig. 9, a cross-sectional structure diagram of an esd protection structure according to an embodiment of the invention is shown.
The electrostatic discharge protection structure includes: the substrate comprises a substrate 110, a gate structure 120 located on the substrate 110, and a first doping region 131 and a second doping region 132 respectively located in the substrate 110 on two sides of the gate structure 120; at least two doped epitaxial layers 140 located in the first doped region 140 and spaced apart from each other by the at least two doped epitaxial layers 140; a first plug 161 electrically connected to the doped epitaxial layer 140; a second plug 162 electrically connected to the second doped region 132.
The substrate is used for providing a process operation foundation.
The substrate 110 can provide a process platform.
In this embodiment, the substrate 110 is made of monocrystalline silicon. In other embodiments of the present invention, the material of the substrate may also be selected from polysilicon, amorphous silicon, or other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In other embodiments of the present invention, the substrate may also be a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate, or other types of substrates. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the esd protection structure is a planar device, so the substrate 110 is a planar substrate. In other embodiments of the present invention, the esd protection structure may also be a three-dimensional device with a fin structure; when the esd protection structure is a three-dimensional device, the substrate may include a planar substrate and a fin protruding from the planar substrate.
The gate structure 120 is a gate structure of the esd protection structure, and can control the conduction and the cut-off of a channel of the esd protection structure.
The gate structure 120 includes: a gate dielectric layer (not shown) on the substrate 110 and a gate electrode on the gate dielectric layer. The gate dielectric layer is used for realizing the electrical isolation between the gate electrode and the channel in the substrate 110; the gate electrode is used to make a connection to an external circuit. In this embodiment, the gate structure 120 is a polysilicon gate structure; therefore, the gate dielectric layer is made of silicon oxide, and the gate electrode is made of polysilicon. In other embodiments of the present invention, the esd protection structure may also have a metal gate structure, that is, the gate structure may also be a metal gate structure.
As shown in fig. 9, in this embodiment, the esd protection structure further includes: a sidewall spacer (not shown) is disposed on the sidewall of the gate structure 120 to protect the gate structure 120 and to define the positions of the first doped region 131 and the second doped region 132.
The side wall can be made of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride, and can be of a single-layer structure or a laminated structure. In this embodiment, the sidewall is of a single-layer structure, and the material of the sidewall is silicon nitride.
The first doped region 131 is used as a part of the drain region of the electrostatic discharge protection structure; the second doped region 132 serves as a source region of the esd protection structure to input an electrostatic current.
In this embodiment, the esd protection structure is an N-type esd protection structure (NSD); therefore, the first doped region 131 and the second doped region 132 are N-type doped regions, that is, the doped ions in the first doped region 131 and the second doped region 132 are N-type ions, such as P, As or Sb.
In this embodiment, the doped ions in the first doped region 131 are P; the concentration of the doped ions is 5E19atom/cm3To 5E22atom/cm3Within the range; the second doping region 132 has P-doped ions; the concentration of the doped ions is 5E19atom/cm3To 5E22atom/cm3Within the range.
The at least two doped epitaxial layers 140 are used together with the first doped region 131 as a drain of the esd protection structure to output an electrostatic current.
The first doping area 131 and the at least two doping epitaxial layers 140 form the drain of the electrostatic discharge protection structure, so that the gradient of the concentration of doped ions in the drain of the electrostatic discharge protection structure can be effectively improved, the probability of breakdown of the electrostatic discharge protection structure can be effectively increased, the trigger voltage of electrostatic discharge protection can be reduced, the protection function of the electrostatic discharge protection structure can be exerted, and the requirement of the electrostatic discharge protection function of a chip can be met.
In this embodiment, the material of the doped epitaxial layer 140 is different from the material of the substrate 110, which can effectively increase the electric field density between the source and the drain of the esd protection structure, thereby facilitating the reduction of the trigger voltage of the esd protection and the exertion of the protection function of the esd protection structure.
Specifically, the substrate 110 is made of silicon; the material of the doped epitaxial layer 140 may be doped silicon germanium or doped silicon carbon. The application range of the germanium-silicon or carbon-silicon material is wider, and the material of the doped epitaxial layer is set to be doped germanium-silicon or doped carbon-silicon, so that the process compatibility of the electrostatic discharge protection structure can be effectively improved, the yield can be improved, and the cost can be reduced.
The number of the doped epitaxial layers 140 is at least two, that is, at least two doped epitaxial layers 140 are disposed in the first doped region 131. By setting the number of the doped epitaxial layers 140 to be at least two, an electric field can be formed between the adjacent doped epitaxial layers 140, so that the trigger voltage of the electrostatic discharge protection structure can be effectively reduced, and the purpose of leakage current suppression can be achieved.
And the number of the doped epitaxial layers 140 is set to be at least two, and the at least two doped epitaxial layers 140 can be connected with different potentials, so that the electrostatic discharge protection structure can be broken down under different voltages, that is, the function of multiple trigger voltages can be realized, and the performance of the electrostatic discharge protection structure can be effectively improved.
In this embodiment, 2 doped epitaxial layers 140 are taken as an example for description. In other embodiments of the present invention, the number of the doped epitaxial layers may also be more than 2.
The doping types of the at least two doped epitaxial layers 140 are the same as the doping type of the first doped region 131, in this embodiment, the esd protection structure is an N-type electrostatic discharge protection structure (NSD), and the first doped region 131 is an N-type doped region; the at least two doped epitaxial layers 140 are N-type doped epitaxial layers 140 and the dopant ions may be one or more of P, As or Sb. Specifically, the doping concentration of the doped epitaxial layer 140 is 1E19atom/cm3To 1E21atom/cm3Within the range.
In the present embodiment, the doped epitaxial layer 140 is a "Σ" shaped epitaxial layer. The doped epitaxial layer 140 is a sigma-shaped epitaxial layer, so that the doped epitaxial layer 140 has a sharp corner protruding away from the center of the doped epitaxial layer 140, and at the sharp corner, the electric field density of the doped epitaxial layer 140 is high, which can effectively improve the probability of the occurrence of the point discharge phenomenon, is beneficial to the reduction of the trigger voltage, and is beneficial to the exertion of the protection function of the electrostatic discharge protection structure.
It should be noted that, the at least two adjacent doped epitaxial layers 140 are disposed at intervals, that is, in a plane parallel to the surface of the substrate 110, the at least two epitaxial doped layers 140 are arranged along a direction away from the gate structure 120, and a certain gap exists between the adjacent epitaxial doped layers 140.
The distance between adjacent doped epitaxial layers 140 is related to the trigger voltage of the electrostatic discharge protection structure: the smaller the distance between the adjacent doped epitaxial layers 140 is, and the larger the electric field density of the adjacent doped epitaxial layers 140 is, the more easily the breakdown phenomenon occurs, so as to obtain a lower trigger voltage, that is, the smaller the distance between the adjacent doped epitaxial layers 140 is, the lower the trigger voltage of the electrostatic discharge protection structure 140 is; in the present embodiment, the doped epitaxial layers 140 are "Σ" shaped epitaxial layers, and the smaller the distance between adjacent doped epitaxial layers 140, the smaller the distance between the sharp corners of the "Σ" shaped epitaxial layers, the easier the tip discharge phenomenon is caused, i.e. the lower the trigger voltage of the esd protection structure is.
In addition, the distance between adjacent doped epitaxial layers 140 cannot be too small, if the distance between adjacent doped epitaxial layers 140 is too small, it is difficult to achieve isolation between adjacent doped epitaxial layers, and the adjacent doped epitaxial layers 140 may communicate with each other, thereby affecting the reduction of the trigger voltage of the esd protection structure.
In this embodiment, the esd protection structure further includes: an electrostatic discharge doped region 145 in the substrate 110 below the at least two doped epitaxial layers 140.
The formation of the esd doping region 145 is used to adjust the trigger voltage so that the trigger voltage of the esd protection structure meets the requirement of the esd protection function of the chip.
The dopant ions in the esd doped region 145 include: one or more of group V elements. The V-group elements with different types, different dosages and different energies are injected, so that the function of modulating the trigger voltage of the electrostatic discharge protection structure can be realized, and the electrostatic discharge protection structure can meet the requirement of chip protection.
In this embodiment, the doping ions in the esd doping region 145 may further include: one or two of N or C. The electrostatic discharge doped region 145 is doped with N or C, which can also adjust the trigger voltage of the electrostatic discharge protection structure, and the N or C reacts with the material of the substrate 110, which can improve the precision of the trigger voltage adjustment.
In this embodiment, the esd doping regions 145 are non-uniformly distributed esd doping regions, i.e. in a plane parallel to the surface of the substrate 110, the distribution of the esd doping regions 145 is not uniform. The non-uniform esd doping region 140 can further reduce the trigger voltage of the esd protection structure, which is beneficial to the performance of the esd protection function.
The first plug 161 is electrically connected to the doped epitaxial layer 140 serving as a drain region, serving as a drain electrode of the electrostatic discharge protection structure, and configured to discharge an electrostatic current; the second plug 162 is electrically connected to the second doped region 132 serving as a source region, serving as a source electrode of the esd protection structure, for inputting an electrostatic current.
The number of the first plugs 161 is equal to the number of the doped epitaxial layer 140, and the first plugs 161 are connected to the doped epitaxial layer 140 in a one-to-one correspondence manner. In this embodiment, the number of the doped epitaxial layers 140 is 2, so the number of the first plugs 161 is also 2, and the 2 first plugs 161 are respectively connected to the 2 doped epitaxial layers 140 in a one-to-one correspondence manner. By the method, the at least two doped epitaxial layers 140 can be respectively connected with different potentials, so that the electrostatic discharge protection structure can be broken down under different voltages, that is, the function of multiple trigger voltages can be realized, and the performance of the electrostatic discharge protection structure can be effectively improved.
It should be noted that, in this embodiment, the electrostatic discharge protection structure further includes: an interlevel dielectric layer 150 on the substrate. The interlevel dielectric layer 150 is used to achieve electrical isolation between adjacent semiconductor structures. In this embodiment, the interlayer dielectric layer 150 is made of silicon oxide. In other embodiments of the present invention, the material of the interlayer dielectric layer 150 may also be other dielectric materials.
The material of the first plug 161 and the second plug 162 is metal. Specifically, the material of the first plug 161 and the second plug 162 may be selected from one or more of tungsten, aluminum, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum, or copper.
In summary, the first doped region and the at least two doped epitaxial layers form the drain of the electrostatic discharge protection structure, so that the gradient of the doped ion concentration of the drain of the electrostatic discharge protection structure can be effectively improved, and the trigger voltage of electrostatic discharge protection can be reduced. Moreover, the materials of the at least two doped epitaxial layers are different from the substrate material, so that the electric field density between the source electrode and the drain electrode of the electrostatic discharge protection structure can be effectively increased, and the trigger voltage of electrostatic discharge protection can be reduced. The material of the doped epitaxial layer can be doped silicon germanium or doped silicon carbon. The application range of the germanium-silicon or carbon-silicon material is wider, the process compatibility of the electrostatic discharge protection structure can be effectively improved, the yield can be improved, and the cost can be reduced. The doped epitaxial layer is a sigma-shaped doped epitaxial layer. The sigma-shaped doped epitaxial layer can effectively improve the probability of point discharge and is beneficial to reducing the trigger voltage. After the at least two doped epitaxial layers are formed, forming an electrostatic discharge doping region in the substrate below the at least two doped epitaxial layers through electrostatic discharge injection; the electrostatic discharge doped region can modulate the trigger voltage, so that the formed electrostatic discharge protection structure meets the requirements of the electrostatic discharge protection function of the chip. The concentration distribution of doped ions in the electrostatic discharge doped region is not uniform, and the non-uniform electrostatic discharge doped region can further reduce the trigger voltage of the electrostatic discharge protection structure, thereby being beneficial to the exertion of the electrostatic discharge protection function. The formation of the doped epitaxial layer and the electrostatic discharge injection can be carried out by adopting the same graphical mask layer, so that the use of the mask layer can be reduced, the process complexity can be reduced, the alignment problem can be avoided, the process difficulty can be reduced, and the yield and the performance of the formed electrostatic discharge protection structure can be improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method for forming an electrostatic discharge protection structure, comprising:
forming a base, wherein the base comprises a substrate, a grid structure positioned on the substrate, and a first doped region and a second doped region which are respectively positioned in the substrate at two sides of the grid structure;
forming at least two doped epitaxial layers in the substrate of the first doped region, wherein the at least two doped epitaxial layers are arranged at intervals, and the bottom of each doped epitaxial layer is lower than that of the first doped region;
and forming a first plug electrically connected with the doped epitaxial layer and a second plug electrically connected with the second doped region.
2. The method of forming of claim 1, wherein a material of the doped epitaxial layer is different from a material of the substrate.
3. The forming method according to claim 1 or 2, wherein the substrate material is silicon; the doped epitaxial layer is made of doped silicon germanium or doped silicon carbon.
4. The method of claim 1, wherein the doped epitaxial layer has a doping concentration of 1E19atom/cm3To 1E21atom/cm3Within the range.
5. The method of forming of claim 1, wherein the doped epitaxial layer is a "Σ" shaped epitaxial layer.
6. The method of forming of claim 1, wherein forming the doped epitaxial layer comprises:
forming at least two grooves in the substrate of the first doping area;
and forming the doped epitaxial layer in the groove.
7. The method of forming of claim 6, wherein the doped epitaxial layer is formed within the recess by means of epitaxial growth.
8. The method of claim 7, wherein in-situ ion doping is performed during epitaxial growth to form the doped epitaxial layer.
9. The method of forming as claimed in claim 1, further comprising: after the doped epitaxial layers are formed and before the first plug and the second plug are formed, performing electrostatic discharge injection, and forming an electrostatic discharge doped region in the substrate, wherein the electrostatic discharge doped region is positioned below the at least two doped epitaxial layers.
10. The method of forming as claimed in claim 9, further comprising: after the at least two epitaxial layers are formed and before the electrostatic discharge injection is carried out, a patterned mask layer is formed on the substrate, and an opening with the bottom exposing the doped epitaxial layers is formed in the mask layer; and carrying out the electrostatic discharge injection on the substrate with the mask layer.
11. The method of forming of claim 9, wherein forming the at least two doped epitaxial layers comprises:
forming a patterned mask layer on the substrate, wherein the mask layer is provided with at least two openings, and the bottom of each opening exposes the substrate of the first doping region;
forming at least two grooves in the substrate by taking the mask layer as a mask;
forming the doped epitaxial layer in the groove;
and carrying out the electrostatic discharge injection on the substrate with the mask layer.
12. The method of claim 10 or 11, wherein the mask layer is a hard mask layer.
13. The method of claim 10, wherein the material of the mask layer is silicon oxide.
14. The method of forming as claimed in any of claims 9 to 11, wherein said implanting ions for electrostatic discharge implantation comprises: one or more of group V element ions.
15. The method of forming of claim 14, wherein the electrostatic discharge implanted ions further comprise: one or two of N or C.
16. The method of claim 1, wherein the number of the first plugs is equal to the number of the doped epitaxial layers, and the first plugs are connected to the doped epitaxial layers in a one-to-one correspondence.
17. An electrostatic discharge protection structure, comprising:
the substrate comprises a substrate, a grid structure positioned on the substrate, and a first doped region and a second doped region which are respectively positioned in the substrate at two sides of the grid structure;
the at least two doped epitaxial layers are positioned in the first doped region and are arranged at intervals, and the bottom of each doped epitaxial layer is lower than that of the first doped region;
a first plug electrically connected to the doped epitaxial layer;
and the second plug is electrically connected with the second doping region.
18. The esd-protection structure of claim 17, wherein a material of the doped epitaxial layer is different from a material of the substrate.
19. Such asThe esd-protection structure of claim 17, wherein the doped epitaxial layer has a doping concentration of 1E19atom/cm3To 1E21atom/cm3Within the range.
20. The esd-protection structure of claim 17, wherein the doped epitaxial layer is a sigma-shaped epitaxial layer.
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