CN109085466B - Photomask electrostatic discharge defect detection method - Google Patents
Photomask electrostatic discharge defect detection method Download PDFInfo
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- CN109085466B CN109085466B CN201810768575.6A CN201810768575A CN109085466B CN 109085466 B CN109085466 B CN 109085466B CN 201810768575 A CN201810768575 A CN 201810768575A CN 109085466 B CN109085466 B CN 109085466B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/12—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing
- G01R31/1218—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing using optical methods; using charged particle, e.g. electron, beams or X-rays
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/12—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing
- G01R31/1227—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials
- G01R31/1263—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials of solid or fluid materials, e.g. insulation films, bulk material; of semiconductors or LV electronic components or parts; of cable, line or wire insulation
- G01R31/129—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials of solid or fluid materials, e.g. insulation films, bulk material; of semiconductors or LV electronic components or parts; of cable, line or wire insulation of components or parts made of semiconducting materials; of LV components or parts
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Abstract
The invention relates to a photomask electrostatic discharge defect detection method, which relates to the semiconductor integrated circuit manufacturing technology, and comprises the following steps of S1: generating a position information file related to the electrostatic discharge defect phenomenon of the photomask through graphic analysis software; s2: the electronic scanning machine station selects a monitoring point according to the position information file related to the photomask static electricity discharge defect phenomenon, and captures the exposed image of the wafer corresponding to the monitoring point; and S3: the image analysis software analyzes the image captured by the electronic scanning machine to generate an image size offset file and a detection method for detecting the electrostatic discharge defect phenomenon.
Description
Technical Field
The present invention relates to semiconductor integrated circuit manufacturing technology, and more particularly, to a method for detecting electrostatic discharge defects of a photomask.
Background
In the manufacturing process of semiconductor integrated circuits, the adverse effect of abnormal deviation of pattern size on the device performance is more and more significant with the development of integrated circuit processes.
Since the photomask is put into semiconductor production by itself, due to the influence of self-design defects, chemical solutions during the photolithography operation, storage conditions, and the like, a partial region is prone to generate an Electro-Static discharge (ESD) phenomenon, such as a region with a small metal interval in the photomask, a metal tip in the photomask, or a metal corner region in the photomask, as shown in fig. 1, thereby causing an image size abnormality after wafer exposure, as shown in fig. 2. After the photomask has the electrostatic discharge defect, the photomask is gradually deteriorated along with the time and cannot be completely repaired, and the production of a new photomask needs a certain period, during which the production capacity ratio and the scanning time of the photomask scanner are long, one photomask is generally scanned once in 15 days, the monitoring frequency is low, and the timeliness is poor, so that the problems of risk control and reduction of the production capacity loss are urgently to be solved.
Therefore, there is a need for a testing method capable of detecting electrostatic discharge defects in time during the manufacturing process of semiconductor integrated circuits.
Disclosure of Invention
The invention aims to provide a photomask static electricity discharge defect detection method and a photomask static electricity discharge defect phenomenon discovered in the method.
The invention provides a photomask electrostatic discharge defect detection method, which comprises the following steps: s1: generating a position information file related to the electrostatic discharge defect phenomenon of the photomask through graphic analysis software; s2: the electronic scanning machine station selects a monitoring point according to the position information file related to the photomask static electricity discharge defect phenomenon, and captures the exposed image of the wafer corresponding to the monitoring point; and S3: and the image analysis software analyzes the image captured by the electronic scanning machine to generate an image size offset file.
Further, in step S1, the mask pattern file is analyzed by the pattern analysis software to find out the structural coordinate information of the chip unit where the electrostatic discharge defect easily occurs, and generate the position information file where the electrostatic discharge defect easily occurs; generating a position information file of the electrostatic discharge defect phenomenon through graphic analysis software aiming at the electrostatic discharge defect phenomenon discovered by the photomask scanner scanning the photomask; and obtaining the position information file related to the electrostatic discharge defect phenomenon of the photomask according to the position information file which is easy to generate the electrostatic discharge defect phenomenon and the position information file of the electrostatic discharge defect phenomenon.
Further, in step S1, the mask pattern file is analyzed by the pattern analysis software to find the structural coordinate information of the chip unit where the electrostatic discharge defect easily occurs, and generate the position information file where the electrostatic discharge defect easily occurs, and the position information file related to the mask electrostatic discharge defect is obtained according to the position information file where the electrostatic discharge defect easily occurs.
Further, the step S2 includes selecting the monitoring points in units of chip units, and the electronic scanning machine taking a snapshot of each chip unit.
Further, step S2 includes selecting the monitoring points in units of exposure areas, and capturing the images of the exposure areas one by an electronic scanning machine.
Further, the step S2 includes selecting the monitor point in units of exposed wafers, and the electronic scanning machine taking a snapshot of each wafer.
Further, the method further includes step S4: and judging whether the photomask has the electrostatic discharge defect phenomenon or not according to the image size offset file generated in the step S3.
Furthermore, if the image size offset is greater than or equal to a set value, the photomask is considered to have the electrostatic discharge defect phenomenon, and the photomask needs to be subjected to risk assessment; if the image size offset is smaller than the set value, the cover is not considered to have the electrostatic discharge defect phenomenon.
Further, step S2 includes selecting different wafers according to the production sequence during the semiconductor integrated circuit production process, and capturing the exposed images of the wafers corresponding to the selected monitor points.
Further, step S3 further includes S31: and the image analysis software analyzes the image captured by the electronic scanning machine and generates an image size offset monitoring chart according to the images captured for multiple times.
The photomask static electricity release defect detection method provided by the invention generates a position information file related to a photomask static electricity release defect phenomenon in advance through graphic analysis software, then an electronic scanning machine selects a monitoring point according to the position information file related to the photomask static electricity release defect phenomenon, a wafer exposed image corresponding to the monitoring point is captured, then the graphic analysis software analyzes the image captured by the electronic scanning machine to generate an image size offset file so as to monitor the wafer exposed image size, so that the photomask static electricity release defect phenomenon detection method is more convenient, the cost is lower, and the photomask static electricity release defect phenomenon can be found in time.
Drawings
FIG. 1 is a schematic diagram illustrating a local electrostatic discharge phenomenon generated by a photomask.
FIG. 2 is a diagram illustrating an image size anomaly after wafer exposure.
FIG. 3 is a flowchart illustrating a method for detecting electrostatic discharge defects of a mask according to an embodiment of the present invention.
Fig. 4 is a schematic diagram illustrating distribution of electrostatic discharge defects in a chip unit according to an embodiment of the invention.
FIG. 5 is a schematic diagram illustrating the distribution of the chip units with ESD defects in the mask according to one embodiment of the present invention.
FIG. 6 is a schematic diagram illustrating an image size shift of a wafer after exposure according to an embodiment of the present invention.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In an embodiment of the present invention, a method for detecting a mask electrostatic discharge defect is provided, please refer to fig. 3, and fig. 3 is a flowchart of the method for detecting a mask electrostatic discharge defect according to an embodiment of the present invention. Specifically, as shown in fig. 3, the method includes:
s1: and generating a position information file related to the electrostatic discharge defect phenomenon of the photomask by using graphic analysis software.
Specifically, in the first embodiment of the present invention, the mask pattern file is analyzed by the pattern analysis software to find out the structural coordinate information of the chip unit where the electrostatic discharge defect easily occurs, and to generate the position information file where the electrostatic discharge defect easily occurs. Specifically, referring to fig. 4, fig. 4 is a schematic diagram illustrating distribution of electrostatic discharge defects easily occurring in a chip unit according to an embodiment of the invention. As shown in fig. 4, the mask pattern file is analyzed by the pattern analysis software to find that the structure with the coordinate position (x1, y1) in the chip unit 310 is prone to generate the esd defect, and the structure with the coordinate position (x1, y1) is usually a region with a small metal interval in the mask, a metal tip in the mask, or a metal corner region in the mask. Referring to fig. 5, fig. 5 is a schematic diagram illustrating a distribution of chip units having an esd defect in a reticle according to an embodiment of the present invention, where the reticle is scanned by a reticle scanner to find out that the chip units 410 in the reticle have an esd defect and to determine coordinate information of the chip units 410 having an esd defect, as shown in fig. 5, the reticle may further include a plurality of chip units similar to the chip units 410, and the chip units may not have an esd defect and may have a structure similar to that of the chip units 410 having an esd defect, and thus belong to the chip units that are prone to have an esd defect, and the graphic analysis software is configured to find out the chip units having an esd defect, the coordinate information of the esd defect in the chip units, and the chip units having an esd defect according to the found out The chip units similar to the chip unit generate a position information file of the electrostatic discharge defect phenomenon. Of course, in an embodiment of the present invention, the location information file of the esd defect may also include only one or two information files of the chip unit where the esd defect occurs, the coordinate information of the esd defect occurring in the chip unit, and the chip unit similar to the chip unit where the esd defect occurs. Specifically, the position information file of the electrostatic discharge defect phenomenon can be generated through graphic analysis software according to the information of the photomask scanned by the photomask scanner at the last time. Then, the position information file related to the electrostatic discharge defect phenomenon of the photomask in step S1 is obtained according to the position information file of the easy electrostatic discharge defect phenomenon and the position information file of the electrostatic discharge defect phenomenon, for example, the position information file related to the electrostatic discharge defect phenomenon of the photomask in step S1 is obtained by combining the position information file of the easy electrostatic discharge defect phenomenon and the position information file of the electrostatic discharge defect phenomenon.
Specifically, in the second embodiment of the present invention, the mask pattern file is analyzed only by the pattern analysis software to find out the structural coordinate information of the chip unit where the electrostatic discharge defect easily occurs, and generate the position information file where the electrostatic discharge defect easily occurs, in the same manner as the position information file where the electrostatic discharge defect easily occurs in the first embodiment, which is not repeated herein, and then the position information file related to the mask electrostatic discharge defect in step S1 is obtained according to the position information file where the electrostatic discharge defect easily occurs.
The Pattern analysis software may be a defective Pattern analysis software (HPA), a Defective Pattern Library (DPL), or the like, and the type of the Pattern analysis software is not particularly limited as long as the Pattern analysis software can implement the above functions.
S2: and the electronic scanning machine station selects monitoring points according to the position information file related to the photomask static electricity discharge defect phenomenon, and captures the exposed images of the wafer corresponding to the monitoring points.
In an embodiment of the present invention, the monitoring points may be selected in units of chip units, and the electronic scanning machine captures the wafer images of the wafer exposed by the coordinate points (x1, y1) in the chip units 310 one by one, as shown in fig. 4. In an embodiment of the present invention, the monitoring points may be selected in units of exposure areas, and the electronic scanning machine performs snapshot on the exposure areas one by one, as shown in fig. 5, to snapshot the exposed image of the wafer corresponding to the chip unit 410 in the exposure area. In an embodiment of the present invention, the monitoring points can be selected by taking the exposed wafer as a unit, and the electronic scanning machine can capture the wafers one by one. Of course, there may be other ways to select the monitoring point, and the invention is not limited to this, and the way to select the monitoring point may be set according to the actual product requirement.
S3: and the image analysis software analyzes the image captured by the electronic scanning machine to generate an image size offset file.
Therefore, in the production process of the semiconductor integrated circuit, the wafer can be selected at any time, and the exposed image of the wafer corresponding to the selected monitoring point is captured to detect the size of the exposed pattern of the wafer, so that the electrostatic discharge defect phenomenon of the photomask is correspondingly detected. For the detection of the electrostatic discharge defect of the photomask, the industry is dedicated to finding the electrostatic discharge defect phenomenon of the photomask as soon as possible by increasing the frequency of scanning the photomask by a photomask scanner, but the photomask scanner is expensive, low in productivity ratio and long in scanning time, and has no breakthrough all the time, but the invention develops a new way, generates a position information file related to the electrostatic discharge defect phenomenon of the photomask in advance by graphic analysis software, then an electronic scanning machine selects a monitoring point according to the position information file related to the electrostatic discharge defect phenomenon of the photomask, captures an image after the wafer exposure corresponding to the monitoring point, then analyzes the image captured by the electronic scanning machine by the graphic analysis software, generates an image size offset file, monitors the size of the image after the wafer exposure, and thus the detection of the electrostatic discharge defect phenomenon of the photomask is more convenient, the cost is lower, the electrostatic discharge defect phenomenon of the photomask can be found in time, a brand new technical scheme is provided for technical personnel in the field, and the technical problem which is expected to be solved but can not be solved all the time is solved.
In an embodiment of the present invention, the method for detecting electrostatic discharge defects of a mask further includes step S4: and judging whether the photomask has the electrostatic discharge defect phenomenon or not according to the image size offset file generated in the step S3. Specifically, in an embodiment of the present invention, if the image size offset is greater than or equal to the set value, it is determined that the photomask has the electrostatic discharge defect, and the risk evaluation needs to be performed on the photomask; if the image size offset is smaller than the set value, the cover is not considered to have the electrostatic discharge defect phenomenon. In an embodiment of the present invention, the setting value can be set according to a requirement of an actual product, which is not limited in the present invention.
In an embodiment of the present invention, step S2 further includes: in the production process of the semiconductor integrated circuit, different wafers can be selected according to the production sequence, and the exposed images of the wafers corresponding to the selected monitoring points are captured. Step S3 further includes S31: and the image analysis software analyzes the image captured by the electronic scanning machine and generates an image size offset monitoring chart according to the images captured for multiple times. The graph for monitoring the image size deviation amount generated in this way monitors the variation trend of the image size deviation amount after the wafer exposure, and specifically, refer to the schematic diagram of the image size deviation after the wafer exposure shown in fig. 6. In the actual monitoring process, if the deviation amount of the exposed image size of the wafer corresponding to a certain monitoring point is close to a set value, the frequency of capturing the exposed image size of the wafer corresponding to the monitoring point can be increased, and the electrostatic discharge defect phenomenon of the photomask can be discovered in time.
In summary, a position information file related to the mask electrostatic discharge defect phenomenon is generated in advance through the graphic analysis software, then the electronic scanning machine selects a monitoring point according to the position information file related to the mask electrostatic discharge defect phenomenon, a wafer exposed image corresponding to the monitoring point is captured, then the graphic analysis software analyzes the image captured by the electronic scanning machine, and an image size offset file is generated to monitor the wafer exposed image size, so that the mask electrostatic discharge defect phenomenon detection is more convenient and lower in cost, and the mask electrostatic discharge defect phenomenon can be found in time.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (8)
1. A method for detecting electrostatic discharge defects of a photomask is characterized by comprising the following steps:
s1: analyzing the photomask graph file through graph analysis software, finding out the structure coordinate information of the chip unit in which the electrostatic discharge defect phenomenon easily occurs, and generating a position information file of the chip unit in which the electrostatic discharge defect phenomenon easily occurs; generating a position information file of the electrostatic discharge defect phenomenon through graphic analysis software aiming at the electrostatic discharge defect phenomenon discovered by the photomask scanner scanning the photomask; obtaining a position information file related to the electrostatic discharge defect phenomenon of the photomask according to the position information file which is easy to generate the electrostatic discharge defect phenomenon and the position information file of the electrostatic discharge defect phenomenon;
s2: the electronic scanning machine station selects a monitoring point according to the position information file related to the photomask static electricity discharge defect phenomenon, and captures the exposed image of the wafer corresponding to the monitoring point;
s3: the image analysis software analyzes the image captured by the electronic scanning machine to generate an image size offset file; and
s4: and judging whether the photomask has the electrostatic discharge defect phenomenon or not according to the image size offset file generated in the step S3.
2. The method as claimed in claim 1, wherein the step S1 is to analyze the mask pattern file by the pattern analysis software to find out the structural coordinate information of the chip unit where the esd event is likely to occur, generate the location information file where the esd event is likely to occur, and obtain the location information file related to the mask esd event according to the location information file where the esd event is likely to occur.
3. The method as claimed in claim 1, wherein the step S2 includes selecting the monitoring points in units of chip units, and capturing the image of each chip unit by an electronic scanning machine.
4. The method for detecting electrostatic discharge defects of a photomask according to claim 1, wherein the step S2 includes selecting the monitoring points in units of exposure areas, and capturing the images of the exposure areas one by an electronic scanning machine.
5. The method as claimed in claim 1, wherein the step S2 includes selecting the monitoring point for each exposed wafer, and capturing the wafer by wafer with an electronic scanning machine.
6. The method for detecting electrostatic discharge defects of a photomask according to claim 1, wherein if the image size offset is greater than or equal to a predetermined value, the photomask is determined to have electrostatic discharge defects and the photomask needs to be subjected to risk assessment; if the image size offset is smaller than the set value, the photomask is determined to have no electrostatic discharge defect phenomenon.
7. The method as claimed in claim 1, wherein the step S2 further comprises selecting different wafers according to the production sequence during the production of the semiconductor integrated circuit, and capturing the exposed images of the wafers corresponding to the selected monitor points.
8. The method for detecting electrostatic discharge defects of a photomask of claim 7, wherein the step S3 further comprises the step S31: and the image analysis software analyzes the image captured by the electronic scanning machine and generates an image size offset monitoring chart according to the images captured for multiple times.
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