CN109067388A - A kind of CML structure output driving stage circuit - Google Patents
A kind of CML structure output driving stage circuit Download PDFInfo
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- CN109067388A CN109067388A CN201811009953.9A CN201811009953A CN109067388A CN 109067388 A CN109067388 A CN 109067388A CN 201811009953 A CN201811009953 A CN 201811009953A CN 109067388 A CN109067388 A CN 109067388A
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- pmos tube
- tube
- common mode
- nmos tube
- output
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
Abstract
The invention discloses a kind of CML structure output driving stage circuits, comprising: first resistor R1, second resistance R2, output common mode clamp circuit M1, the first PMOS tube P1, the second PMOS tube P2, third PMOS tube P3, the first NMOS tube N1, the second NMOS tube N2, third NMOS tube N3 and terminating resistor RA.By the present invention in that controlling bridging resistance output common mode voltage with output common mode clamp circuit, can combine AC/DC mode can optimize the TX of power consumption；In circuit realization, one " fixation " bottom tail current source N3 is used and top tail current source P3 that one uses output common mode clamp circuit to control, make the bridging resistance stabilization of the CML under AC mode in reasonable operating voltage, it is no longer necessary to provide termination voltage；It is an adaptive TX in itself furthermore it is also possible to realize automatically to AC/DC mode tuning.
Description
Technical field
The present invention relates to IC design technical fields, are to be related to a kind of CML structure output driving stage electricity particularly
Road.
Background technique
Conventional CML structure output stage drive circuit power consumption and heating problem chip ever-reduced for scale are more and more prominent
Out, therefore, circuit designers constantly study the structure for saving power consumption, but many structures are only limited to AC or are only limited to DC mode,
Compatibility is not strong；Or AC/DC can work, but only one mode can save power consumption.
Summary of the invention
It is an object of the invention to propose a kind of CML structure output driving stage circuit, in AC operating mode and DC Working mould
Optimised power consumption is realized under formula.
In order to achieve the above objectives, the present invention provides following technical schemes:
A kind of CML structure output driving stage circuit, comprising: first resistor (R1), second resistance (R2), output common mode clamper
Circuit (M1), the first PMOS tube (P1), the second PMOS tube (P2), third PMOS tube (P3), the first NMOS tube (N1), the 2nd NMOS
Manage (N2), third NMOS tube (N3) and terminating resistor (RA), in which:
One end of the first resistor (R1) and the first end of the third PMOS tube (P3) are connected with supply voltage AVdd；
The other end of the first resistor (R1) is connected with one end of the second resistance (R2), the other end of the second resistance (R2)
Ground connection；
The common end of the first resistor (R1) and the second resistance (R2) and the output common mode clamp circuit (M1)
First end be connected, the control terminal phase of the second end of the output common mode clamp circuit (M1) and the third PMOS tube (P3)
Even, the third end of the output common mode clamp circuit (M1) is connected with the second end of first PMOS tube (P1), and and Out_N
It is connected；4th end of the output common mode clamp circuit (M1) is connected with the second end of second PMOS tube (P2), and with
Out_P is connected；
The second end of the third PMOS tube (P3) first end and described second with first PMOS tube (P1) respectively
The first end of PMOS tube (P2) is connected, and the control terminal of first PMOS tube (P1) is connected with In_P, second PMOS tube
(P2) control terminal is connected with In_N；
The second end of first PMOS tube (P1) is connected with the first end of first NMOS tube (N1), and described second
The second end of PMOS tube (P2) is connected with the first end of second NMOS tube (N2), the control terminal of first NMOS tube (N1)
It is connected with the In_P, the control terminal of second NMOS tube (N2) is connected with the In_N；
The second end of first NMOS tube (N1) is connected with the second end of second NMOS tube (N2), common end with
The first end of the third NMOS tube (N3) is connected, the second end ground connection of the third NMOS tube (N3), the third NMOS tube
(N3) control terminal inputs the second bias voltage Vbn；
The second end of first PMOS tube (P1) and the second end of second PMOS tube (P2) pass through the termination electricity
Hinder (RA) be connected；
The second end of first PMOS tube (P1) is connected with the Out_N, the second end of second PMOS tube (P2)
It is connected with the Out_P；
The third NMOS tube (N3) configures second biased electrical according to AC/DC connection type as bottom tail current source
Press Vbn；The third PMOS tube (P3) is used as top tail current source to do biasing by the output common mode clamp circuit and is controlled,
The output common mode clamp circuit forms feedback control loop, by comparing common-mode voltage VcomWith the practical common mode electrical level of output voltage,
Obtain the first bias voltage Vbp, by the first bias voltage VbpThe third PMOS tube (P3) is fed back to, the reality is defeated
Common mode electrical level is adjusted to the common-mode voltage V outcom。
Further, the output common mode clamp circuit include: 3rd resistor (R3), the 4th resistance (R4), capacitor (C) and
First operational amplifier (OP1), in which:
The resistance value of the 3rd resistor (R3) and the 4th resistance (R4) is equal；
The inverting input terminal of first operational amplifier (OP1) as the output common mode clamp circuit (M1) first
End, inputs the common-mode voltage Vcom；The normal phase input end of first operational amplifier (OP1) and the one end of the capacitor (C)
It is connected, the other end ground connection of the capacitor (C)；
One end of the capacitor (C) one end phase with one end of the 3rd resistor (R3) and the 4th resistance (R4) respectively
Even, fourth end and the Out_N phase of the other end of the 3rd resistor (R3) as the output common mode clamp circuit (M1)
Even；Third end and the Out_P phase of the other end of 4th resistance (R3) as the output common mode clamp circuit (M1)
Even；
The output end of first operational amplifier (OP1) is defeated as the second end of the output common mode clamp circuit (M1)
The first bias voltage V outbpIt is connected with the control terminal of the third PMOS tube (P3).
Further, first PMOS tube (P1), second PMOS tube (P2) and the third PMOS tube (P3)
First end be source electrode, second end is drain electrode, third end is grid.
Further, first NMOS tube (N1), second NMOS tube (N2) and the third NMOS tube (N3)
First end be drain electrode, second end is source electrode, third end is grid.
Further, further includes: swing-scanning control device (M2), the swing-scanning control device (M2) include: first end, second end and
Third end, in which:
The first end of the swing-scanning control device (M2) is connected with the second end of the output common mode clamp circuit (M1), receives
The first bias voltage Vbp, the second end reception target amplitude of oscillation voltage V of the swing-scanning control device (M2)mbf, the swing-scanning control
Second bias voltage V described in the three-polar output of device (M2)bnIt is connected with the control terminal of the third NMOS tube (N3)；
The swing-scanning control device (M2) is used to adjust the V according to AC/DC connection typebn。
Further, the swing-scanning control device (M2) includes: the 4th PMOS tube (P4), the 5th PMOS tube (P5), the 6th
PMOS tube (P6), the 4th NMOS tube (N4), second operational amplifier (OP2) and amplitude of oscillation resistance (RB), in which:
First end, the first end and the 6th PMOS tube of the 5th PMOS tube (P5) of 4th PMOS tube (P4)
(P6) first end is connected with the supply voltage AVdd；
Output common mode described in first end of the control terminal of 4th PMOS tube (P4) as the swing-scanning control device (M2)
The second end of clamp circuit (M1) is connected, and receives the first bias voltage Vbp；The second end of 4th PMOS tube (P4) and
The second end of 5th PMOS tube (P5) is connected, common end respectively with the amplitude of oscillation resistance (RB) one end and described second
The reverse input end of operational amplifier (OP2) is connected；
Amplitude of oscillation resistance (the RB) the other end be connected with the second end of the 4th NMOS tube (N4), and be grounded；It is described
The first end of 4th NMOS tube (N4) is connected with the second end of the 6th PMOS tube (P6) and control terminal；5th PMOS tube
(P5) control terminal is connected with the control terminal of the 6th PMOS tube (P6)；
The control terminal of 4th NMOS tube (N4) is connected with the output end of the second operational amplifier (OP2),
Second bias voltage V described in three-polar output of its common end as the swing-scanning control device (M2)bn；
Second end of the positive input of the second operational amplifier (OP2) as the swing-scanning control device (M2)
Receive target amplitude of oscillation voltage Vmbf。
Further, the 4th PMOS tube (P4), the 5th PMOS tube (P5) and the 6th PMOS tube (P6)
First end be source electrode, second end is drain electrode, third end is grid.
Further, the first end of the 4th NMOS tube (N4) is drain electrode, second end is source electrode, third end is grid.
It can be seen via above technical scheme that compared with prior art, the invention discloses a kind of drivings of CML structure output
Grade circuit, comprising: first resistor R1, second resistance R2, output common mode clamp circuit M1, the first PMOS tube P1, the second PMOS tube
P2, third PMOS tube P3, the first NMOS tube N1, the second NMOS tube N2, third NMOS tube N3 and terminating resistor RA, by upper and lower
The CML structure driving circuit of the equal double tail current sources of electric currents, completely bridging resistance and output common mode clamp circuit, in AC/DC mould
When formula switches, the first PMOS tube P1, the second PMOS tube P2 and third PMOS tube P3 can be automatically closed, and only need active arrangement bottom
Tail current needs to increase or reduce one times.By the present invention in that controlling the output of bridging resistance altogether with output common mode clamp circuit
Mode voltage, can combine AC/DC mode can optimize the TX of power consumption；In circuit realization, one " fixation " has been used
Bottom tail current source N3 and a top tail current source P3 controlled using output common mode clamp circuit, make under AC mode
The bridging resistance stabilization of CML is in reasonable operating voltage, it is no longer necessary to provide termination voltage；Furthermore it is also possible to realize it is automatic right
AC/DC mode tuning is an adaptive TX in itself.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the initiator block structure chart of the most common high-speed multimedia interface chip in the prior art；
Fig. 2 is the most common CML structure output driving stage circuit diagram in the prior art；
Fig. 3 is signal output waveform figure when AC is coupled in the prior art；
Fig. 4 is signal output waveform figure when DC is coupled in the prior art；
Fig. 5 is the double tail current source operation principle schematic diagrams of routine AC mode in the prior art；
Fig. 6 is the corresponding signal output waveform figure of the double tail current sources of routine AC mode in the prior art；
Fig. 7 is that routine DC mode bridges resistance performance schematic illustration in the prior art；
Fig. 8 is a kind of CML structure output driving stage circuit diagram provided in an embodiment of the present invention；
Fig. 9 is the schematic diagram of output common mode clamp circuit M1 provided in an embodiment of the present invention；
Figure 10 is another kind CML structure output driving stage circuit diagram provided in an embodiment of the present invention；
Figure 11 is the schematic diagram of swing-scanning control device M2 provided in an embodiment of the present invention.
Specific embodiment
As shown in Figure 1, for the initiator block structure chart of the most common high-speed multimedia interface chip in the prior art, packet
It includes: turning serial convertor 1, preceding driving 2, driving stage 3, terminating resistor 4 and electrostatic discharge protective circuit 5 parallel, it should be noted that
Capacitor C1 and C2 in Fig. 1 may be with or without according to different communications protocol, for example the pressure of DP, VB1 agreement must have,
HDMI agreement does not limit, it is thus possible to which having may also not have；Wherein, driving stage 3 is usually using CML as shown in Figure 2 as defeated
Driving stage circuit out, capacitor is with and without can work normally here.If Fig. 3 is signal output waveform figure when AC is coupled,
Fig. 4 is signal output waveform figure when DC is coupled, such as: terminating resistor RtermUnder normal conditions for 50 ohm (substantially all 40~
60 ohm), when high-speed data is sent, equivalent resistance is R after the TX resistance of CML differential pair output node and upper RX resistanceterm/
2=25 ohm, by taking the Single-end output amplitude of oscillation is 400mV as an example, the tail current I of Fig. 2 needs 16mA.
The output driving level structure of conventional CML structure is simple, and different coupled modes wide usages are strong, but power consumption is very big.
There is designer to be improved for the TX power consumption of AC coupling work mode, but just for AC mode, or
Although can be configured to two kinds of operating modes, only AC mode is to save power consumption module, and common CML knot is reduced under DC mode
Structure (for RX using the DC connection type of bridging resistance, is considered as AC mode) in the analysis of this paper.Above for the coupling side AC
Formula has all used double tail current source modes, as shown in figure 5, for the double tail current source operation principle schematic diagrams of routine AC mode.Such as
Shown in Fig. 5, all resistance are Rterm, high speed signal high speed COMS bus exchange switch, coupled capacitor AC conducting, with the instantaneous of a certain bit
For, work as N1, P2 switch disconnects, P1, and when N2 is closed the switch, there is I/4 electric current to flow through bridging resistance, Vdiff=I*Rterm/2,
The double corresponding signal output waveform figures of tail current source of conventional AC mode are as shown in fig. 6, comparison diagram 6 and Fig. 3, the only position of common mode
Different from, and differential mode voltage numerical value is the same, it is thereby achieved that only using half power consumption (AVdd*I/2), then output is same puts
The purpose of the signal of width.
Separately there is designer to be optimized for DC coupling work mode, for example TX terminating resistor is changed to by single-ended connection
Bridging is wherein one of measure, but the bridging resistance of usually CML structure is in the ac mode without termination voltage, cannot normal work
Make, as shown in fig. 7, bridging resistance performance schematic illustration for routine DC mode.Although the mode electric current for bridging resistance is I, and
Do not reduce, but is the power supply for being drawn from the end RX.Under normal conditions, TX is portable equipment, more harsh to power consumption requirements, and RX is electricity
Depending on or computer monitor, power supply capacity is abundant, thus achieved the purpose that save the end TX power consumption, signal output waveform figure such as Fig. 3
It is shown.
Although the TX power consumption above in relation to AC coupling work mode improve and can have been switched with the mode of configuration, and can
To use double tail current sources under (and DC mode of RX bridging resistance) in the ac mode, however can also be just for common DC mode
Often work, but it has been to revert to common CML structure, without any optimization.
For the mode of most common single tail current source switching current existing in Fig. 2, current efficiency is lower, TX power consumption
It is excessive, and the circuit for partially doing optimised power consumption respectively to AC mode and DC mode is difficult to compatible both of which again and all optimizes.Therefore,
It can apply to AC/DC both of which the purpose of the present invention is design is a, and the CML structure output of optimised power consumption may be implemented
Driving stage circuit.
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
As shown in figure 8, the circuit specifically includes the embodiment of the invention provides a kind of CML structure output driving stage circuit:
First resistor R1, second resistance R2, output common mode clamp circuit M1, the first PMOS tube P1, the second PMOS tube P2, third PMOS tube
P3, the first NMOS tube N1, the second NMOS tube N2, third NMOS tube N3 and terminating resistor RA, in which:
The first end of one end of above-mentioned first resistor R1 and above-mentioned third PMOS tube P3 are connected with supply voltage AVdd；It is above-mentioned
The other end of first resistor R1 is connected with one end of above-mentioned second resistance R2, the other end ground connection of above-mentioned second resistance R2；It is above-mentioned
The common end of first resistor R1 and above-mentioned second resistance R2 are connected with the first end of above-mentioned output common mode clamp circuit M1, above-mentioned defeated
The second end of common mode clamp circuit M1 is connected with the control terminal of above-mentioned third PMOS tube P3 out, above-mentioned output common mode clamp circuit M1
Third end be connected with the second end of above-mentioned first PMOS tube P1, and be connected with Out_N；Above-mentioned output common mode clamp circuit M1's
4th end is connected with the second end of above-mentioned second PMOS tube P2, and is connected with Out_P.
The second end of above-mentioned third PMOS tube P3 respectively with the first end of above-mentioned first PMOS tube P1 and above-mentioned 2nd PMOS
The first end of pipe P2 is connected, and the control terminal of above-mentioned first PMOS tube P1 is connected with In_P, the control terminal of above-mentioned second PMOS tube P2
It is connected with In_N；The second end of above-mentioned first PMOS tube P1 is connected with the first end of above-mentioned first NMOS tube N1, and above-mentioned second
The second end of PMOS tube P2 is connected with the first end of above-mentioned second NMOS tube N2, the control terminal of above-mentioned first NMOS tube N1 with it is above-mentioned
In_P is connected, and the control terminal of above-mentioned second NMOS tube N2 is connected with above-mentioned In_N.
The second end of above-mentioned first NMOS tube N1 is connected with the second end of above-mentioned second NMOS tube N2, common end with it is above-mentioned
The first end of third NMOS tube N3 is connected, the second end ground connection of above-mentioned third NMOS tube N3, the control of above-mentioned third NMOS tube N3
The second bias voltage V of end inputbn；The second end of above-mentioned first PMOS tube P1 and the second end of above-mentioned second PMOS tube P2 pass through upper
State terminating resistor RAIt is connected；The second end of above-mentioned first PMOS tube P1 is connected with above-mentioned Out_N, and the of above-mentioned second PMOS tube P2
Two ends are connected with above-mentioned Out_P；Above-mentioned third NMOS tube N3 configures as bottom tail current source according to AC/DC connection type above-mentioned
Second bias voltage Vbn；Above-mentioned third PMOS tube P3 conduct top tail current source does biasing by above-mentioned output common mode clamp circuit and adds
With control, above-mentioned output common mode clamp circuit forms feedback control loop, by comparing common-mode voltage VcomIt is total with the reality of output voltage
Mould level obtains the first bias voltage Vbp, by above-mentioned first bias voltage VbpAbove-mentioned third PMOS tube P3 is fed back to, it will be above-mentioned
Reality output common mode electrical level is adjusted to above-mentioned common-mode voltage Vcom。
It should be noted that eventually flowing to bottom tail electricity since entire differential pair total current is from the extraction of top tail current source
Stream source provides without other branches or extracts electric current, therefore can be automatically adjusted to top tail current source after feedback loop stable
It is suitable with base current source numerical value；In addition, the partial pressure of first resistor R1 and second resistance R2 can control common-mode voltage Vcom, usually
It is by VcomThe position (or slightly biased under) of AVdd/2 is set, i.e., R1=R2 is set in embodiments of the present invention.
As shown in figure 9, above-mentioned output common mode clamp circuit includes: 3rd resistor R3, the 4th resistance R4, capacitor C and first
Operational amplifier OP1, in which:
The resistance value of above-mentioned 3rd resistor R3 and above-mentioned 4th resistance R4 are equal；The reverse phase of above-mentioned first operational amplifier OP1
First end of the input terminal as above-mentioned output common mode clamp circuit M1, inputs above-mentioned common-mode voltage Vcom；Above-mentioned first operation amplifier
The normal phase input end of device OP1 is connected with one end of above-mentioned capacitor C, the other end ground connection of above-mentioned capacitor C.
One end of above-mentioned capacitor C is connected with one end of one end of above-mentioned 3rd resistor R3 and the 4th resistance R4 respectively, above-mentioned
The other end of 3rd resistor R3 is connected as the 4th end of above-mentioned output common mode clamp circuit M1 with above-mentioned Out_N；Above-mentioned 4th
The other end of resistance R3 is connected as the third end of above-mentioned output common mode clamp circuit M1 with above-mentioned Out_P；Above-mentioned first operation
The output end of amplifier OP1 exports above-mentioned first bias voltage V as the second end of above-mentioned output common mode clamp circuit M1bpWith it is upper
The control terminal for stating third PMOS tube P3 is connected.
It should be noted that above-mentioned first PMOS tube P1, above-mentioned second PMOS tube P2 and above-mentioned third PMOS tube P3
First end is source electrode, second end is drain electrode, third end is grid.Above-mentioned first NMOS tube N1, above-mentioned second NMOS tube N2 and
The first end of above-mentioned third NMOS tube N3 is drain electrode, second end is source electrode, third end is grid.
In fig. 8, above-mentioned first PMOS tube P1, above-mentioned second PMOS tube P2, above-mentioned first NMOS tube N1 and above-mentioned
Two NMOS tube N2 are switch, and above-mentioned third PMOS tube P3 and above-mentioned third NMOS tube N3 are current source, in which: above-mentioned 3rd PMOS
Pipe P3 is top tail current source；Above-mentioned third NMOS tube N3 is bottom tail current source.Terminating resistor RAUsing complete cross-over mode,
And RA=2*Rterm, termination voltage is not provided.
3rd resistor R3 and the 4th resistance R4 is the big resistance at least more than 50k ohm, it is therefore an objective to be reduced to terminating resistor
RAIn parallel influence.Work as VcomWhen for AVdd/2, if output common mode voltage is greater than Vcom, then VbpRise, controls third PMOS tube P3
Electric current reduce, force down output common mode voltage；Vice versa, it may be assumed that
First, when AC mode, bottom tail current source N3 is configured to I/2, and output common mode clamp circuit M1 passes through above-mentioned negative
Feedback holds output common mode voltage in AVdd/2, can essentially form Fig. 5 the double tail current source working forms of equivalence (Fig. 5's
TX does not need termination voltage)；
When second, DC mode, the pull-up ability of RX termination can draw common-mode voltage to (AVdd-I*R near AVddterm/
2), it is much higher than AVdd/2, the meeting negative-feedback of output common mode clamp circuit reduces top tail current source P3 until thoroughly closing.At this point,
First PMOS tube P1, the second PMOS tube P2 and third PMOS tube P3 failure, circuit are automatically regulated to be the bridging list tail electricity such as Fig. 7
Stream source operating mode.
It further, as shown in Figure 10, is another kind CML structure output driving stage circuit provided in an embodiment of the present invention,
On the basis of Fig. 8, the circuit further include: swing-scanning control device M2, above-mentioned swing-scanning control device M2 include: first end, second end and
Third end, in which:
The first end of above-mentioned swing-scanning control device M2 is connected with the second end of above-mentioned output common mode clamp circuit M1, receives above-mentioned
First bias voltage Vbp, the second end reception target amplitude of oscillation voltage V of above-mentioned swing-scanning control device M2mbf, above-mentioned swing-scanning control device M2's
The above-mentioned second bias voltage V of three-polar outputbnIt is connected with the control terminal of above-mentioned third NMOS tube N3；
Above-mentioned swing-scanning control device M2 is used to adjust above-mentioned V according to AC/DC connection typebn。
Further, as shown in figure 11, above-mentioned swing-scanning control device M2 includes: the 4th PMOS tube P4, the 5th PMOS tube P5,
Six PMOS tube P6, the 4th NMOS tube N4, second operational amplifier OP2 and amplitude of oscillation resistance RB, in which:
The first end of above-mentioned 4th PMOS tube P4, the first end of above-mentioned 5th PMOS tube P5 and above-mentioned 6th PMOS tube P6
First end is connected with above-mentioned supply voltage AVdd；The control terminal of above-mentioned 4th PMOS tube P4 as above-mentioned swing-scanning control device M2
The second end of the above-mentioned output common mode clamp circuit M1 in one end is connected, and receives above-mentioned first bias voltage Vbp；Above-mentioned 4th PMOS tube
The second end of P4 is connected with the second end of above-mentioned 5th PMOS tube P5, common end respectively with above-mentioned amplitude of oscillation resistance RBOne end and
The reverse input end of above-mentioned second operational amplifier OP2 is connected.
Above-mentioned amplitude of oscillation resistance RBThe other end be connected with the second end of above-mentioned 4th NMOS tube N4, and be grounded；Above-mentioned 4th
The first end of NMOS tube N4 is connected with the second end of above-mentioned 6th PMOS tube P6 and control terminal；The control of above-mentioned 5th PMOS tube P5
End is connected with the control terminal of above-mentioned 6th PMOS tube P6；The control terminal of above-mentioned 4th NMOS tube N4 is put with above-mentioned second operation
The output end of big device OP2 is connected, three-polar output above-mentioned second bias voltage of the common end as above-mentioned swing-scanning control device M2
Vbn；The positive input of above-mentioned second operational amplifier OP2 receives target as the second end of above-mentioned swing-scanning control device M2
Amplitude of oscillation voltage Vmbf。
It should be noted that above-mentioned 4th PMOS tube P4, above-mentioned 5th PMOS tube P5 and above-mentioned 6th PMOS tube P6
First end is source electrode, second end is drain electrode, third end is grid.The first end of above-mentioned 4th NMOS tube N4 is drain electrode, second end
It is grid for source electrode, third end.
Specifically, as shown in figure 11, the amplitude of oscillation of reality output is by the electric current of third PMOS tube P3 and third NMOS tube N3
What the sum of value determined.When DC mode, IN3=I, IP3=0；When AC mode, IN3=IP3=I/2.The sum of the two current value is identical, pendulum
Width is also identical, therefore it may only be necessary to a control circuit, it is ensured that sum of the two is consistently equal to target current I, then may make system certainly
It is dynamic to adjust AC/DC different mode lower bottom part tail current source P3, specifically, the controller circuitry implementation of above-mentioned function can be reached
Very much, as shown in figure 11, it is to enumerate one embodiment:
Wherein, the 4th PMOS tube P4 and the 4th NMOS tube N4 is third PMOS tube P3 and third NMOS tube N3 in Figure 10 respectively
1/n times of breadth length ratio, the current mirror that the 5th PMOS tube P5 and the 6th PMOS tube P6 are 1:1.The normal phase input end (+) of amplifier is defeated
Enter target amplitude of oscillation voltage, such as 400mV, and flows through amplitude of oscillation resistance RB=n*Rterm/ 2 electric current is the 1/n of the sum of double tail currents
Times, generating practical amplitude of oscillation voltage is (IN3+IP3)*Rterm/ 2, input amplifier negative-phase input (-) is compared, and exports result control
Current value under bottom tail current source N3 adjust automatically AC/DC mode processed.
In the basic procedure of script, when AC/DC pattern switching, above-mentioned first PMOS tube P1, above-mentioned second PMOS tube P2
It can be automatically closed with above-mentioned third PMOS tube P3, it is only necessary to which active arrangement bottom tail current needs to increase or reduce one times.It is no
Then under different mode, the amplitude of oscillation can be inconsistent.For this " uniquely needing to configure " parameter addition controller benefit be, entirely
System can become completely adaptive mode.Certainly, if without using this optimization, still taproot circuit still can be with
Work.Only parameter configuration is carried out according to DC/AC mode.
Double tail current source CML provided in an embodiment of the present invention use output common mode clamper simultaneously using bridging resistance
Circuit control bridges resistance output common mode voltage, and can combine AC/DC mode can optimize the TX of power consumption；In circuit reality
In existing, one " fixation " bottom tail current source N3 used and top tail that one uses output common mode clamp circuit to control is electric
Stream source P3 makes the bridging resistance stabilization of the CML under AC mode in reasonable operating voltage, it is no longer necessary to provide termination voltage；Separately
Outside, it can also realize automatically to AC/DC mode tuning, be an adaptive TX in itself.
It should be noted that, in this document, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion so that article or equipment including a series of elements not only include those elements, but also is wrapped
Other elements that are not explicitly listed are included, or further include for this article or the intrinsic element of equipment.Do not having more
In the case where more limitations, the element that is limited by sentence "including a ...", it is not excluded that include above-mentioned element article or
There is also other identical elements in person's equipment.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (8)
1. a kind of CML structure output driving stage circuit characterized by comprising first resistor (R1), second resistance (R2), defeated
Common mode clamp circuit (M1), the first PMOS tube (P1), the second PMOS tube (P2), third PMOS tube (P3), the first NMOS tube out
(N1), the second NMOS tube (N2), third NMOS tube (N3) and terminating resistor (RA), in which:
One end of the first resistor (R1) and the first end of the third PMOS tube (P3) are connected with supply voltage AVdd；It is described
The other end of first resistor (R1) is connected with one end of the second resistance (R2), another termination of the second resistance (R2)
Ground；
The of the common end of the first resistor (R1) and the second resistance (R2) and the output common mode clamp circuit (M1)
One end is connected, and the second end of the output common mode clamp circuit (M1) is connected with the control terminal of the third PMOS tube (P3), institute
The third end for stating output common mode clamp circuit (M1) is connected with the second end of first PMOS tube (P1), and is connected with Out_N；
4th end of the output common mode clamp circuit (M1) is connected with the second end of second PMOS tube (P2), and with Out_P phase
Even；
The second end of the third PMOS tube (P3) respectively with the first end of first PMOS tube (P1) and the 2nd PMOS
The first end for managing (P2) is connected, and the control terminal of first PMOS tube (P1) is connected with In_P, second PMOS tube (P2)
Control terminal is connected with In_N；
The second end of first PMOS tube (P1) is connected with the first end of first NMOS tube (N1), second PMOS tube
(P2) second end is connected with the first end of second NMOS tube (N2), the control terminal of first NMOS tube (N1) with it is described
In_P is connected, and the control terminal of second NMOS tube (N2) is connected with the In_N；
The second end of first NMOS tube (N1) is connected with the second end of second NMOS tube (N2), common end with it is described
The first end of third NMOS tube (N3) is connected, the second end ground connection of the third NMOS tube (N3), the third NMOS tube (N3)
Control terminal input the second bias voltage Vbn；
The second end of first PMOS tube (P1) and the second end of second PMOS tube (P2) pass through the terminating resistor (RA)
It is connected；
The second end of first PMOS tube (P1) is connected with the Out_N, the second end of second PMOS tube (P2) and institute
Out_P is stated to be connected；
The third NMOS tube (N3) configures second bias voltage according to AC/DC connection type as bottom tail current source
Vbn；The third PMOS tube (P3) is used as top tail current source to do biasing by the output common mode clamp circuit and is controlled, institute
It states output common mode clamp circuit and forms feedback control loop, by comparing common-mode voltage VcomWith the practical common mode electrical level of output voltage, obtain
First bias voltage V outbp, by the first bias voltage VbpThe third PMOS tube (P3) is fed back to, by the reality output
Common mode electrical level is adjusted to the common-mode voltage Vcom。
2. circuit according to claim 1, which is characterized in that the output common mode clamp circuit includes: 3rd resistor
(R3), the 4th resistance (R4), capacitor (C) and the first operational amplifier (OP1), in which:
The resistance value of the 3rd resistor (R3) and the 4th resistance (R4) is equal；
First end of the inverting input terminal of first operational amplifier (OP1) as the output common mode clamp circuit (M1),
Input the common-mode voltage Vcom；One end phase of the normal phase input end and the capacitor (C) of first operational amplifier (OP1)
Even, the other end ground connection of the capacitor (C)；
One end of the capacitor (C) is connected with one end of one end of the 3rd resistor (R3) and the 4th resistance (R4) respectively, institute
The other end for stating 3rd resistor (R3) is connected as the 4th end of the output common mode clamp circuit (M1) with the Out_N；Institute
The other end for stating the 4th resistance (R3) is connected as the third end of the output common mode clamp circuit (M1) with the Out_P；
The output end of first operational amplifier (OP1) exports institute as the second end of the output common mode clamp circuit (M1)
State the first bias voltage VbpIt is connected with the control terminal of the third PMOS tube (P3).
3. circuit according to claim 1, which is characterized in that first PMOS tube (P1), second PMOS tube
(P2) and the first end of the third PMOS tube (P3) is source electrode, second end is drain electrode, third end is grid.
4. circuit according to claim 1, which is characterized in that first NMOS tube (N1), second NMOS tube
(N2) and the first end of the third NMOS tube (N3) is drain electrode, second end is source electrode, third end is grid.
5. circuit according to claim 1 or 2, which is characterized in that further include: swing-scanning control device (M2), the amplitude of oscillation control
Device (M2) processed includes: first end, second end and third end, in which:
The first end of the swing-scanning control device (M2) is connected with the second end of the output common mode clamp circuit (M1), described in reception
First bias voltage Vbp, the second end reception target amplitude of oscillation voltage V of the swing-scanning control device (M2)mbf, the swing-scanning control device
(M2) the second bias voltage V described in three-polar outputbnIt is connected with the control terminal of the third NMOS tube (N3)；
The swing-scanning control device (M2) is used to adjust the V according to AC/DC connection typebn。
6. circuit according to claim 5, which is characterized in that the swing-scanning control device (M2) includes: the 4th PMOS tube
(P4), the 5th PMOS tube (P5), the 6th PMOS tube (P6), the 4th NMOS tube (N4), second operational amplifier (OP2) and the amplitude of oscillation
Resistance (RB), in which:
The first end of 4th PMOS tube (P4), the first end of the 5th PMOS tube (P5) and the 6th PMOS tube (P6)
First end be connected with the supply voltage AVdd；
Output common mode clamper described in first end of the control terminal of 4th PMOS tube (P4) as the swing-scanning control device (M2)
The second end of circuit (M1) is connected, and receives the first bias voltage Vbp；The second end of 4th PMOS tube (P4) and described
The second end of 5th PMOS tube (P5) is connected, common end respectively with the amplitude of oscillation resistance (RB) one end and second operation
The reverse input end of amplifier (OP2) is connected；
Amplitude of oscillation resistance (the RB) the other end be connected with the second end of the 4th NMOS tube (N4), and be grounded；Described 4th
The first end of NMOS tube (N4) is connected with the second end of the 6th PMOS tube (P6) and control terminal；5th PMOS tube (P5)
Control terminal be connected with the control terminal of the 6th PMOS tube (P6)；
The control terminal of 4th NMOS tube (N4) is connected with the output end of the second operational amplifier (OP2), public
Second bias voltage V described in three-polar output of the end as the swing-scanning control device (M2) altogetherbn；
The positive input of the second operational amplifier (OP2) is received as the second end of the swing-scanning control device (M2)
Target amplitude of oscillation voltage Vmbf。
7. circuit according to claim 6, which is characterized in that the 4th PMOS tube (P4), the 5th PMOS tube
(P5) and the first end of the 6th PMOS tube (P6) is source electrode, second end is drain electrode, third end is grid.
8. circuit according to claim 6, which is characterized in that the first end of the 4th NMOS tube (N4) is drain electrode, the
Two ends are source electrode, third end is grid.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811009953.9A CN109067388B (en) | 2018-08-31 | 2018-08-31 | CML structure output drive stage circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811009953.9A CN109067388B (en) | 2018-08-31 | 2018-08-31 | CML structure output drive stage circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6340909B1 (en) * | 1998-01-30 | 2002-01-22 | Rambus Inc. | Method and apparatus for phase interpolation |
| CN101171537A (en) * | 2005-03-09 | 2008-04-30 | 菲尼萨公司 | Interconnect mechanism for connecting a laser driver to a laser |
| US20120162189A1 (en) * | 2009-09-18 | 2012-06-28 | Panasonic Corporation | Driver circuit and video system |
| EP2590320A2 (en) * | 2011-11-01 | 2013-05-08 | NeoEnergy Microelectronic, Inc. | Switching system and method for control thereof |
| US20150188537A1 (en) * | 2013-12-27 | 2015-07-02 | Canon Kabushiki Kaisha | Differential signal driving circuit |
| CN204481788U (en) * | 2015-04-07 | 2015-07-15 | 电子科技大学 | A kind of LVDS drive circuit suppressing output common mode to fluctuate |
-
2018
- 2018-08-31 CN CN201811009953.9A patent/CN109067388B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6340909B1 (en) * | 1998-01-30 | 2002-01-22 | Rambus Inc. | Method and apparatus for phase interpolation |
| CN101171537A (en) * | 2005-03-09 | 2008-04-30 | 菲尼萨公司 | Interconnect mechanism for connecting a laser driver to a laser |
| US20120162189A1 (en) * | 2009-09-18 | 2012-06-28 | Panasonic Corporation | Driver circuit and video system |
| EP2590320A2 (en) * | 2011-11-01 | 2013-05-08 | NeoEnergy Microelectronic, Inc. | Switching system and method for control thereof |
| US20150188537A1 (en) * | 2013-12-27 | 2015-07-02 | Canon Kabushiki Kaisha | Differential signal driving circuit |
| CN204481788U (en) * | 2015-04-07 | 2015-07-15 | 电子科技大学 | A kind of LVDS drive circuit suppressing output common mode to fluctuate |
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| Publication number | Publication date |
|---|---|
| CN109067388B (en) | 2022-05-24 |
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