CN109065562B - Backside illuminated CMOS image sensor and manufacturing method thereof - Google Patents

Backside illuminated CMOS image sensor and manufacturing method thereof Download PDF

Info

Publication number
CN109065562B
CN109065562B CN201811095233.9A CN201811095233A CN109065562B CN 109065562 B CN109065562 B CN 109065562B CN 201811095233 A CN201811095233 A CN 201811095233A CN 109065562 B CN109065562 B CN 109065562B
Authority
CN
China
Prior art keywords
layer
opening
substrate
pad
image sensor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201811095233.9A
Other languages
Chinese (zh)
Other versions
CN109065562A (en
Inventor
邢家明
叶菁
高喜峰
施喆天
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omnivision Technologies Shanghai Co Ltd
Original Assignee
Omnivision Technologies Shanghai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omnivision Technologies Shanghai Co Ltd filed Critical Omnivision Technologies Shanghai Co Ltd
Priority to CN201811095233.9A priority Critical patent/CN109065562B/en
Publication of CN109065562A publication Critical patent/CN109065562A/en
Application granted granted Critical
Publication of CN109065562B publication Critical patent/CN109065562B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1464—Back illuminated imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14621—Colour filter arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14645—Colour imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

The invention provides a back-illuminated CMOS image sensor and a manufacturing method thereof. The back-illuminated CMOS image sensor includes: the substrate, the dielectric layer, the connecting line layer embedded in the dielectric layer, a step-shaped opening which is located in the substrate and the dielectric layer and exposes the connecting line layer, an isolation layer which covers the surface of the step-shaped opening and extends to cover the back of the substrate, a welding pad layer which is located in the step-shaped opening and is electrically connected with the connecting line layer, a grid part and a color filter layer. The welding pad layer is positioned in the step-shaped hole, and the absolute value of the height difference between the top surface of the welding pad layer and the top surface of the isolation layer on the back surface of the substrate is smaller than a preset value, so that when the color filter layer is formed through a rotary coating process, the whole surface to be coated with the raw material of the color filter layer is smooth, the welding pad layer cannot prevent the raw material of the color filter layer from being thrown away, the formed color filter layer is uniform, stripes can be avoided, and the image quality of the back-illuminated CMOS image sensor is improved.

Description

Backside illuminated CMOS image sensor and manufacturing method thereof
Technical Field
The invention belongs to the field of image sensors, and particularly relates to a back-illuminated CMOS image sensor and a manufacturing method thereof.
Background
In the back-illuminated CMOS image sensor, the interlayer dielectric layer and the metal wiring layer which are arranged between the filter layer and the pixel unit are moved to the other side of the pixel unit, and light rays are directly emitted to the photodiode without being blocked by the metal wiring layer, so that compared with a front-illuminated CMOS image sensor, the back-illuminated CMOS image sensor has the advantages that light energy which can be obtained by a single pixel unit is larger, the picture quality is obviously improved, and the back-illuminated CMOS image sensor is widely applied.
In a back-illuminated CMOS image sensor, the structure of the pad layer is usually implemented in two ways: one is the way that the pad layer is convexly distributed on a part of the substrate, and the other is the way that the pad layer is distributed at the bottom of the substrate groove. However, in practice, the color filter layer of the conventional back-illuminated CMOS image sensor is not uniform and is in a stripe shape, which affects the image quality.
Disclosure of Invention
The invention aims to solve the problem of non-uniform color filter layers of a back-illuminated CMOS image sensor and improve the imaging quality.
In order to achieve the above object, the present invention provides a back-illuminated CMOS image sensor including:
a substrate having oppositely disposed front and back surfaces,
a dielectric layer on the front side of the substrate;
the connecting wire layer is embedded in the dielectric layer;
the stepped opening is positioned in the substrate and the dielectric layer and above the connecting line layer, and the stepped opening exposes a partial area of the connecting line layer;
the isolation layer covers the surface of the step-shaped opening, exposes the connecting line layer and extends to cover a partial area of the back surface of the substrate;
the welding pad layer is positioned in the step-shaped opening and covers part of the isolation layer and is electrically connected with the connecting line layer; the absolute value of the height difference between the top surface of the pad layer and the top surface of the isolation layer on the back surface of the substrate is less than a preset value;
a grid portion on a back surface of the substrate; and
and a color filter layer positioned in the cells of the cell part.
Further, the stepped bore includes:
a first opening through a portion of the thickness of the substrate;
the second opening penetrates through the substrate at the bottom of the first opening and the dielectric layer with partial thickness, and the section width of the second opening is smaller than that of the first opening; and
and the third opening penetrates through the dielectric layer at the bottom of the second opening and exposes the connecting line layer, and the section width of the third opening is smaller than that of the second opening.
Further, the isolation layer comprises a high-dielectric-constant dielectric layer and a buffer layer formed on the high-dielectric-constant dielectric layer.
Further, the preset value is 1000 angstroms.
Further, the backside-illuminated CMOS image sensor further comprises a grounding opening, wherein the grounding opening penetrates through a part of the isolation layer and a part of the thickness of the substrate on the backside of the substrate.
Further, a gap is formed between the pad layer and the first opening, the back-illuminated CMOS image sensor further includes a first shielding portion and a second shielding portion, the first shielding portion covers a surface of the gap and extends to cover a partial region of the pad and a partial region of the back surface of the substrate; the second shielding part fills the grounding open hole and covers a part of the back surface of the substrate, and the second shielding part, the first shielding part and the grid part are distributed at intervals.
The invention also provides a manufacturing method of the back-illuminated CMOS image sensor, which comprises the following steps:
providing a substrate, wherein the substrate is provided with a front surface and a back surface which are oppositely arranged, a dielectric layer is formed on the front surface of the substrate, and a connecting line layer is embedded in the dielectric layer;
forming a step-shaped opening, wherein the step-shaped opening is positioned in the substrate and the dielectric layer and above the connecting line layer, and the step-shaped opening exposes a partial area of the connecting line layer;
forming an isolation layer, wherein the isolation layer covers the surface of the step-shaped opening, exposes the connecting line layer and extends to cover the back surface of the substrate;
forming a bonding pad layer, wherein the bonding pad layer is positioned in the step-shaped opening and covers part of the isolation layer and is electrically connected with the connecting line layer; the absolute value of the height difference between the top surface of the pad layer and the top surface of the isolation layer on the back surface of the substrate is less than a preset value;
forming a grid portion on a back surface of the substrate; and
forming a color filter layer located in the cells of the cell part by a spin coating process.
Further, the step of forming the step-shaped opening and the isolation layer includes:
etching the substrate with partial thickness to form a first opening;
etching the substrate at the bottom of the first opening and the dielectric layer with partial thickness to form a second opening, wherein the section width of the second opening is smaller than that of the first opening;
forming an isolation layer covering the surfaces of the first and second openings and covering the back surface of the substrate;
etching part of the isolation layer at the bottom of the second opening and the dielectric layer with partial thickness below the isolation layer to form a third opening, wherein the third opening exposes the connecting line layer, and the section width of the third opening is smaller than that of the second opening;
wherein the first opening, the second opening and the third opening form the stepped opening,
the isolation layer is partially consumed when the third opening is formed.
Further, the step of forming the pad layer includes:
forming a pad raw material layer, wherein the pad raw material layer is formed in the stepped opening and extends to cover the isolation layer on the back surface of the substrate, and the absolute value of the height difference between the top surface of the pad raw material layer formed in the stepped opening and the top surface of the isolation layer on the back surface of the substrate is controlled to be smaller than a preset value; the welding pad raw material layer is electrically connected with the connecting line layer; and
and etching to remove the weld pad raw material layer on the back surface of the substrate, etching to remove the weld pad raw material layer near the inner wall of the first opening, forming a gap between the weld pad layer and the first opening, and forming the weld pad layer by the residual weld pad raw material layer.
Further, after forming the pad layer and before forming the grid portion, the method further includes:
and etching and removing the isolation layer of the partial area on the back surface of the substrate and the substrate with partial thickness below the isolation layer to form a grounding opening.
Compared with the prior art, in the backside illuminated CMOS image sensor provided by the invention, the welding pad layer is positioned in the step-shaped opening, and the absolute value of the height difference between the top surface of the welding pad layer and the top surface of the isolation layer on the back surface of the substrate is smaller than the preset value, so that when the color filter layer is formed by a rotary coating process, the whole surface to be coated with the raw material of the color filter layer is relatively flat, the welding pad layer cannot prevent the raw material of the color filter layer from being thrown out, the formed color filter layer is relatively uniform, stripes can be avoided, and the image quality of the backside illuminated CMOS image sensor is improved.
Drawings
FIG. 1 is a schematic cross-sectional view of a pad layer of a backside illuminated CMOS image sensor protruding over a substrate;
FIG. 2 is a cross-sectional view of another bond pad layer of a backside illuminated CMOS image sensor at the bottom of a substrate trench;
FIG. 3 is a flow chart of a method for fabricating a backside illuminated CMOS image sensor according to an embodiment of the present invention;
FIG. 4 is a top view of a backside illuminated CMOS image sensor in accordance with an embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view of the AA' region after the first opening is formed in the method of forming an embodiment of the invention;
FIG. 6 is a schematic cross-sectional view of the AA' region after the second opening is formed in the method of forming an embodiment of the invention;
FIG. 7 is a schematic cross-sectional view of the AA' region after forming the isolation layer in the method of manufacturing the embodiment of the invention;
FIG. 8 is a schematic cross-sectional view of the portion AA' after the third opening is formed in the method of forming an embodiment of the present invention;
FIG. 9 is a schematic cross-sectional view of the portion AA' after forming the pad layer in the method of forming an embodiment of the invention;
FIG. 10 is a schematic cross-sectional view of the AA' region after forming a grounding opening in the method of forming an embodiment of the present invention;
fig. 11 is a schematic cross-sectional view of the grid part formed at AA' in the manufacturing method according to the embodiment of the invention.
Wherein the reference numbers are as follows:
11-a substrate; 11 a-the front side of the substrate; 11 b-the back side of the substrate; 12-a dielectric layer; 13-a wiring layer; 14-an insulating layer; 15-a pad layer;
21-a substrate; 21 a-the front side of the substrate; 21 b-the back side of the substrate; 22-a dielectric layer; 23-a wiring layer; 24-a pad layer; 25-a passivation layer;
31-a substrate; 31 a-the front side of the substrate; 31 b-the back side of the substrate; 32-a dielectric layer;
33-a wiring layer; 34-an isolation layer; 34 a-a high dielectric constant dielectric layer; 34 b-a buffer layer;
35-a pad layer; 36-gap; 37 a-a grid portion; 37 b-a first shade; 37 c-a second shade; 38-ground opening;
41-a first opening; 42-a second opening; 43-third opening.
Detailed Description
In the background art, it has been mentioned that the protruding distribution of the pad layer on a portion of the substrate is likely to cause the color filter layer formed subsequently to be non-uniform and stripe-shaped, which may affect the image quality.
Fig. 1 is a schematic cross-sectional view of a pad layer of a back-illuminated CMOS image sensor protruding over a substrate. As shown in fig. 1, the substrate 11 has a front surface 11a and a back surface 11b which are oppositely arranged, a dielectric layer 12 is formed on the front surface 11a of the substrate 11, a wiring layer 13 is embedded in the dielectric layer 12, an insulating layer 14 is formed on the back surface 11b of the substrate 11, an opening (not numbered) penetrates through the substrate 11 and a part of the thickness of the dielectric layer 12, and a pad layer 15 is electrically connected with the wiring layer 13 through the opening. To ensure a structurally sound bond pad layer 15, the bond pad layer 15 must not be too thin, typically at least 5000 angstroms thick. In addition, in the process after forming the pad layer, a color filter layer (not shown) is formed on the back surface 11b of the substrate by using a spin coating process, which is a conventional process of uniformly spin coating a raw material on a plane, but since the pad layer protrudes from the substrate to have a certain thickness and is higher than the color filter layer to be formed, when the raw material of the color filter layer is coated in the grid on the substrate, the raw material of the surrounding color filter layer is blocked by the pad layer having a certain thickness and cannot be thrown off normally, so that the thickness of the raw material of the color filter layer formed by spin coating is not uniform (for example, in a stripe shape), and the finally formed color filter layer is also not uniform (for example, in a stripe shape), thereby affecting the image quality.
Fig. 2 is a cross-sectional view of another pad layer of a backside illuminated CMOS image sensor at the bottom of a substrate trench. As shown in fig. 2, the substrate 21 has a front surface 21a and a back surface 21b which are oppositely arranged, a dielectric layer 22 is formed on the front surface 21a of the substrate, a wiring layer 23 is embedded in the dielectric layer 22, a trench 26 penetrates through the substrate 21 and a part of the thickness of the dielectric layer 22, a pad layer 24 is located at the bottom of the trench 26 and electrically connected with the wiring layer 23, a passivation layer 25 fills the trench 26 and covers the back surface 21b of the substrate 21, and an opening 27 exposing the pad layer 24 is formed in the passivation layer 25. However, when a color filter layer is formed on the back surface 21b of the substrate by the spin-on process, the raw material of the color filter layer may enter the openings 27 to affect the uniformity of the formed color filter layer. In order to solve the problem of stripe-shaped color filter layer, the inventor has tried to fill the opening 27 with a filling layer and cover the surface of the passivation layer 25 before forming the color filter layer, then use a chemical mechanical polishing process to flatten the surface of the filling layer, and after forming the color filter layer, form a through hole penetrating the filling layer and exposing the pad layer by photolithography and etching processes.
Based on this, the inventor has provided a backside illumination formula CMOS image sensor, and the solder pad layer is arranged in the echelonment trompil, and the absolute value of the difference in height between the top surface of the solder pad layer and the top surface of the isolation layer on the back of the substrate is less than the default, therefore, when forming the color filter layer through the spin coating technology, the whole surface that will coat the color filter layer raw materials is comparatively level and smooth, and the solder pad layer can not block the color filter layer raw materials and throw away, and the color filter layer that forms from this is comparatively even, can avoid appearing the stripe, has promoted backside illumination formula CMOS image sensor's image quality.
The invention is described in further detail below with reference to the figures and specific examples. The advantages and features of the present invention will become more apparent from the following description. It is to be noted, however, that the drawings are designed in a simplified form and are not to scale, but rather are to be construed in an illustrative and descriptive sense only and not for purposes of limitation.
Fig. 4 is a top view of a backside illuminated CMOS image sensor according to an embodiment of the present invention, as shown in fig. 4, the backside illuminated CMOS image sensor 30 includes a photosensitive area 30a, a light-shielding area 30b, and a pad layer area 30c, the photosensitive area 30a is located in a central area of the backside illuminated CMOS image sensor 30, a grid portion is distributed in the photosensitive area, the grid portion includes a plurality of grids in a grid shape, and color filter layer units are formed in the grids; the light-shielding regions 30b are, for example, annularly distributed around the photosensitive region 30a, the pad layer regions 30c are, for example, distributed on two opposite sides of the light-shielding regions 30b, and the pad layer regions 30c are distributed with a plurality of pad layers 35 distributed in an array.
Fig. 11 is a schematic cross-sectional view of the back-illuminated CMOS image sensor according to the embodiment of the present invention taken along the line AA' of fig. 4, the back-illuminated CMOS image sensor according to the embodiment of the present invention includes:
a substrate 31 having a front surface 31a and a back surface 31b disposed opposite to each other,
a dielectric layer 32 on the front surface 31a of the substrate 31;
a wiring layer 33 embedded in the dielectric layer 32;
a step-shaped opening which is positioned in the substrate 31 and the dielectric layer 32 and is positioned above the connecting line layer 33, wherein the step-shaped opening exposes a partial area of the connecting line layer 33;
an isolation layer 34 covering the surface of the step-shaped opening and exposing the wiring layer 33; optionally, the isolation layer 34 extends to cover a partial region of the back surface 31b of the substrate;
a pad layer 35 located in the step-shaped opening and covering a part of the isolation layer 34, the pad layer 35 being electrically connected to the wiring layer 33, an absolute value of a height difference between a top surface of the pad layer 35 and a top surface of the isolation layer 34 on the back surface 31b of the substrate being smaller than a preset value;
a grid part 37a, the grid part 37a being located on the back surface of the substrate; and
and a color filter layer located between the grids of the grid part 37 a.
As shown in connection with fig. 11, the substrate 31 in the present embodiment is inverted, that is, the front surface 31a of the substrate faces downward, and incident light enters from the direction of the back surface 31b of the substrate. A dielectric layer 32 is formed on the front surface 31a of the substrate, and a wiring layer 33 is embedded in the dielectric layer 32, the wiring layer 33 providing interconnections between the various doped components, circuits and input/output of the back-illuminated CMOS image sensor. The wiring layer 33 may be in the form of a plurality of conductive lines interconnected by plugs formed in a dielectric layer. It should be understood that wiring level 33 is only schematically shown in the figures, and the actual positioning and configuration of wiring level 33 may vary depending on design requirements. The wiring layer 33 is made of a conductive material, such as any one of aluminum, an aluminum alloy, titanium nitride, tungsten, polysilicon, a metal silicide, or a combination of two or more thereof, and may be formed by a process including any one of Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or a combination of two or more thereof. Alternatively, the conductive material is, for example, copper or a copper alloy, and may be formed by techniques including CVD, sputtering, electroplating, or other suitable processes.
As shown in fig. 8 and 11, the step-shaped opening is located in the substrate 31 and the dielectric layer 32 and above the wiring layer 33, the step-shaped opening exposes a partial region of the wiring layer 33, the step-shaped opening is intended to sink the pad layer 35 in the hole, so that the height of the pad layer 35 is reduced, and in a subsequent raw material process for forming a color filter layer by spin coating, the surrounding raw materials are not blocked by the protruding pad layer in the prior art when being thrown away, thereby avoiding non-uniformity of the color filter layer.
In detail, the stepped hole includes, from top to bottom:
a first opening 41 through a portion of the thickness of the substrate 31; as an alternative embodiment, the shape of a section (i.e., a cross section) of the first opening 41 parallel to the surface of the back-illuminated CMOS image sensor may be rectangular, and the shape of a section (i.e., a longitudinal section) perpendicular to the surface of the back-illuminated CMOS image sensor may be inverted trapezoidal or rectangular;
a second opening 42 penetrating through the substrate 31 at the bottom of the first opening 41 and the dielectric layer 32 with a partial thickness, wherein the cross-sectional width of the second opening 42 is smaller than that of the first opening 41; and
a third opening 43 penetrating through the dielectric layer 32 at the bottom of the second opening 42 and exposing the wiring layer 33, wherein the cross-sectional width of the third opening 43 is smaller than that of the second opening 42;
the first opening 41, the second opening 42, and the third opening 43 are communicated with each other, and are combined to form the stepped opening.
Alternatively, the first opening 42 may extend through a portion of the thickness of the substrate 31, suitable when the substrate 31 is relatively thick (e.g., greater than 3 μm); the first opening 41 may also extend through the entire substrate 31, which is suitable when the substrate 31 is thin; the depth of the first opening 41 through the substrate 31 may vary according to design requirements.
Alternatively, the cross-sectional width of the third opening 43 may be equal to the cross-sectional width of the second opening 42, so that a mask for forming the third opening 43 may be saved.
As shown in fig. 8 and 11, the isolation layer 34 covers the surfaces of the first opening 41 and the second opening 42, and the pad layer 35 covers part of the isolation layer 34 at the bottom of the first opening 41.
Preferably, the isolation layer 34 includes a high-k dielectric layer 34a and a buffer layer 34b formed on the high-k dielectric layer 34 a. The high-k dielectric layer 34a covers the surfaces of the first opening 41 and the second opening 42, and also covers the back surface 31b of the substrate. The high-k dielectric layer 34a has negative charges, light enters the substrate 31 from the backside of the substrate, electrons are generated by the photo sensitive element (e.g., photodiode) in the substrate 31, and the negative charges on the high-k dielectric layer 34a repel the electrons generated by the photo sensitive element (e.g., photodiode), so that the electrons move in a direction away from the high-k dielectric layer 34a (i.e., away from the backside 31b of the substrate), thereby preventing the electrons from moving to the backside 31b of the substrate, and further suppressing noise and dark current.
Specifically, the material of the high-k dielectric layer 34a may be aluminum oxide (Al203), hafnium oxide (Hf02), lead oxynitride (HfON), lead silicate (HfSiO), hafnium silicon oxynitride (HfSiON), zirconium oxide (Zr02), zirconium oxynitride (Zr ON), zirconium silicate (ZrSiO), zirconium silicon oxynitride (ZrSiON), hafnium zirconium oxide (HfZr02), hafnium zirconium oxynitride (HfZrON), hafnium zirconium silicate (HfZrSiO), hafnium zirconium oxynitride (HfZrSiON), titanium oxide (Ti02), lanthanum oxide (La203), or the like, or a combination of two or more thereof. The buffer layer 34b covers the high-k dielectric layer 34a on the surfaces of the first opening 41 and the second opening 42, and also extends to cover the high-k dielectric layer on the back surface 31b of the substrate around the first opening 41. The material of the buffer layer 34b may be silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination of two or more thereof. The spacer layer 34 plays a good role of isolation between the pad layer 35 and the substrate 31.
The pad layer 35 is located in the step-shaped opening and electrically connected to the wiring layer 33, and an absolute value of a height difference between the top surface of the pad layer 35 and the top surface of the isolation layer 34 on the back surface 31b of the substrate is smaller than a preset value; preferably, the preset value is, for example, 1000 angstroms. Preferably, the material of the pad layer is, for example, aluminum.
The back-illuminated CMOS image sensor may further include a ground opening 38, the ground opening 38 penetrating a portion of the isolation layer 34 on the back surface 31b of the substrate and a portion of the thickness of the substrate 31 below the isolation layer 34.
The back-illuminated CMOS image sensor further includes a first shielding portion 37b and a second shielding portion 37 c. The material of the grid portion 37a, the first shielding portion 37b, and the second shielding portion 37c is, for example, aluminum.
The grid part 37a is located on a part of the high-k dielectric layer 34a on the back surface 31b of the substrate, the grid part 37a includes a plurality of grids, the grids are in a grid shape when viewed from top to bottom, the color filter layer includes a plurality of color filter units, the color filter units are formed in the grids (namely in the grids), microlenses are formed right above the color filter units, pixel units are correspondingly distributed in the substrate right below the color filter units, the pixel units include photoelectric sensitive elements (such as photodiodes), and the microlenses, the color filter units and the pixel units are in one-to-one correspondence in a direction perpendicular to the substrate. The grid-shaped grids well limit incident light, crosstalk is avoided, and imaging quality of the back-illuminated CMOS image sensor is improved.
Further, a gap 36 is formed between the pad layer 35 and the first opening 41, and the gap 36 is formed by etching to remove the irregular pad material layer near the inner wall of the first opening 41.
The first shielding portion 37b covers the surface of the gap 36, and extends to cover a partial region of the pad layer 35 and a partial region of the buffer layer 34 b. The first shielding portion 37b is used to shield the gap 36, so as to prevent light from entering the substrate from the gap 36 and prevent optical crosstalk.
The second shielding portion 37c fills the grounding opening 38 and covers a portion of the high-k dielectric layer 34a, and the second shielding portion 37c, the first shielding portion 37b and the grid portion 37a are spaced apart from each other to avoid mutual interference. Continuing to refer to fig. 4, the second shielding portion 37c is located in the light shielding region 30b when viewed from above, and the second shielding portion 37c is used to cover the region that does not need to be exposed to light on the back surface of the substrate, so as to prevent light crosstalk; meanwhile, the second shielding portion 37c (made of metal) contacts the substrate 31 through the grounding opening 38, and the back-illuminated CMOS image sensor is grounded to the outside through the second shielding portion 37c, so that electrostatic interference and other electromagnetic interference of the back-illuminated CMOS image sensor can be prevented, and signal stability is improved.
The embodiment of the invention also provides a method for manufacturing the back-illuminated CMOS image sensor, and the flow chart is shown as 3, and the method comprises the following steps:
providing a substrate, wherein the substrate is provided with a front surface and a back surface which are oppositely arranged, a dielectric layer is formed on the front surface of the substrate, and a connecting line layer is embedded in the dielectric layer;
forming a step-shaped opening, wherein the step-shaped opening is positioned in the substrate and the dielectric layer and above the connecting line layer, and the step-shaped opening exposes a partial area of the connecting line layer;
forming an isolation layer, wherein the isolation layer covers the surface of the step-shaped opening, exposes the connecting line layer and extends to cover the back surface of the substrate;
forming a bonding pad layer, wherein the bonding pad layer is positioned in the step-shaped opening and covers part of the isolation layer and is electrically connected with the connecting line layer; the absolute value of the height difference between the top surface of the pad layer and the top surface of the isolation layer on the back surface of the substrate is less than a preset value;
forming a grid portion on a back surface of the substrate; and
and forming a color filter layer positioned in the grids of the grid part.
A method for fabricating a backside illuminated CMOS image sensor according to an embodiment of the present invention is described in detail below with reference to fig. 5 to 11.
As shown in fig. 5, a substrate 31 is provided, the substrate 31 having a front surface 31a of the substrate and a back surface 31b of the substrate oppositely disposed; substrate 31 may be a silicon, germanium, silicon germanium, gallium arsenide substrate, or silicon on insulator substrate. The type of substrate can be selected as desired by those skilled in the art. A dielectric layer 32 is formed on the front surface 31a of the substrate, and a wiring layer 33 is embedded in the dielectric layer 32. A portion of the thickness of substrate 31 is etched to form first opening 41.
Next, as shown in fig. 6, the substrate at the bottom of the first opening 41 and the dielectric layer 32 with a partial thickness are etched to form a second opening 42, wherein the cross-sectional width of the second opening 42 is smaller than the cross-sectional width of the first opening 41.
Next, as shown in fig. 7, an isolation layer 34 is formed, the isolation layer 34 covering the surfaces of the first opening 41 and the second opening 42 and covering the back surface 31b of the substrate; the isolation layer 34 includes a high-permittivity dielectric layer 34a and a buffer layer 34b on the high-permittivity dielectric layer 34 a.
Next, as shown in fig. 8, a portion of the isolation layer 34 at the bottom of the second opening 42 and a portion of the dielectric layer 33 below the isolation layer are etched to form a third opening 43, the third opening 43 exposes the interconnection layer 33, and the cross-sectional width of the third opening 43 is smaller than the cross-sectional width of the second opening 42.
The first opening 41, the second opening 42 and the third opening 43 form a step-shaped opening, when the third opening 43 is formed, a portion of the isolation layer 34 is consumed, and the overall thickness of the isolation layer 34 is reduced.
Further, the first opening 41 is rectangular when viewed from top to bottom, and the cross-sectional shape perpendicular to the surface of the back-illuminated CMOS image sensor may be an inverted trapezoid or a rectangle; alternatively, the first opening 42 may extend through a portion of the thickness of the substrate 31, for example, more than 3 μm when the substrate 31 is thicker, and the first opening 41 may extend through the entire substrate 31, for example, when the substrate 31 is thinner, the depth of the first opening 41 extending through the substrate 31 may vary according to design requirements.
Alternatively, the cross-sectional width of the third opening 43 may be equal to the cross-sectional width of the second opening 42, so that a mask for forming the third opening 43 may be saved.
In this embodiment, the wiring layer 33 is not exposed when the second opening 42 is formed, but in other embodiments, the wiring layer 33 is exposed when the second opening 42 is formed, and then the isolation layer 34 is formed.
Next, as shown in fig. 9, a pad layer 35 is formed; a pad blank layer may be first formed by a Physical Vapor Deposition (PVD) process, which is formed in the stepped opening and extends over the isolation layer 34 on the back surface 31b of the substrate.
The absolute value of the height difference between the top surface of the pad raw material layer formed in the stepped opening and the top surface of the isolation layer 34 on the back surface 31b of the substrate is made smaller than a preset value by controlling the deposition time and related parameters; preferably, the preset value is 1000 angstroms; the pad material layer is electrically connected to the wiring layer 33; and
the pad material layer on the isolation layer 34 on the back surface 31b of the substrate is etched and removed, and the irregular pad material layer deposited near the inner wall of the first opening 41 is also etched and removed, so that a gap is formed between the remaining pad material layer and the first opening, and the remaining pad material layer constitutes the pad layer 35, so that the absolute value of the height difference between the top surface of the pad layer 35 and the top surface of the isolation layer 34 on the back surface 31b of the substrate is smaller than a predetermined value.
Preferably, the material of the pad layer 35 is, for example, aluminum.
In this embodiment, the pad layer 35 and the wiring layer 33 are electrically connected through a via composed of the second opening and the third opening, and in other embodiments, a plurality of vias may be disposed between the bottom of the first opening 41 and the wiring layer 33 to prevent the pad layer in one of the vias from being connected, so that the pad layer can be electrically connected through the other vias, thereby achieving the purpose of redundancy design.
Next, as shown in fig. 10, a ground opening 38 is formed; the isolation layer 34 on the back surface of the substrate and the substrate 31 below the isolation layer are etched to remove a part of the thickness, and a grounding opening 38 is formed.
Next, as shown in fig. 11, a grid portion is formed;
the buffer layer 34b on the back surface 31b of the substrate is etched to expose the high-k dielectric layer 34 a.
Then, a metal raw material layer, which is made of, for example, aluminum, may be formed by a process of Physical Vapor Deposition (PVD), and covers the upper surface of the pad layer 35, the surface of the gap 36 between the pad layer 35 and the first opening 41, the surface of the isolation layer on the back surface 31b of the substrate, and the surface of the ground opening 38.
Thereafter, the metal material layer is etched back to form the grid portion 37a, the first blocking portion 37b, and the second blocking portion 37 c. The grid part 37a is positioned on the high-dielectric-constant dielectric layer 34a on the back surface 31b of the substrate, and the first shielding part 37b covers the surface of the gap 36 between the pad layer 35 and the first opening 41 and extends to cover partial areas of the pad layer 35 and partial areas of the buffer layer 34 b; the first shielding portion 37b is used to shield the gap 36, so as to prevent light from entering the substrate 31 from the gap 36 and prevent optical crosstalk.
The second shielding portion 37c fills the grounding opening 38 and covers a portion of the high-k dielectric layer 34a, and the second shielding portion 37c, the first shielding portion 37b and the grid portion 37a are spaced apart from each other to avoid mutual interference. The second shielding portion 37c is used for covering the region which does not need to be exposed on the back surface 31b of the substrate, and preventing optical crosstalk; meanwhile, the second shielding portion 37c (made of metal) is in contact with the substrate 31 through the grounding opening 38, and the back-illuminated CMOS image sensor is grounded through the second shielding portion 37c, so that electrostatic interference and other electromagnetic interference of the back-illuminated CMOS image sensor can be prevented, and signal stability can be improved.
Next, a color filter layer is formed, the color filter layer includes a plurality of color filter layer cells, the grid portion 37a includes a plurality of grids, the grids are in a grid shape when viewed from top to bottom, the color filter layer cells are formed in the grids (i.e., in the grids), each color filter layer cell only allows incident light of a specific color to pass through, microlenses are formed right above the color filter layer cells, pixel cells are correspondingly distributed in a substrate right below the color filter layer cells, the pixel cells include photoelectric sensitive elements (such as photodiodes), and the microlenses, the color filter cells, and the pixel cells are in one-to-one correspondence in a direction perpendicular to the substrate. The grid-shaped grids well limit incident light, crosstalk is avoided, and imaging quality of the back-illuminated CMOS image sensor is improved.
The color filter layer is formed by adopting a spin coating process, the spin coating process conventionally comprises the step of uniformly spin coating raw materials on a plane, the raw materials of the color filter layer are coated in a grid (namely a grid) on the substrate, the absolute value of the height difference between the top surface of the welding pad layer 35 and the top surface of the isolation layer 34 on the back surface 31b of the substrate is smaller than a preset value, the whole surface to be coated is relatively flat, the raw materials of the surrounding color filter layer can be normally thrown out in the process of spin coating the raw materials of the color filter layer, the raw materials of the color filter layer formed by spin coating are uniform, the problem that the color filter layer has stripes due to non-uniformity is solved, and the image quality of the back-illuminated CMOS image sensor is improved.
The welding pad layer is positioned in the step-shaped opening, the absolute value of the height difference between the top surface of the welding pad layer and the top surface of the isolation layer on the back surface of the substrate is smaller than a preset value, so that the whole surface to be coated tends to be flat, the steps of filling the opening after the welding pad layer is formed, chemically and mechanically grinding and etching the filling layer through a photomask to expose the welding pad layer again in the prior art are omitted, and the process is simplified.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the method disclosed by the embodiment, the description is relatively simple because the method corresponds to the device disclosed by the embodiment, and the relevant part can be referred to the device part for description.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (9)

1. A backside-illuminated CMOS image sensor, comprising:
a substrate having oppositely disposed front and back surfaces,
a dielectric layer on the front side of the substrate;
the connecting wire layer is embedded in the dielectric layer;
the stepped opening is positioned in the substrate and the dielectric layer and above the connecting line layer, and the stepped opening exposes a partial area of the connecting line layer; the stepped opening comprises a first opening that extends through a portion of the thickness of the substrate;
the isolation layer covers the surface of the step-shaped opening, exposes the connecting line layer and extends to cover a partial area of the back surface of the substrate; the welding pad layer is positioned in the step-shaped opening and covers part of the isolation layer and is electrically connected with the connecting line layer; the absolute value of the height difference between the top surface of the pad layer and the top surface of the isolation layer on the back surface of the substrate is less than a preset value; the preset value is 1000 angstroms;
a ground opening through a portion of the isolation layer on a backside of the substrate and a portion of a thickness of the substrate below the isolation layer;
a grid portion on a back surface of the substrate; and
a color filter layer located in the grid of the grid part;
a gap is formed between the pad layer and the first opening, the back-illuminated CMOS image sensor further comprises a first shielding part and a second shielding part, and the first shielding part and the second shielding part are made of metal and are positioned in the same metal layer; the first shielding part covers the surface of the gap to prevent optical crosstalk; the second shielding part fills the grounding open hole and covers a part of the back surface of the substrate to prevent electrostatic interference and electromagnetic interference.
2. The backside-illuminated CMOS image sensor of claim 1, wherein the stepped opening further comprises:
the second opening penetrates through the substrate at the bottom of the first opening and the dielectric layer with partial thickness, and the section width of the second opening is smaller than that of the first opening; and
and the third opening penetrates through the dielectric layer at the bottom of the second opening and exposes the connecting line layer, and the section width of the third opening is smaller than that of the second opening.
3. The backside-illuminated CMOS image sensor of claim 1 or 2, the isolation layer comprising a high-permittivity dielectric layer and a buffer layer formed on the high-permittivity dielectric layer.
4. The backside-illuminated CMOS image sensor of claim 2, further comprising a ground opening that penetrates through a portion of the isolation layer and a portion of the thickness of the substrate at the backside of the substrate.
5. The backside-illuminated CMOS image sensor of claim 4, wherein the first shielding portion further extends to cover a partial region of the pad and a partial region of the backside of the substrate; the second shielding part, the first shielding part and the grid part are distributed at intervals.
6. A method for manufacturing a backside illuminated CMOS image sensor is characterized by comprising the following steps:
providing a substrate, wherein the substrate is provided with a front surface and a back surface which are oppositely arranged, a dielectric layer is formed on the front surface of the substrate, and a connecting line layer is embedded in the dielectric layer;
forming a step-shaped opening, wherein the step-shaped opening is positioned in the substrate and the dielectric layer and above the connecting line layer, and the step-shaped opening exposes a partial area of the connecting line layer; the stepped opening comprises a first opening that extends through a portion of the thickness of the substrate;
forming an isolation layer, wherein the isolation layer covers the surface of the step-shaped opening, exposes the connecting line layer and extends to cover the back surface of the substrate;
forming a bonding pad layer, wherein the bonding pad layer is positioned in the step-shaped opening and covers part of the isolation layer and is electrically connected with the connecting line layer; the absolute value of the height difference between the top surface of the pad layer and the top surface of the isolation layer on the back surface of the substrate is less than a preset value; the preset value is 1000 angstroms;
forming a ground opening through a portion of the isolation layer on the back side of the substrate and a portion of the thickness of the substrate below the isolation layer;
forming a grid portion on a back surface of the substrate; and
forming a color filter layer located in the cells of the cell part by a spin coating process;
a gap is formed between the pad layer and the first opening, the back-illuminated CMOS image sensor further comprises a first shielding part and a second shielding part, and the first shielding part and the second shielding part are made of metal and are located in the same metal layer; the first shielding part covers the surface of the gap to prevent optical crosstalk; the second shielding part fills the grounding open hole and covers a part of the back surface of the substrate to prevent electrostatic interference and electromagnetic interference.
7. The method of claim 6, wherein the step of forming the step-shaped opening and the isolation layer comprises:
etching the substrate at the bottom of the first opening and the dielectric layer with partial thickness to form a second opening, wherein the section width of the second opening is smaller than that of the first opening;
forming an isolation layer covering the surfaces of the first and second openings and covering the back surface of the substrate;
etching part of the isolation layer at the bottom of the second opening and the dielectric layer with partial thickness below the isolation layer to form a third opening, wherein the third opening exposes the connecting line layer, and the section width of the third opening is smaller than that of the second opening;
the step-shaped opening is formed by the first opening, the second opening and the third opening, and when the third opening is formed, a part of the isolation layer is consumed.
8. The method of fabricating a backside-illuminated CMOS image sensor according to claim 7, wherein the step of forming the pad layer comprises:
forming a pad raw material layer, wherein the pad raw material layer is formed in the stepped opening and extends to cover the isolation layer on the back surface of the substrate, and the absolute value of the height difference between the top surface of the pad raw material layer formed in the stepped opening and the top surface of the isolation layer on the back surface of the substrate is controlled to be smaller than a preset value; the welding pad raw material layer is electrically connected with the connecting line layer; and
and etching to remove the weld pad raw material layer on the back surface of the substrate, etching to remove the weld pad raw material layer near the inner wall of the first opening, forming a gap between the weld pad layer and the first opening, and forming the weld pad layer by the residual weld pad raw material layer.
9. The method of claim 8, further comprising, after forming the pad layer and before forming the grid portion:
and etching and removing the isolation layer of the partial area on the back surface of the substrate and the substrate with partial thickness below the isolation layer to form a grounding opening.
CN201811095233.9A 2018-09-19 2018-09-19 Backside illuminated CMOS image sensor and manufacturing method thereof Active CN109065562B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811095233.9A CN109065562B (en) 2018-09-19 2018-09-19 Backside illuminated CMOS image sensor and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811095233.9A CN109065562B (en) 2018-09-19 2018-09-19 Backside illuminated CMOS image sensor and manufacturing method thereof

Publications (2)

Publication Number Publication Date
CN109065562A CN109065562A (en) 2018-12-21
CN109065562B true CN109065562B (en) 2021-03-19

Family

ID=64763156

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811095233.9A Active CN109065562B (en) 2018-09-19 2018-09-19 Backside illuminated CMOS image sensor and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN109065562B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113644084B (en) * 2021-08-06 2023-12-01 武汉新芯集成电路制造有限公司 Semiconductor device and method for manufacturing the same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103972257B (en) * 2014-05-29 2017-01-04 豪威科技(上海)有限公司 Preparation method of stacked image sensor
US10204952B2 (en) * 2014-08-29 2019-02-12 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device having recess filled with conductive material and method of manufacturing the same
CN104362162A (en) * 2014-09-30 2015-02-18 武汉新芯集成电路制造有限公司 Image sensor with landfill type color filter and manufacture method thereof
US10833119B2 (en) * 2015-10-26 2020-11-10 Taiwan Semiconductor Manufacturing Co., Ltd. Pad structure for front side illuminated image sensor
KR102591546B1 (en) * 2016-09-02 2023-10-24 에스케이하이닉스 주식회사 Image Sensor Having Guard Dams
CN106298829B (en) * 2016-11-08 2019-05-03 武汉新芯集成电路制造有限公司 A kind of forming method of metal grate

Also Published As

Publication number Publication date
CN109065562A (en) 2018-12-21

Similar Documents

Publication Publication Date Title
JP7265869B2 (en) image sensor
US9024405B2 (en) Solid-state image sensor
TWI577001B (en) Solid-state imaging device, method of manufacturing solid-state imaging device, and electronic device
TWI699007B (en) Solid-state imaging devices
US7470965B2 (en) Solid-state imaging device
US7847361B2 (en) Solid state imaging device in which a plurality of imaging pixels are arranged two-dimensionally, and a manufacturing method for the solid state imaging device
CN107482028B (en) Image sensor structure for reducing crosstalk and improving quantum efficiency
CN106531753B (en) Image pickup apparatus and method of manufacturing the same
KR102578569B1 (en) Backside illuminated image sensor and method of manufacturing the same
US20100109113A1 (en) Semiconductor device and method for manufacturing the same
KR20090080490A (en) Solid-state imaging device, method of fabricating solid-state imaging device, and camera
US9136295B2 (en) Semiconductor device and method for manufacturing the same
KR102581170B1 (en) Backside illuminated image sensor and method of manufacturing the same
TW201904041A (en) Solid-state imaging device
CN101308821B (en) Method for manufacturing image sensor
KR20200030851A (en) Backside illuminated image sensor and method of manufacturing the same
CN109065562B (en) Backside illuminated CMOS image sensor and manufacturing method thereof
TWI717795B (en) Image sensor and method for forming the same
TWI710126B (en) Image sensor, semiconductor structure for an image sensor and method for manufacturing thereof
CN113658963A (en) Solid-state imaging device
US20200119062A1 (en) Backside Illuminated Image Sensor and Method of Manufacturing Same
US20240290812A1 (en) Image sensor
US20160172413A1 (en) Solid-state imaging apparatus and imaging system
KR100690175B1 (en) Cmos image sensor and method for fabricating the same
KR20230132221A (en) Backside illuminated image sensor and method of manufacturing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant