CN109037038A - Method for forming semiconductor device - Google Patents

Abstract

The invention discloses a method for forming a semiconductor device, which comprises the following steps. First, a material layer is formed on a substrate, and a first mask layer is formed on the material layer. The first mask layer includes a plurality of first blocking regions, each of which is arranged parallel to each other along a first axis. Next, a second mask layer is formed on the material layer. The second mask layer comprises a plurality of second blocking regions, wherein the second blocking regions are mutually parallel and arranged along the second axis, and at least one corner region of each second blocking region and each first blocking region are mutually overlapped. The material layer is then patterned using the corner regions as a mask to form a plurality of patterns, which form an array arrangement.

Description

Method for forming semiconductor device

technical field

The invention relates to a manufacturing process of a semiconductor device, in particular to a manufacturing process of forming a microstructure of a semiconductor device by multiple photolithography and etching.

Background technique

In the semiconductor manufacturing process, the manufacture of some microstructures requires the use of photolithography and etching in appropriate substrates or material layers such as semiconductor substrates/film layers, dielectric material layers, or metal material layers to form microstructures with Tiny patterns of precise dimensions. To achieve this purpose, in conventional semiconductor technology, a mask layer (mask layer) is formed on the target material layer, so that these tiny patterns are first formed/defined in the mask layer, and then the patterns are transferred to target layer. Generally speaking, the mask layer is, for example, a patterned photoresist layer formed by a photolithography process, and/or a patterned mask layer formed using the patterned photoresist layer.

With the complexity of integrated circuits, the size of these tiny patterns continues to decrease, so the equipment used to generate feature patterns must meet the strict requirements of manufacturing process resolution and overlay accuracy. Single patterning ( The single patterning) method has been unable to meet the resolution requirements or manufacturing process requirements for manufacturing micro-linewidth patterns. Therefore, semiconductor companies now mostly use multiple patterning (multiple patterning) methods, such as double patterning (double patterning) manufacturing process or spacer self-aligned double patterning (spacer self-aligned double patterning, SADP) manufacturing process, etc., as A way to overcome the resolution limit of lithographic exposure setups. However, the aforementioned two manufacturing processes are both precise and highly demanding manufacturing process methods, and their use inevitably increases the complexity and cost of the manufacturing process.

Contents of the invention

An object of the present invention is to provide a method for forming a semiconductor device, which uses two photolithography and etching processes to form two alternately arranged barrier regions, and uses the overlapping area of these barrier regions as the basis for the subsequent patterning process . Therefore, a semiconductor structure with a relatively dense layout and a relatively small size can be formed under the premise of simplifying the manufacturing process and saving costs.

To achieve the above purpose, an embodiment of the present invention provides a method for forming a semiconductor device, which includes the following steps. First, a material layer is formed on a substrate, and a first mask layer is formed on the material layer. The first mask layer includes a plurality of first blocking regions, and each first blocking region is arranged parallel to each other along a first axis. Next, a second mask layer is formed on the material layer. The second mask layer includes a plurality of second barrier regions, each second barrier region is arranged parallel to each other along a second axis, wherein each second barrier region is mutually connected to at least one corner region of each first barrier region overlapping. Then, the material layer is patterned by using the corner regions as a mask to form a plurality of patterns, and the patterns form an array arrangement.

In general, the present invention forms two different mask layers sequentially on a material layer, such as a hard mask layer and/or a target layer, and makes the two mask layers respectively comprise a plurality of regular The blocking regions have the same shape and the same spacing, and at least one corner region of each blocking region of the two mask layers overlaps with each other. Wherein, the blocking regions of the two mask layers can be selected to have the same shape, such as square, parallelogram, circle or ellipse, etc., or have different shapes, such as square and circle, but not This is the limit. Also, the overlapping corner regions may have the same or different areas, but not limited thereto. Therefore, only through a simple photolithography and etching process, and use the corner area as an etching mask to pattern the underlying material layer to form a target pattern with a relatively dense layout and a relatively small size, and achieve the production process Simplification and cost saving purposes.

Description of drawings

1 to 5 are schematic steps of a method for forming a semiconductor device in a first preferred embodiment of the present invention; wherein

1 is a schematic cross-sectional view of a semiconductor device after forming a first mask layer;

2 is a schematic cross-sectional view of a semiconductor device after forming a second mask layer;

3 is a schematic cross-sectional view of a semiconductor device after performing an etching process;

4 is a schematic top view of a semiconductor device after forming a first mask layer and a second mask layer;

5 is a schematic cross-sectional view of a semiconductor device after performing another etching process;

6 is a schematic diagram of a semiconductor device in a preferred embodiment of the present invention;

7 is a schematic diagram of steps of a method for forming a semiconductor device in a second preferred embodiment of the present invention;

8 is a schematic diagram of steps of a method for forming a semiconductor device in a third preferred embodiment of the present invention;

9 is a schematic diagram of steps of a method for forming a semiconductor device in a fourth preferred embodiment of the present invention;

FIG. 10 is a schematic diagram of the steps of the method for forming a semiconductor device in the fifth preferred embodiment of the present invention.

Description of main component symbols

100 basal layer

101 base

102 dielectric layer

103 plug structure

105 bit line structure

110 target layer

115 conductive patterns

130 hard mask layer

131 mask pattern

200 sacrificial layers

301 first mask layer

302 second mask layer

311, 321, 331, 341, 351 Barriers

311a, 321a, 331a, 341a, 351a first axis

311C, 321C, 331C, 341C, 351C corner area

312, 322, 332, 342, 352 Barriers

312a, 322a, 332a, 342a, 352a Second axis

312C, 322C, 332C, 342C, 352C corner area

P1, P21, P31, P41, P51 spacing

P2, P22, P32, P42, P52 spacing

D1 first direction

D2 second direction

D3 third direction

Detailed ways

In order to enable those who are familiar with the technical field of the present invention to further understand the present invention, several preferred embodiments of the present invention are enumerated below, and in conjunction with the accompanying drawings, the constitutional content and intended achievement of the present invention are explained in detail. effect.

Please refer to FIG. 1 to FIG. 5, which are schematic diagrams of the steps of a method for forming a semiconductor device in a preferred embodiment of the present invention, wherein FIG. 4 is a schematic top view of the semiconductor device at the formation stage, and the remaining drawings are is a schematic cross-sectional view of the semiconductor device at the formation stage. First, a substrate layer 100 is provided, which includes, for example, a semiconductor substrate (not shown) stacked in sequence, such as a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate ( epitaxial silicon substrate), silicon-on-insulator substrate, etc., and/or a dielectric layer (not shown), such as silicon oxide, silicon nitride, silicon oxynitride, etc., but not hereby limit. A target layer 110 and a hard mask layer 130 are sequentially formed on the base layer 100 , as shown in FIG. 1 .

In this embodiment, the hard mask layer 130 has, for example, a single-layer structure, which may include silicon nitride (SiN), silicon carbonitride (SiCN) and other materials, as shown in FIG. 1 . Alternatively, in another embodiment, the hard mask layer may also have a composite layer structure, for example, comprising a first hard mask layer (for example comprising silicon nitride) and a second hard mask layer (for example comprising silicon nitride) stacked in sequence. Contains titanium nitride), etc. Next, a first mask layer 301 and a second mask layer 302 are sequentially formed on the hard mask layer 130 . Specifically, the first mask layer 301 includes a plurality of barrier regions 311 disposed on the surface of the hard mask layer 130, and each barrier region 311 preferably has a regular and identical shape, such as a square (as shown in FIG. 4 ). or rhombus etc. Moreover, the barrier regions 311 are arranged apart from each other and have the same pitch P1 , as shown in FIG. 1 . In addition, if further viewed from a top view as shown in FIG. An array arrangement can be formed on the hard mask layer 130 . Wherein, the first axis 311a is, for example, the extension line of the central axis of each blocking area 311, so that each first axis 311a can pass through the center of each blocking area 311, and each blocking area 311 is equally divided into a symmetrical area along each first axis 311a. of two parts.

Next, a sacrificial layer 200 and a second mask layer 302 are formed on the first mask layer 301 and the hard mask layer 130 . The sacrificial layer 200 is a flat layer formed on the hard mask layer 130, which covers the hard mask layer 130 and the first mask layer 301 integrally, and further fills the gaps between the blocking regions 311 ,as shown in picture 2. The second mask layer 302 is formed on the sacrificial layer 200 and covers a part of the sacrificial layer 200 . Similarly, the second mask layer 302 includes a plurality of barrier regions 312 disposed on the surface of the sacrificial layer 200, each barrier region 312 has a regular and identical shape, and preferably has the same shape as the barrier region 311, such as a square Or rhombus, etc., but not limited thereto. Furthermore, the blocking regions 312 are also spaced apart from each other and have a pitch P2 that is the same as the pitch P1 , as shown in FIG. 2 . In addition, if further viewed from a top view as shown in FIG. It can also be arranged in an array on the hard mask layer 130 . Wherein, the second axis 312a is, for example, the extension line of the central axis of each blocking area 312, so that each second axis 312a can pass through the center of each blocking area 312, and each blocking area 312 is equally divided into two symmetrical areas along each second axis 312a. of two parts. Moreover, the second direction D2 is perpendicular to the first direction D1, that is, in this embodiment, the first axis 311a is perpendicular to the second axis 312a.

It should be noted that although the blocking area 312 has the same shape and pitch as the blocking area 311 , the blocking area 312 does not completely overlap the blocking area 311 . In this embodiment, the blocking regions 312 and the blocking regions 311 are arranged alternately in the projection direction perpendicular to the base layer 100, so that at least one corner region 312C of each blocking region 312 overlaps with one corner region 311C of the blocking region 311 , as shown in Figure 2 and Figure 4. Preferably, the first axis 311a is located between two adjacent blocking areas 312 and overlaps the centerlines of the two adjacent blocking areas 312, and the second axis 312a is also located between two adjacent blocking areas 311 and overlaps the two adjacent blocking areas 312. The center line of the adjacent blocking area 311, thus, the corner area 311C (312C) where each blocking area 311 overlaps with each blocking area 312 can also have the same and regular shape, and each corner area 311C (312C) can have the same area, For example, it is about 1/9 to 1/4 of the area of each blocking area 311 , 312 , but not limited thereto. In another embodiment, the first axis 311a may be chosen not to overlap the centerlines of two adjacent blocking regions 312, or the second axis 312a may be selected not to overlap the centerlines of two adjacent blocking regions 311, so that each blocking region The overlapping corner regions have different areas (not shown).

Then, an etching process is performed using each blocking region 312 of the second mask layer 302 as an etching mask to remove the sacrificial layer 200 not covered by each blocking region 312 and the first mask layer 311 thereunder. That is to say, the portion of each barrier area 311 that does not overlap with each barrier area 312 (ie, the non-corner area) will be removed together with the etched part of the sacrificial layer 200 . In each barrier area 311 , only the corner area 311C that overlaps with each upper barrier area 312 can be reserved, as shown in FIG. 3 .

After the second mask layer 302 and the remaining sacrificial layer 200 are completely removed, another etching process is then performed. In this etching process, the first mask layer 301 remaining on the hard mask layer 130, that is, the four corner regions 311C of each barrier region 311, is used as an etching mask to further transfer its pattern to the underlying hard mask layer 130. The mask layer 130 forms a plurality of mask patterns 131, as shown in FIG. 5 . Subsequently, after the corner regions 311C of the barrier regions 311 are completely removed, the underlying target layer 110 can be patterned using the mask pattern 131 as an etching mask, so as to form in the target layer 110 that can be positioned opposite to each corner region. Multiple target patterns (not shown) of 311C.

Thus, the manufacturing process of the first preferred embodiment of the present invention is completed. In this embodiment, barrier regions 311 and 312 with the same shape and spacing are formed sequentially on the hard mask layer 130 and the target layer 110, and each barrier region 311 and 312 is mutually connected at least in the corner regions 311C and 312C. overlapping. Thus, the underlying hard mask layer 130 and the target layer 110 can be sequentially patterned by using the corner regions 311C and 312C as etching masks. According to the method of this embodiment, each blocking area 311, 312 can have a regular and identical shape, such as a square or a rhombus, and each blocking area 311, 312 is respectively along the first axis 311a and the second axis extending in parallel. 312a are arranged sequentially, therefore, their overlapping corner regions 311C, 312C also have a regular and identical shape, such as a square (as shown in FIG. 4 ) or a rhombus, and the same area, for example, approximately 1/9 to 1/4 of the area of 312, but not limited thereto. In this case, the target patterns and mask patterns 131 finally formed according to the corner regions 311C, 312C also have regular and identical shapes, such as square or rhombus, and if viewed from a top view (not shown) As shown), the target patterns and the mask pattern 131 can also be arranged in an array.

It can be known from the above-mentioned embodiments that the formation method of the present invention forms the target pattern and the mask pattern 131 with a relatively dense layout and a relatively small size through a simple photolithography and etching process, thereby achieving the purpose of simplifying the process and saving costs. Therefore, the forming method of the present invention can be practically applied in the semiconductor manufacturing process, for example, to form a semiconductor storage device, such as a dynamic random access memory (DRAM) device, electrically connected to each storage node (storage node contact, SNC) contact pad.

That is to say, in one embodiment, the base layer 100 may include a semiconductor substrate 101, such as a silicon substrate, a silicon-containing substrate (such as SiC, SiGe), or a silicon-on-insulator (SOI) substrate, etc. , and a dielectric layer 102 formed thereon, for example comprising silicon nitride (SiN). Moreover, a buried transistor structure (not shown) is formed in the substrate 100 as a word line, and a plurality of bit line (BL) structures 105 are further formed in the dielectric layer 102 on the substrate 101, and A plurality of plug structures 103, as shown in FIG. 6 .

In this embodiment, the target layer 110 may optionally include a conductive layer, such as a low-resistance metal material such as tungsten (W), aluminum (Al) or copper (Cu), thus, Using the aforementioned forming method of the present invention, the conductive layer is patterned by using the mask pattern 131 to form a plurality of conductive patterns 115 , as shown in FIG. 6 . In this case, each conductive pattern 115 should also have a regular and identical shape, such as a square or a rhombus, and if viewed from a top view (not shown), the conductive patterns 115 can also be arranged in an array, and each conductive pattern 115 are respectively aligned and directly contact each of the lower plug structures 103 .

Thus, each conductive pattern 115 can be electrically connected to the lower plug structure 103, and serves as a storage node pad (SNpad), so that each plug structure 103 can pass through a metal silicide layer (silicide layer, not shown) and electrically connected to a source/drain region (not shown) of a transistor element, and serves as a storage node (storagenode contact, SNC). However, the practical application of the present invention should not be limited to the foregoing embodiments. In other embodiments, it can also be selected to be applied to other semiconductor manufacturing processes, so as to form a relatively dense layout and a relatively large size on the premise of simplifying the manufacturing process and saving costs. Tiny semiconductor structures.

Those skilled in the art should also understand that the formation method of the present invention is not limited to the aforementioned steps, and can also be achieved in other ways. For example, in some embodiments, the hard mask layer 130 may also be omitted, and the first mask layer 301 and the second mask layer 302 are directly formed on the target layer 110 . Other embodiments or variations of the forming method of the present invention will be described below. In order to simplify the description, the following description mainly focuses on the differences of the various embodiments, and the similarities will not be repeated. In addition, the same components in the various embodiments of the present invention are marked with the same symbols, so as to facilitate mutual comparison between the various embodiments.

Please refer to FIG. 7 , which shows the method for forming a semiconductor device in the second preferred embodiment of the present invention. The steps of this embodiment are substantially the same as those in the first preferred embodiment, and will not be repeated here. The main difference between the manufacturing process of this embodiment and the aforementioned first preferred embodiment is that although the barrier regions 321 of the first mask layer 301 and the barrier regions 322 of the second mask layer 302 also have regular and identical shapes, Each blocking area 321 , 322 is substantially a parallelogram, as shown in FIG. 7 .

Specifically, the blocking regions 321 are arranged apart from each other and have the same pitch P21. Moreover, the blocking regions 321 are also arranged sequentially along the first axis 321 a parallel to the first direction D1 , so that the blocking regions 321 can be arranged in an array on the hard mask layer 130 , as shown in FIG. 7 . On the other hand, the blocking regions 322 are also spaced apart from each other and have a pitch P22 that is the same as the pitch P21. In addition, each blocking region 322 is preferably arranged sequentially along the second axis 322 a extending parallel to a third direction D3 , so that each blocking region 322 can also be arranged in an array on the hard mask layer 130 . It should be noted that, in this embodiment, the third direction D3 only intersects with the first direction D1, but is not perpendicular to the first direction D1, that is, the first axis 321a and the second axis 322a of this embodiment Also, they only intersect but are not perpendicular to each other, and the first axis 311 a overlaps the centerlines of two adjacent blocking regions 322 , and the second axis 322 a overlaps the centerlines of two adjacent blocking regions 321 , as shown in FIG. 7 .

The blocking regions 322 , 321 are arranged alternately in a projection direction perpendicular to the base layer 100 , so that at least one corner region 322C of each blocking region 322 partially overlaps a corner region 321C of the blocking region 321 . Moreover, each corner area 321C, 322C may have a regular and identical shape, such as a parallelogram, and the same area, which is generally about one-ninth to one-fourth of the area of each blocking area 321, 322, but not This is the limit. Subsequently, as shown in FIGS. 3 to 4 of the first embodiment, at least one etching process is performed to sequentially transfer the patterns of the corner regions 321C and 322C to the underlying hard mask layer 130 and the target layer 110; Or in the case of omitting the hard mask layer, the patterns of the respective corner regions 321C, 322C are directly transferred to the underlying target layer 110 .

Thus, the manufacturing process of the second preferred embodiment of the present invention is completed. In this embodiment, the barrier regions 321 and 322 with the same shape and spacing are formed sequentially on the hard mask layer 130 and/or the target layer 110, so that each barrier region 321 and 322 is at least in its corner region 321C, 322C overlap each other, and the underlying hard mask layer 130 and/or target layer 110 can be sequentially patterned using the corner regions 321C, 322C as etching masks.

According to the method of this embodiment, even if the shape of each barrier area 321, 322 is a parallelogram, and its axes 321a, 322a only intersect but are not perpendicular, at least one corner area 321C, 322C of each barrier area 321, 322 can be mutually overlapping, and have a regular pattern with a relatively small area, such as a parallelogram as shown in Figure 7. In this case, the target patterns (not shown) and/or mask patterns (not shown) formed on the hard mask layer 130 and/or the target layer 110 according to the corner regions 321C and 322C also have the same Regular and identical shapes, such as parallelograms.

Please refer to FIG. 8 , which shows a method for forming a semiconductor device in a third preferred embodiment of the present invention. The steps of this embodiment are substantially the same as those in the first preferred embodiment, and will not be repeated here. The main difference between the manufacturing process of this embodiment and the aforementioned first preferred embodiment is that each barrier region 331 of the first mask layer 301 and each barrier region 332 of the second mask layer 302 are substantially circular, as shown in FIG. 8.

Specifically, the blocking regions 331 are arranged apart from each other and have the same pitch P31. Moreover, the blocking regions 331 are also arranged sequentially along the first axis 331 a parallel to the first direction D1 , so that the blocking regions 331 can be arranged in an array on the hard mask layer 130 , as shown in FIG. 8 . On the other hand, the blocking regions 332 are also spaced apart from each other and have a pitch P32 that is the same as the pitch P31. In addition, each blocking region 332 is preferably arranged sequentially along the second axis 332 a extending parallel to the second direction D2 , so that each blocking region 332 can also be arranged in an array on the hard mask layer 130 .

Moreover, the blocking regions 332 and 331 are arranged alternately in the projection direction perpendicular to the base layer 100 , so that at least one corner region 332c of each blocking region 332 partially overlaps with the blocking region 331-corner region 331C. The overlapping corner regions 331C, 332C also have a regular shape, such as a spindle shape as shown in FIG. 8 . In this embodiment, the areas of the corner regions 331C and 332C are the same, and are substantially smaller than the areas of the barrier regions 331 and 332 . Subsequently, the steps shown in FIG. 3 to FIG. 4 can be carried out, and the patterns of the corner regions 331C and 332C are sequentially transferred to the underlying hard mask layer 130 and the target layer 110; or the hard mask layer is omitted. In some cases, the patterns of the corner regions 331C and 332C are directly transferred to the underlying target layer 110 . Thus, the manufacturing process of the third preferred embodiment of the present invention is completed.

According to the method of this embodiment, even if each barrier area 331, 332 is circular in shape, at least one corner area 331C, 332C of each barrier area 331, 332 can overlap with each other and have a regular pattern with a relatively small area. In this case, the target patterns (not shown) and/or mask patterns (not shown) formed on the hard mask layer 130 and/or the target layer 110 according to the corner regions 331C and 332C also have the same Regular and identical shapes, such as spindles.

Please refer to FIG. 9 , which shows a method for forming a semiconductor device in a fourth preferred embodiment of the present invention. The steps of this embodiment are substantially the same as those in the second preferred embodiment, and will not be repeated here. The main difference between the manufacturing process of this embodiment and the aforementioned second preferred embodiment is that each barrier region 341 of the first mask layer 301 and each barrier region 342 of the second mask layer 302 are substantially elliptical, as shown in FIG. 9.

Specifically, the blocking regions 341 are arranged apart from each other and have the same pitch P41. Moreover, the blocking regions 341 are also arranged sequentially along the first axis 341 a parallel to the first direction D1 , so that the blocking regions 341 can be arranged in an array on the hard mask layer 130 , as shown in FIG. 9 . On the other hand, the blocking regions 342 are also spaced apart from each other and have a pitch P42 that is the same as the pitch P41. In addition, each blocking region 342 is preferably arranged sequentially along the third axis 342 a extending parallel to the third direction D3 , so that each blocking region 342 can also be arranged in an array on the hard mask layer 130 .

The blocking regions 342 are alternately arranged in a projection direction perpendicular to the base layer 100 , so that at least one corner region 342C of each blocking region 342 partially overlaps a corner region 341C of the blocking region 341 . Moreover, each corner area 341C, 342C also has a regular shape, and may have the same or different areas, such as the spindle shape shown in FIG. 9 . For example, in this embodiment, some of the corner regions 341C and 342C are spindle-shaped with relatively large areas, but it is not limited thereto. Subsequently, the aforementioned steps shown in FIG. 3 to FIG. 4 can be performed to sequentially transfer the patterns of the corner regions 341C and 342C to the underlying hard mask layer 130 and/or the target layer 110 .

Thus, the manufacturing process of the fourth preferred embodiment of the present invention is completed. According to the method of this embodiment, even if the shape of each barrier area 341 , 342 is ellipse, at least one corner area 341C, 342C of each barrier area 341 , 342 can overlap with each other and have a regular pattern with a relatively small area. In this case, the target patterns (not shown) and/or mask patterns (not shown) formed on the hard mask layer 130 and/or the target layer 110 according to the corner regions 341C and 342C also have the same Regular and identical shapes, such as spindles.

Please refer to FIG. 10 , which shows a method for forming a semiconductor device in a fifth preferred embodiment of the present invention. The steps of this embodiment are substantially the same as those in the first preferred embodiment, and will not be repeated here. The main difference between the fabrication process of this embodiment and the aforementioned first preferred embodiment is that the shapes of the barrier regions 351 of the first mask layer 301 and the barrier regions 352 of the second mask layer 302 are different. For example, each blocking area 351 is substantially square, and each blocking area 352 is substantially circular, as shown in FIG. 10 .

Specifically, the blocking regions 351 are arranged separately from each other and have the same pitch P51. Moreover, the blocking regions 351 are also arranged sequentially along the first axis 351 a parallel to the first direction D1 , so that the blocking regions 351 can be arranged in an array on the hard mask layer 130 , as shown in FIG. 10 . On the other hand, the blocking regions 352 are also spaced apart from each other and have a pitch P52 that is the same as the pitch P51. In addition, the blocking regions 352 are preferably arranged sequentially along the second axis 352 a parallel to the second direction D2 , so that the blocking regions 352 can also be arranged in an array on the hard mask layer 130 .

Thus, each barrier area 352 is still arranged alternately with each other in the projection direction perpendicular to the base layer 100, so that at least one corner area 352c of each barrier area 352 is partially overlapped with a corner area 351c of the barrier area 351, as shown in FIG. 10 . It should be noted that each blocking area 351, 352 has a regular and identical shape, such as a square and a circle, and each blocking area 351, 352 is respectively along the first axis 351a and the second axis 352a perpendicular to each other. Therefore, the overlapping corner regions 351C, 352C also have a regular shape, such as a fan shape as shown in FIG. 10 . The area of each corner area 351C, 352C is substantially smaller than the area of each blocking area 351, 352, and the area of each corner area 351C, 352C may be the same or different from each other, but not limited thereto.

Subsequently, the steps shown in FIG. 3 to FIG. 4 can be carried out, and the patterns of the corner regions 351C and 352C are sequentially transferred to the underlying hard mask layer 130 and/or the target layer 110 . Thus, the manufacturing process of the fifth preferred embodiment of the present invention is completed. According to the method of this embodiment, even if the shapes of the blocking regions 351, 352 are different, such as square and circular respectively, at least one corner region 351C, 352C of each blocking region 351, 352 can be overlapped with each other and have opposite areas. Smaller regular patterns, such as the fan shape shown in Figure 10. In this case, the target patterns (not shown) and/or mask patterns (not shown) formed on the hard mask layer 130 and/or the target layer 110 according to the corner regions 351C and 352C also have the same A regular and identical shape, such as a fan.

Generally speaking, the present invention is to sequentially form two different mask layers on a material layer, such as a hard mask layer and/or a target layer, and make the two mask layers include a plurality of regular shapes and The barrier areas have the same spacing, and only at least one corner area of the barrier areas overlaps with each other. Wherein, the barrier regions of the two mask layers can be selected to have the same shape, such as square, parallelogram or circle, etc., or have different shapes, such as square and circle, but this is not a limitation. limit. Therefore, only through a simple photolithography and etching process, and use the corner area as an etching mask to pattern the underlying material layer to form a target pattern with a relatively dense layout and a relatively small size, and achieve the production process Simplification and cost saving purposes. In addition, those skilled in the art should understand that although the aforementioned embodiments of the present invention use each of the blocking regions as a mask pattern as an implementation mode, it is not limited thereto. In other embodiments, if each of the barrier regions is used as an opening pattern, the corner regions of the barrier regions overlapping each other at least at their corners can define an array of openings, and then a part of the barrier region is removed by a subsequent etching process. The sacrificial layer, that is, defines a plurality of plug holes arranged in an array in the underlying hard mask layer and/or the target layer.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (18)

1. A method for forming a semiconductor device, comprising: forming a layer of material on a substrate; A first mask layer is formed on the material layer, the first mask layer includes a plurality of first barrier regions, and each first barrier region is arranged parallel to each other along a first axis; A second mask layer is formed on the material layer, the second mask layer includes a plurality of second barrier regions, and each second barrier region is arranged parallel to each other along a second axis, wherein the second axis and the the first axis intersects, and at least one corner area of each of the second blocking areas and each of the first blocking areas overlaps each other; and The material layer is patterned using the corner regions as a mask to form a plurality of patterns, and the patterns are arranged in an array. 2. The method for forming a semiconductor device according to claim 1, wherein the second axis is not perpendicular to the first axis. 3. The method for forming a semiconductor device according to claim 1, wherein the second axis is perpendicular to the first axis. 4. The method for forming a semiconductor device according to claim 1, wherein the first barrier regions and the second barrier regions have the same shape. 5. The method for forming a semiconductor device according to claim 4, wherein the first barrier regions and the second barrier regions are both square or rhombus. 6. The method for forming a semiconductor device according to claim 5, wherein the corner regions are square, and the area of each of the corner regions is approximately the area of each of the first barrier regions or each of the second barrier regions One-ninth to one-fourth of that. 7. The method for forming a semiconductor device according to claim 4, wherein the first barrier regions and the second barrier regions are parallelograms. 8. The method for forming a semiconductor device according to claim 7, wherein the corner regions are parallelograms, and the area of each corner region is approximately that of each of the first barrier regions or each of the second barrier regions One-ninth to one-fourth of the area. 9. The method for forming a semiconductor device according to claim 4, wherein the first barrier regions and the second barrier regions are both elliptical. 10. The method for forming a semiconductor device according to claim 4, wherein the first barrier regions and the second barrier regions are circular. 11. The method for forming a semiconductor device according to claim 1, wherein the first barrier regions and the second barrier regions have different shapes. 12. The method for forming a semiconductor device according to claim 1, wherein the corner regions have different areas. 13. The method for forming a semiconductor device according to claim 1, wherein the material layer comprises a hard mask layer. 14. The method for forming a semiconductor device according to claim 13, further comprising: forming a dielectric layer on the substrate; forming a plurality of plugs within the dielectric layer; forming a conductive layer over the dielectric layer and the plugs; and The conductive layer is patterned using the patterns as a mask. 15. The method for forming a semiconductor device according to claim 1, wherein the material layer comprises a conductive layer. 16. The method for forming a semiconductor device according to claim 15, further comprising: forming a dielectric layer on the substrate; and A plurality of plugs are formed in the dielectric layer, wherein the conductive layer is formed on the plugs and the dielectric layer. 17. The method for forming a semiconductor device according to claim 16, wherein the pattern pairs are located on the plugs and directly contact the plugs. 18 . The method for forming a semiconductor device according to claim 1 , wherein, in a projection direction, the first barrier regions and the second barrier regions are arranged alternately.