CN109037038A - The forming method of semiconductor device - Google Patents
The forming method of semiconductor device Download PDFInfo
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- CN109037038A CN109037038A CN201710426474.6A CN201710426474A CN109037038A CN 109037038 A CN109037038 A CN 109037038A CN 201710426474 A CN201710426474 A CN 201710426474A CN 109037038 A CN109037038 A CN 109037038A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
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Abstract
The present invention discloses a kind of forming method of semiconductor device, and it includes following steps.Firstly, material layer is formed on the substrate, and the first mask layer is formed in material layer.First mask layer includes multiple first Resistance, and each first Resistance is arranged along first axle in parallel to each other.Then, the second mask layer is formed in material layer.Second mask layer includes multiple second Resistance, and each second Resistance is arranged along second axis in parallel to each other, wherein an at least corner region for each second Resistance and each first Resistance is overlapped.Then, using corner region as mask come patterned material layer, to form multiple patterns, those patterns form an array arrangement.
Description
Technical field
The present invention relates to a kind of manufacture craft of semiconductor device, more particularly to it is a kind of using multiple Lithography Etching come shape
At the manufacture craft of the micro-structure of semiconductor device.
Background technique
In semiconductor fabrication process, the manufacture of some micro-structures is needed in semiconductor substrate/film layer, dielectric materials layer
Or in the substrate appropriate such as metal material layer or material layer, using manufacture crafts such as photoetching and etchings, being formed has accurate dimension
Micro pattern.It to reach this purpose, is that mask layer is formed on target material layer in traditional semiconductor technology
The grade patterns are then transferred to target so as to elder generation's formation/define these micro patterns in the mask layer by (mask layer)
Film layer.In general, mask layer is, for example, the patterning photoresist layer formed by lithographic fabrication process, and/or utilize
The patterned mask layer that the patterning photoresist layer is formed.
With the complication of integrated circuit, the size of these micro patterns is steadily decreasing, so being used to generate characteristic pattern
The equipment of case just must satisfy the strict demand of manufacture craft resolution ratio and overlay accuracy (overlay accuracy), single
Patterning (single patterning) method has been unable to satisfy the resolution requirements or manufacture craft for manufacturing small line width patterns
Demand.Therefore semiconductor dealer now mostly uses multiple patterning (multiple patterning) method, such as dual pattern
Change (double patterning) manufacture craft or the double pattern of clearance wall autoregistration (spacer self-aligned
Double patterning, SADP) manufacture craft etc., the approach as the resolution limit for overcoming photoetching exposure device.So
And aforementioned two manufacture craft is all that the control of accurate and manufacture craft requires high process for making, can not be kept away using upper
Increase complex manufacturing technology degree and manufacture craft cost with exempting from.
Summary of the invention
It is to utilize Twi-lithography etching system a purpose of the present invention is that providing a kind of forming method of semiconductor device
Alternately arranged two Resistance is formed as technique, and using the overlapping region of those Resistance as subsequent pattern manufacture craft
Foundation.As a result, can be under the premise of manufacture craft simplification to be with cost savings, formation layout is relatively intensive and size is relatively slight
Semiconductor structure.
In order to achieve the above object, one embodiment of the invention provides a kind of forming method of semiconductor device, it includes following
Step.Firstly, forming a material layer on a substrate, and first mask layer is formed in the material layer.This first
Mask layer includes multiple first Resistance, and each first Resistance is arranged along a first axle in parallel to each other.Then, exist
Second mask layer is formed in the material layer.Second mask layer includes multiple second Resistance, each second Resistance phase
It is mutually arranged in parallel along a second axis, wherein respectively at least one corner region of second Resistance and respectively first Resistance
It is overlapped.Then, the material layer is patterned as a mask using those corner regions, to form multiple patterns, those
Pattern forms an array arrangement.
Generally, the present invention is in a material layer, and an e.g. hard mask layer and/or a destination layer sequentially form
Two different mask layers, and two mask layer is made to separately include multiple Resistance with regular shape and identical spacing, and
An at least corner region for the respectively Resistance of two mask layer is overlapped.Wherein, tool may be selected in the Resistance of two mask layer
There is identical shape, be e.g. all square, parallelogram, round or ellipse etc., or with different shapes,
It is e.g. square and round, but not limited to this.Also, the corner region being respectively overlapped can have identical or different area,
But not limited to this.Simple photoetching process can only be passed through as a result, and come using the corner region as etching mask
The material layer of lower section is patterned, to form the relatively intensive and relatively slight size target pattern of layout, and reaches production work
The simplified purpose with cost savings of skill.
Detailed description of the invention
Fig. 1 to Fig. 5 is the step schematic diagram of the forming method of semiconductor device in first preferred embodiment of the invention；Wherein
Fig. 1 is diagrammatic cross-section of the semiconductor device after forming the first mask layer；
Fig. 2 is diagrammatic cross-section of the semiconductor device after forming the second mask layer；
Fig. 3 is diagrammatic cross-section of the semiconductor device after carrying out an etching process；
Fig. 4 is upper schematic diagram of the semiconductor device after forming the first mask layer and the second mask layer；
Fig. 5 is diagrammatic cross-section of the semiconductor device after carrying out another etching process；
Fig. 6 is the schematic diagram of semiconductor device in the preferred embodiment of the present invention；
Fig. 7 is the step schematic diagram of the forming method of semiconductor device in second preferred embodiment of the invention；
Fig. 8 is the step schematic diagram of the forming method of semiconductor device in third preferred embodiment of the invention；
Fig. 9 is the step schematic diagram of the forming method of semiconductor device in four preferred embodiment of the invention；
Figure 10 is the step schematic diagram of the forming method of semiconductor device in fifth preferred embodiment of the invention.
Main element symbol description
100 basal layers
101 substrates
102 dielectric layers
103 plug structures
105 bit line structures
110 destination layers
115 conductive patterns
130 hard mask layers
131 mask patterns
200 sacrificial layers
301 first mask layers
302 second mask layers
311,321,331,341,351 Resistance
311a, 321a, 331a, 341a, 351a first axle
311C, 321C, 331C, 341C, 351C corner region
312,322,332,342,352 Resistance
312a, 322a, 332a, 342a, 352a second axis
312C, 322C, 332C, 342C, 352C corner region
P1, P21, P31, P41, P51 spacing
P2, P22, P32, P42, P52 spacing
D1 first direction
D2 second direction
D3 third direction
Specific embodiment
To enable the general technology person for being familiar with the technical field of the invention to be further understood that the present invention, hereafter spy is enumerated
Several preferred embodiments of the invention, and cooperate appended attached drawing, the constitution content that the present invention will be described in detail and to be reached
Effect.
Please refer to Fig. 1 to Fig. 5, illustrated is in the preferred embodiment of the present invention, the forming method of semiconductor device
Step schematic diagram, wherein Fig. 4 is the semiconductor device in the upper schematic diagram of formation stages, remaining attached drawing is then the semiconductor
It is installed on the diagrammatic cross-section of formation stages.Firstly, provide a basal layer (substrate layer) 100, such as comprising according to
The semiconductor substrate (not being painted) that sequence stacks, such as silicon base (silicon substrate), (silicon- containing silicon base
Containing substrate), extension silicon base (epitaxial silicon substrate), silicon-coated insulated substrate
(silicon-on-insulator substrate) etc. an and/or dielectric layer (not being painted), such as comprising silica, silicon nitride,
Silicon oxynitride etc., but not limited to this.A destination layer 110 and a hard mask layer 130 are also sequentially formed on basal layer 100, such as
Shown in Fig. 1.
In the present embodiment, hard mask layer 130 is, for example, to have a single layer structure, may include silicon nitride (SiN), carbon nitrogen
The materials such as SiClx (SiCN), as shown in Figure 1.Alternatively, in another embodiment, which can also have a composite layer knot
Structure, such as comprising the first hard mask layer (such as comprising silicon nitride) sequentially stacked and the second hard mask layer (such as include nitridation
Titanium) etc..Then, the first mask layer 301 and the second mask layer 302 are sequentially formed on hard mask layer 130.Specifically, first
Mask layer 301 includes the multiple Resistance 311 being arranged on 130 surface of hard mask layer, and each Resistance 311 preferably has rule
And identical shape, such as square (as shown in Figure 4) or diamond shape.Also, each Resistance 311 is mutually separated setting, and is had
There is identical spacing P1, as shown in Figure 1.In addition, if further from the point of view of a top view as shown in Figure 4, each Resistance 311
Preferably along the multiple first axle 311a sequentials extended in parallel towards a first direction D1, make each Resistance 311 can
(array arrangement) is arranged at an array on hard mask layer 130.Wherein, first axle 311a is, for example, each blocking
The extension line of the central axis in area 311 makes each first axle 311a that can run through the center of each Resistance 311, and by each Resistance 311
It is divided into along each symmetrical two parts of first axle 311a.
Then, a sacrificial layer 200 and the second mask layer 302 are formed on the first mask layer 301 and hard mask layer 130.
Sacrificial layer 200 is formed in the flatness layer on hard mask layer 130, be globality be covered on hard mask layer 130 and first
On mask layer 301, and the gap between each Resistance 311 is further filled up, as shown in Figure 2.And the second mask layer 302 is then shape
At on sacrificial layer 200, and cover the sacrificial layer 200 of a part.Similarly, the second mask layer 302 includes to be arranged in sacrificial layer
Multiple Resistance 312 on 200 surfaces, each Resistance 312 have rule and identical shape, and preferably have and Resistance
311 identical shapes, such as square or diamond shape, but not limited to this.Furthermore each Resistance 312 is also mutually separated setting,
And there is a spacing P2 identical with spacing P1, as shown in Figure 2.In addition, if further coming from a top view as shown in Figure 4
It sees, each Resistance 312 is preferably along the multiple second axis 312a sequentials extended in parallel towards a second direction D2, is made
Each Resistance 312 can equally arrange on hard mask layer 130 at an array.Wherein, second axis 312a is, for example, each Resistance
The extension line of 312 central axis makes each second axis 312a that can run through the center of each Resistance 312, and by each Resistance 312
It is divided into along each symmetrical two parts of second axis 312a.Also, second direction D2 is perpendicular to first direction D1, that is, at this
In embodiment, first axle 311a is perpendicular to second axis 312a.
Although Resistance 312 is simultaneously it is noted that Resistance 312 is of similar shape with Resistance 311 and spacing
It will not be completely overlapped in Resistance 311.In the present embodiment, each Resistance 312 is with Resistance 311 perpendicular to basal layer 100
Projecting direction on be to be alternately arranged with each other, so that an at least corner region 312C for each Resistance 312 is overlapped in Resistance 311 1
Corner region 311C, as shown in Figures 2 and 4.Preferably, first axle 311a and is overlapped between two adjacent Resistance 312
Middle line in two adjacent Resistance 312, and second axis 312a is also located between two adjacent Resistance 311, and is overlapped two-phase neighbour
The middle line of Resistance 311, each Resistance 311 corner region 311C (312C) Chong Die with each Resistance 312 can equally have as a result,
Identical and regular shape, and each corner region 311C (312C) can have same area, such as be about each Resistance 311,312
/ 9th of area are to a quarter, and but not limited to this.In another embodiment, it may be selected to weigh first axle 311a not
It is laminated on the middle line of two adjacent Resistance 312, or selects the middle line for making second axis 312a not be overlapped two adjacent Resistance 311, and
Make respectively corner region that respectively Resistance is overlapped that there is different areas (not drawing formula).
Then, it is that etching mask carries out an etching process with each Resistance 312 of the second mask layer 302, removes not
The sacrificial layer 200 that is covered by each Resistance 312 and the first mask layer 311 below.That is, in each Resistance 311 not
The part (i.e. non-corner region) Chong Die with each Resistance 312 can be removed together along with the partial sacrificial layer 200 being etched.
And in each Resistance 311 only can be Chong Die with each Resistance 312 of top corner region 311C can be retained, as shown in Figure 3.
The second mask layer 302 is being removed completely with after remaining sacrificial layer 200, is making work followed by another etching is carried out
Skill.The etching process is then the first mask layer 301 to remain on hard mask layer 130, i.e., 4 of each Resistance 311
Its pattern is further transferred to the hard mask layer 130 of lower section as an etching mask, forms multiple masks by corner region 311C
Pattern 131, as shown in Figure 5.It is subsequent, then it can be after the corner region 311C for removing completely each Resistance 311, separately with mask pattern
131 pattern the destination layer 110 of lower section as etching mask, can be to positioned at each corner region with the formation in destination layer 110
Multiple target patterns (not being painted) of 311C.
The manufacture craft of first preferred embodiment of the invention is completed as a result,.In the present embodiment, mainly in hard mask
Layer 130 with shape Resistance 311,312 identical with spacing is sequentially formed on destination layer 110, and make each Resistance 311,312 to
It is few to overlap each other in its corner region 311C, 312C.As a result, i.e. can using its corner region 311C, 312C as etching mask come according to
The hard mask layer 130 and destination layer 110 of sequence patterning lower section.Method according to the present embodiment, each Resistance 311,312 can all have
Regular and identical shape, such as square or diamond shape, and each Resistance 311,312 is respectively along first extended in parallel
Axis 311a and second axis 312a sequential, therefore, overlapped corner region 311C, 312C also have rule and phase
Same shape, such as square (as shown in Figure 4) or diamond shape and identical area, such as it is about each Resistance 311,312 faces
Long-pending 1/9th are to a quarter, and but not limited to this.In the case, the last shape according to each corner region 311C, 312C
At those target patterns and mask pattern 131, also the same have rule and an identical shape, such as square or diamond shape, and
If those target patterns can also be arranged with mask pattern 131 at an array from the point of view of a top view (not being painted).
By the above embodiments it is found that forming method of the invention, forms cloth by simple photoetching process
Office relatively intensive and relatively slight size target pattern and mask pattern 131, and reach manufacture craft simplification and cost savings
Purpose.Therefore, forming method of the invention can be applied in semiconductor fabrication process, such as to form semiconductor
Storage device, e.g. a dynamic random are handled in memory (dynamic random access memory, DRAM) device,
It is electrically connected the engagement pad of each memory node (storage node contact, SNC).
That is, in one embodiment, basal layer 100 can be made to include semiconductor base 101, an e.g. silicon base,
Containing silicon base (such as SiC, SiGe) or silicon-coated insulated (silicon-on-insulator, SOI) substrate etc., and it is formed thereon
A dielectric layer 102, such as include silicon nitride (SiN).Also, an embedded transistor arrangement is also formed in substrate 100 (not
It is painted) using as character line, and multiple bit lines (bit line, BL) is then formed further in the dielectric layer 102 in substrate 101
Structure 105, and multiple plug structures 103, as shown in Figure 6.
And the destination layer 110 of the present embodiment then may be selected to include a conductive layer, such as include tungsten (tungsten, W), aluminium
The low resistances metal material such as (aluminum, Al) or copper (copper, Cu), as a result, i.e. using present invention formation side above-mentioned
Method patterns the conductive layer using mask pattern 131, forms multiple conductive patterns 115, as shown in Figure 6.In the case, respectively
Conductive pattern 115 should equally have rule and identical shape, such as square or diamond shape, and if coming from a top view (not being painted)
It sees, conductive pattern 115 can also be arranged at an array, and each conductive pattern 115 aligns respectively and each plug of directly contact lower section
Structure 103.
Each conductive pattern 115 can be electrically connected the plug structure 103 of lower section as a result, and as a memory node connection pad (SN
Pad), enabling each plug structure 103 by being located at a metal silicide layer on 101 surface of substrate, (silicide layer, does not draw
Show) and it is electrically connected to the source/drain region (not being painted) of a transistor unit, and as a memory node (storage
node contact,SNC).However, practical application of the invention should be not limited to aforementioned implementation pattern, in other embodiments,
Other semiconductor fabrication process are optionally applied to, to form layout phase under the premise of manufacture craft simplification is with cost savings
To intensive and relatively slight size semiconductor structure.
The usual skill in this field can also pass through it will also be appreciated that forming method of the invention is not limited to aforementioned step
Other modes are reached.For example, it in some embodiments, also may be selected to omit hard mask layer 130, and by the first mask layer 301
It is formed directly on destination layer 110 with the second mask layer 302.Below for the other embodiments or change of forming method of the present invention
Change type is illustrated.And illustrate to simplify, illustrate to be described in detail mainly for each embodiment difference below, and no longer to phase
It is repeated with place.In addition, identical element system is indicated in various embodiments of the present invention with identical label, with benefit
It checks one against another between each embodiment.
It please refers to shown in Fig. 7, is painted the forming method of the semiconductor device in second preferred embodiment of the invention, this reality
The step of applying is generally identical as aforementioned first preferred embodiment, is not repeating in this.The manufacture craft of the present embodiment is with before
First preferred embodiment main difference is stated to be, each Resistance 321 of the first mask layer 301 and the second mask layer 302 it is each
Though Resistance 322 equally has rule and identical shape, each Resistance 321,322 are generally into a parallelogram,
As shown in Figure 7.
Specifically, each Resistance 321 is mutually separated setting, and spacing P21 having the same.Also, it is each to stop
Area 321 is equally to make each Resistance 321 can be along the first axle 321a sequential extended in parallel towards first direction D1
It is arranged on hard mask layer 130 at an array, as shown in Figure 7.On the other hand, each Resistance 322 is also mutually separated setting, and is had
There is a spacing P22 identical with spacing P21.In addition, each Resistance 322 is preferably extended in parallel along towards a third direction D3
Second axis 322a sequential, arrange each Resistance 322 equally can on hard mask layer 130 at an array.It should be noted
, in the present embodiment, third direction D3 only intersects with first direction D1, but is not perpendicular to first direction D1, that is,
It says, the first axle 321a of the present embodiment is equally only to intersect without being mutually perpendicular to second axis 322a, and first axle
311a is overlapped the middle line of two adjacent Resistance 322, and second axis 322a is overlapped the middle line of adjacent two Resistance 321, such as Fig. 7 institute
Show.
Each Resistance 322,321 is to be alternately arranged with each other on the projecting direction perpendicular to basal layer 100, makes each Resistance
A 322 at least corner region 322C partially overlaps 321 1 corner region 321C of Resistance.Also, each corner region 321C, 322C can
With rule and identical shape, such as parallelogram and identical area are generally about each Resistance 321,322
/ 9th of area are to a quarter, and but not limited to this.It is subsequent, can as shown in Fig. 3 to Fig. 4 of first embodiment, into
The pattern of each corner region 321C, 322C, are sequentially transferred to the hard mask layer 130 and mesh of lower section by a row at least etching process
Mark layer 110；Or in the case where omitting the hard mask layer, the pattern of each corner region 321C, 322C are directly transferred to lower section
Destination layer 110.
The manufacture craft of second preferred embodiment of the invention is completed as a result,.In the present embodiment, mainly in hard mask
Layer 130 and/or destination layer 110 on sequentially form the Resistance 321,322 with same shape and spacing, make each Resistance 321,
322 at least overlap each other in its corner region 321C, 322C, and can using its corner region 321C, 322C as etching mask come according to
The hard mask layer 130 and/or destination layer 110 of sequence patterning lower section.
Method according to the present embodiment, even if the shape of each Resistance 321,322 is parallelogram, and its axis
321a, 322a only intersect and out of plumb, and at least corner region 321C, 322C of each Resistance 321,322 can also be made to overlap each other,
And there is the relatively small regular pattern of area, parallelogram as shown in Figure 7.In the case, finally according to each corner
Area 321C, 322C and the target pattern (not being painted) and/or mask pattern formed in hard mask layer 130 and/or destination layer 110
(not being painted), it is also the same that there is rule and identical shape, such as parallelogram.
It please refers to shown in Fig. 8, is painted the forming method of the semiconductor device in third preferred embodiment of the invention, this reality
The step of applying is generally identical as aforementioned first preferred embodiment, is not repeating in this.The manufacture craft of the present embodiment is with before
First preferred embodiment main difference is stated to be, each Resistance 331 of the first mask layer 301 and the second mask layer 302 it is each
Resistance 332 is generally in a circle, as shown in Figure 8.
Specifically, each Resistance 331 is mutually separated setting, and spacing P31 having the same.Also, it is each to stop
Area 331 is equally to make each Resistance 331 can be along the first axle 331a sequential extended in parallel towards first direction D1
It is arranged on hard mask layer 130 at an array, as shown in Figure 8.On the other hand, each Resistance 332 is also mutually separated setting, and is had
There is a spacing P32 identical with spacing P31.In addition, each Resistance 332 is preferably along extending in parallel towards second direction D2
Second axis 332a sequential arrange each Resistance 332 equally can on hard mask layer 130 at an array.
Also, each Resistance 332,331 is to be alternately arranged with each other on the projecting direction perpendicular to basal layer 100, is made each
An at least corner region 332c for Resistance 332 partially overlaps 331 1 corner region 331C of Resistance.Its overlapped corner region
331C, 332C also have well-regulated shape, spindle as shown in Figure 8.In the present embodiment, each corner region 331C, 332C
Area is identical, and is generally less than the area of each Resistance 331,332.It is subsequent, it can carry out such as earlier figures 3 to step shown in Fig. 4
Suddenly, the pattern of each corner region 331C, 332C are sequentially transferred to the hard mask layer 130 and destination layer 110 of lower section；Or it is omitting
In the case where the hard mask layer, the pattern of each corner region 331C, 332C are directly transferred to the destination layer 110 of lower section.It is as a result,
Complete the manufacture craft of third preferred embodiment of the invention.
Method according to the present embodiment, though the shape of each Resistance 331,332 be circle, can also make each Resistance 331,
332 at least corner region 331C, 332C overlaps each other, and has the relatively small regular pattern of area.In the case, most
The target pattern (not being painted) that is formed afterwards according to each corner region 331C, 332C and in hard mask layer 130 and/or destination layer 110 and/
Or mask pattern (not being painted), it is also the same that there is rule and identical shape, such as spindle.
It please refers to shown in Fig. 9, is painted the forming method of the semiconductor device in four preferred embodiment of the invention, this reality
The step of applying is generally identical as aforementioned second preferred embodiment, is not repeating in this.The manufacture craft of the present embodiment is with before
The second preferred embodiment main difference is stated to be, each Resistance 341 of the first mask layer 301 and the second mask layer 302 it is each
Resistance 342 is generally in an ellipse, as shown in Figure 9.
Specifically, each Resistance 341 is mutually separated setting, and spacing P41 having the same.Also, it is each to stop
Area 341 is equally to make each Resistance 341 can be along the first axle 341a sequential extended in parallel towards first direction D1
It is arranged on hard mask layer 130 at an array, as shown in Figure 9.On the other hand, each Resistance 342 is also mutually separated setting, and is had
There is a spacing P42 identical with spacing P41.In addition, each Resistance 342 is preferably along extending in parallel towards third direction D3
Third axis 342a sequential, arrange each Resistance 342 equally can on hard mask layer 130 at an array.
Each Resistance 342 is to be alternately arranged with each other on the projecting direction perpendicular to basal layer 100, makes each Resistance 342
An at least corner region 342C partially overlap 341 1 corner region 341C of Resistance.Also, each corner region 341C, 342C also have
Well-regulated shape, also, can have identical or different area, spindle as shown in Figure 9.For example, in this implementation
In example, part corner region 341C, 342C are the biggish spindle of area, and but not limited to this.It is subsequent, earlier figures 3 can be carried out
To step shown in Fig. 4, the pattern of each corner region 341C, 342C are sequentially transferred to the hard mask layer 130 and/or destination layer of lower section
110。
The manufacture craft of four preferred embodiment of the invention is completed as a result,.Method according to the present embodiment, even if each resistance
The shape for keeping off area 341,342 is ellipse, and at least corner region 341C, 342C of each Resistance 341,342 can also be made to weigh each other
It is folded, and there is the relatively small regular pattern of area.In the case, it is finally being covered firmly according to each corner region 341C, 342C
The target pattern (not being painted) and/or mask pattern (not being painted) that mold layer 130 and/or destination layer 110 are formed, it is also the same that there are rule
Then and identical shape, such as spindle.
It please refers to shown in Figure 10, is painted the forming method of the semiconductor device in fifth preferred embodiment of the invention, this
The step of embodiment, is generally identical as aforementioned first preferred embodiment, is not repeating in this.The manufacture craft of the present embodiment with
Aforementioned first preferred embodiment main difference is, each Resistance 351 of the first mask layer 301 and the second mask layer 302
The shape of each Resistance 352 is different.For example, each Resistance 351 is generally square in one, and each Resistance 352 is big
It is in a circle, as shown in Figure 10 on body.
Specifically, each Resistance 351 is mutually separated setting, and spacing P51 having the same.Also, it is each to stop
Area 351 is equally to make each Resistance 351 can be along the first axle 351a sequential extended in parallel towards first direction D1
It is arranged on hard mask layer 130 at an array, as shown in Figure 10.On the other hand, each Resistance 352 is also mutually separated setting, and
With a spacing P52 identical with spacing P51.In addition, each Resistance 352 is preferably extended in parallel along towards second direction D2
Second axis 352a sequential, arrange each Resistance 352 equally can on hard mask layer 130 at an array.
Each Resistance 352 is still to be alternately arranged with each other on the projecting direction perpendicular to basal layer 100 as a result, makes each resistance
An at least corner region 352c in gear area 352 partially overlaps 351 1 corner region 351C of Resistance, as shown in Figure 10.It should be noted
It is that each Resistance 351,352 is to be respectively provided with rule and identical shape, such as square and circle, and each Resistance 351,352
It is respectively along orthogonal first axle 351a and second axis 352a sequential, therefore, overlapped corner
Area 351C, 352C also have well-regulated shape, sector as shown in Figure 10.The area of each corner region 351C, 352C are generally small
Area in each Resistance 351,352, and the area of each corner region 351C, 352C can be the same or different from each other, but not with this
It is limited.
It is subsequent, step shown in Fig. 3 to Fig. 4 can be carried out, the pattern of each corner region 351C, 352C are sequentially transferred to lower section
Hard mask layer 130 and/or destination layer 110.The manufacture craft of fifth preferred embodiment of the invention is completed as a result,.According to this
The method of embodiment, though the shape of each Resistance 351,352 is different, such as be square respectively with it is round, each resistance can also be made
At least corner region 351C, a 352C in gear area 351,352 overlaps each other, and has the relatively small regular pattern of area, such as schemes
Sector shown in 10.In the case, finally according to each corner region 351C, 352C in hard mask layer 130 and/or destination layer
110 target patterns (not being painted) and/or mask pattern (not being painted) formed, it is also the same with regular and identical shape, such as
It is fan-shaped.
Generally, the present invention is in a material layer, and an e.g. hard mask layer and/a destination layer sequentially form two
Different mask layers, and two mask layer is made to include multiple Resistance with regular shape and identical spacing, and Resistance
Only at least a corner region is overlapped.Wherein, the Resistance of two mask layer may be selected to be of similar shape, and e.g. all be
Square, parallelogram or circle etc., or with different shapes, be e.g. square and round, but not with this
It is limited.Simple photoetching process can only be passed through as a result, and patterned down using the corner region as etching mask
The material layer of side, to form the target pattern that layout is relatively intensive and size is relatively slight, and reach manufacture craft simplify with
The purpose of cost savings.In addition, this field person has usually intellectual, it is to be appreciated that though present invention is respectively should
Pattern is implemented as mask pattern in Resistance, but is not limited.In other embodiments, if respectively the Resistance is
As patterns of openings, then respectively the Resistance at least then can define aperture array in respectively corner region that its corner overlaps each other,
The sacrificial layer of part is removed by subsequent etch manufacture craft again, it can be in hard mask layer and/or the target of lower section
Multiple plug holes arranged into an array are defined in layer.
The above description is only a preferred embodiment of the present invention, all equivalent changes done according to the claims in the present invention with repair
Decorations, should all belong to the scope of the present invention.
Claims (18)
1. a kind of forming method of semiconductor device, characterized by comprising:
A material layer is formed on a substrate；
First mask layer is formed in the material layer, which includes multiple first Resistance, each first resistance
Area is kept off to arrange along a first axle in parallel to each other；
Second mask layer is formed in the material layer, which includes multiple second Resistance, each second resistance
It keeps off area to arrange along a second axis in parallel to each other, wherein the second axis intersects with the first axle, and respectively second resistance
At least one corner region for keeping off area and respectively first Resistance is overlapped；And
Using those corner regions as the mask patterning material layer, to form multiple patterns, those patterns are into an array
Arrangement.
2. the forming method of semiconductor device as described in claim 1, which is characterized in that the second axis be not orthogonal to this
One axis.
3. the forming method of semiconductor device as described in claim 1, which is characterized in that the second axis perpendicular to this first
Axis.
4. the forming method of semiconductor device as described in claim 1, which is characterized in that those first Resistance and those the
Two Resistance are of similar shape.
5. the forming method of semiconductor device as claimed in claim 4, which is characterized in that those first Resistance and those the
Two Resistance are all square or diamond shape.
6. the forming method of semiconductor device as claimed in claim 5, which is characterized in that those corner regions are square, and
Respectively the area of the corner region about respectively first Resistance or respectively 1/9th of the area of second Resistance to a quarter.
7. the forming method of semiconductor device as claimed in claim 4, which is characterized in that those first Resistance and those the
Two Resistance are all parallelogram.
8. the forming method of semiconductor device as claimed in claim 7, which is characterized in that those corner regions are parallel four side
Shape, and respectively the area of the corner region is about respectively first Resistance or respectively 1 to four/9th point of the area of second Resistance
One of.
9. the forming method of semiconductor device as claimed in claim 4, which is characterized in that those first Resistance and those the
Two Resistance are all ellipse.
10. the forming method of semiconductor device as claimed in claim 4, which is characterized in that those first Resistance and those
Second Resistance is all round.
11. the forming method of semiconductor device as described in claim 1, which is characterized in that those first Resistance and those
Second Resistance has different shapes.
12. the forming method of semiconductor device as described in claim 1, which is characterized in that those corner regions have different
Area.
13. the forming method of semiconductor device as described in claim 1, which is characterized in that the material layer includes a hard mask
Layer.
14. the forming method of semiconductor device as claimed in claim 13, which is characterized in that also include:
A dielectric layer is formed on this substrate；
Multiple plugs are formed in the dielectric layer；
A conductive layer is formed on the dielectric layer and those plugs；And
The conductive layer is patterned as mask using those patterns.
15. the forming method of semiconductor device as described in claim 1, which is characterized in that the material layer includes a conductive layer.
16. the forming method of semiconductor device as claimed in claim 15, which is characterized in that also include:
A dielectric layer is formed on this substrate；And
Multiple plugs are formed in the dielectric layer, wherein the conductive layer is formed on those plugs and the dielectric layer.
17. the forming method of semiconductor device as claimed in claim 16, which is characterized in that those patterns are to positioned at the plug
And directly contact those plugs.
18. the forming method of semiconductor device as described in claim 1, which is characterized in that on a projecting direction, those
One Resistance is alternately arranged with those second Resistance.
Priority Applications (1)
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|---|---|---|---|
| CN201710426474.6A CN109037038A (en) | 2017-06-08 | 2017-06-08 | The forming method of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710426474.6A CN109037038A (en) | 2017-06-08 | 2017-06-08 | The forming method of semiconductor device |
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Family
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1393906A (en) * | 2001-06-26 | 2003-01-29 | 联华电子股份有限公司 | Process for preparing lower storage junctions of DRAM |
| US20100112463A1 (en) * | 2008-11-03 | 2010-05-06 | Hynix Semiconductor Inc. | Method for forming fine contact hole pattern of semiconductor device |
| US20130129991A1 (en) * | 2010-08-09 | 2013-05-23 | Coumba Ndoye | Multiple exposure with image reversal in a single photoresist layer |
| US20140065556A1 (en) * | 2012-08-29 | 2014-03-06 | Tomoya Oori | Patterning method |
| US20160081187A1 (en) * | 2014-08-19 | 2016-03-17 | International Business Machines Corporation | Circuit board formation using organic substrates |
-
2017
- 2017-06-08 CN CN201710426474.6A patent/CN109037038A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1393906A (en) * | 2001-06-26 | 2003-01-29 | 联华电子股份有限公司 | Process for preparing lower storage junctions of DRAM |
| US20100112463A1 (en) * | 2008-11-03 | 2010-05-06 | Hynix Semiconductor Inc. | Method for forming fine contact hole pattern of semiconductor device |
| US20130129991A1 (en) * | 2010-08-09 | 2013-05-23 | Coumba Ndoye | Multiple exposure with image reversal in a single photoresist layer |
| US20140065556A1 (en) * | 2012-08-29 | 2014-03-06 | Tomoya Oori | Patterning method |
| US20160081187A1 (en) * | 2014-08-19 | 2016-03-17 | International Business Machines Corporation | Circuit board formation using organic substrates |
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