JP2013258186A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of forming contact holes at an interval of 2F with stability even when miniaturization progresses.SOLUTION: A method of manufacturing a semiconductor device includes the following steps of: forming a first mask film on a processed layer; patterning the first mask film to form a plurality of first masks arranged at a substantially regular interval in two directions orthogonal to each other; forming a second mask film covering the first mask films and the exposed processed layer; removing a part of the second mask film to form a plurality of sidewalls surrounding respectively the circumferences of the plurality of first masks and mutually coupled in the two directions orthogonal to each other; removing the first mask; and forming holes to the processed layer by using the sidewalls as a processing mask.

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a contact hole.

  A DRAM (Dynamic Random Access Memory), which is one of semiconductor devices, includes a multi-cell transistor arrayed on a semiconductor substrate and a cell capacitor formed on the upper layer side.

  For electrical connection between the source / drain of each cell transistor and the cell capacitor or bit line, a contact plug or the like penetrating the interlayer insulating film is used. As a result of miniaturization and high integration of semiconductor devices, these contact plugs are arranged at a pitch of 2F (F: minimum processing dimension) (see, for example, Patent Document 1).

JP 2007-287794 A

  The contact plug is formed by forming a contact hole in the interlayer insulating film and embedding a conductive material such as polysilicon in the hole. The contact hole is formed by using a photolithographic technique including an exposure using a reticle having a mask pattern corresponding to the contact hole pattern and an etching technique.

  As the semiconductor device manufacturing technology advances, the minimum processing dimension F has been reduced. As a result, it has become difficult to form contact holes at a 2F pitch. That is, the related semiconductor device manufacturing method has a problem that the contact hole cannot be formed stably and the yield is low.

  In a method for manufacturing a semiconductor device according to an embodiment of the present invention, a first mask film is formed on a layer to be processed, the first mask film is patterned, and substantially along two orthogonal directions. A plurality of first masks arranged at regular intervals are formed, a second mask film covering the first mask film and the exposed layer to be processed is formed, and a part of the second mask film is formed Forming a plurality of sidewalls surrounding each of the plurality of first masks and interconnected with respect to the two orthogonal directions; removing the first mask; and A hole is formed in the layer to be processed using a wall as a processing mask.

  According to the present invention, holes are formed using sidewalls formed using a plurality of first masks arranged at equal intervals along two orthogonal directions as processing masks. Holes can be formed in both the inner and outer regions. Thereby, it is possible to form an array of holes at a pitch smaller than the pitch of the reticle pattern.

1 is a diagram showing a planar layout of a part of a semiconductor device according to a first embodiment of the present invention. It is the X1-X1 sectional view taken on the line of FIG. It is the Y1-Y1 sectional view taken on the line of FIG. It is a top view which shows schematic structure of the photomask used for manufacture of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a figure for demonstrating the formation position of the cell contact hole formed by the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and a cross-sectional view at a position corresponding to a line X1-X1 in FIG. 1; FIG. 5B is a diagram for explaining the same step as FIG. 5A and is a cross-sectional view at a position corresponding to the Y1-Y1 line in FIG. 1. FIG. 6 is a diagram for explaining a process following the process illustrated in FIG. 5A and FIG. 5B, and is a cross-sectional view at a position corresponding to the X1-X1 line in FIG. 1. FIG. 6B is a diagram for explaining the same step as FIG. 6A and is a cross-sectional view at a position corresponding to the Y1-Y1 line in FIG. 1. FIG. 6 is a diagram for explaining a process following the process illustrated in FIG. 6A and FIG. 6B, and is a cross-sectional view at a position corresponding to the X1-X1 line in FIG. 1. It is a figure for demonstrating the process same as FIG. 7A, Comprising: It is sectional drawing in the position corresponding to the Y1-Y1 line | wire of FIG. FIG. 8 is a diagram for explaining a process following the process illustrated in FIG. 7A and FIG. 7B, and is a cross-sectional view at a position corresponding to a line X 1 -X 1 in FIG. 1. It is a figure for demonstrating the process same as FIG. 7A, Comprising: It is sectional drawing in the position corresponding to the Y1-Y1 line | wire of FIG. It is a figure for demonstrating the process following the process shown to FIG. 8A and 8B, Comprising: It is sectional drawing in the position corresponding to the X1-X1 line | wire of FIG. It is a figure for demonstrating the process same as FIG. 8A, Comprising: It is sectional drawing in the position corresponding to the Y1-Y1 line | wire of FIG. FIG. 9 is a view for explaining a step following the step shown in FIG. 9A and FIG. 9B, and is a cross-sectional view at a position corresponding to the X1-X1 line in FIG. 1. FIG. 10B is a diagram for explaining the same step as FIG. 10A and is a cross-sectional view at a position corresponding to the Y1-Y1 line in FIG. 1. FIG. 10 is a diagram for explaining a step following the step shown in FIG. 10A and FIG. 10B, and a cross-sectional view at a position corresponding to the X1-X1 line in FIG. 1. FIG. 11B is a diagram for explaining the same step as FIG. 11A and is a cross-sectional view at a position corresponding to a Y1-Y1 line in FIG. 1. FIG. 12 is a diagram for explaining a process following the process illustrated in FIG. 11A and FIG. 11B, and a cross-sectional view at a position corresponding to the X1-X1 line in FIG. 1. FIG. 12B is a diagram for explaining the same step as FIG. 12A, and is a cross-sectional view at a position corresponding to the Y1-Y1 line in FIG. 1. FIG. 12 is a diagram for explaining a process following the process illustrated in FIGS. 12A and 12B, and is a cross-sectional view at a position corresponding to the X1-X1 line in FIG. 1. FIG. 13C is a diagram for explaining the same step as FIG. 13A and is a cross-sectional view at a position corresponding to a Y1-Y1 line in FIG. 1.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Here, a DRAM (Dynamic Random Access Memory) is exemplified as the semiconductor device, but the present invention is not limited to this and can be applied to various semiconductor devices.

  FIG. 1 is a diagram showing a planar layout of a part of the semiconductor device 100 according to the first embodiment of the present invention.

  Referring to FIG. 1, a part of the memory cell region of the semiconductor device 100 is shown. In the memory cell region, a plurality of active regions 13 are defined by forming element isolation regions 12 in a semiconductor substrate (1 in FIG. 2). The plurality of active regions 13 each have an oval shape that is long in the X direction, and are arranged at equal intervals and equal pitches in the X direction and the Y direction, respectively. Although FIG. 1 shows a total of eight active regions 13 in 4 rows and 2 columns, in reality, more active regions (for example, several thousand to several hundred thousand or more) are arranged.

  Of the two active regions 13 arranged in the Y direction in FIG. 1, the active region 13 belonging to the left column is referred to as a first active region 13a, and the active region 13 belonging to the right column is referred to as a second active region 13b. There is. The element isolation region 12 located on the left side of the first active region 13a is the first element isolation region 12a, and the element isolation region 12 located between the first active region 13a and the second active region 13b is the second element isolation. The element isolation region 12 located on the right side of the region 12b and the second element isolation region 12b may be referred to as a third element isolation region 12c. The element isolation region 12 is configured by embedding an element isolation insulating film in a groove formed in a semiconductor substrate.

  Further, in the memory area shown in FIG. 1, a plurality of word lines 10 extending in the Y direction are arranged at equal intervals and equal pitches in the X direction. The word line 10 includes a (real) word line WL also serving as a gate electrode of a cell transistor formed in the active region 13 and a dummy word line DWL formed on the element isolation region 12.

  The two word lines WL formed so as to straddle the plurality of first active regions 13a may be referred to as a first word line WL10a and a second word line WL10b from the left. Further, the two word lines WL formed so as to straddle the plurality of second active regions 13a may be referred to as a third word line WL10c and a fourth word line WL10d from the left. Furthermore, the dummy word line DWL located between the first active region 13a and the second active region 13b may be referred to as a first dummy word line DWL10a.

  A region on the surface side of each active region 13 is divided into three cell contact regions 25 by two word lines 10. Cell contact hole formation positions Hp are set at equal intervals and equal pitches so as to correspond to the cell contact regions 25, respectively. Here, the cell contact hole formation position Hp is set so that one exists at a pitch = 2F, where F is the minimum processing dimension.

  A pair of transistors sharing one of the source / drain regions is formed in each active region 13. Three cell contact regions 25 formed in each active region 13 correspond to the source / drain regions of the pair of transistors. The cell contact hole is used to form a contact plug connected to these source / drain regions.

  From the left of the figure, the cell contact region 25 through which the X1-X1 line passes is the first cell contact region 25a1, the second cell contact region 25a2, the third cell contact region 25a3, the fourth cell contact region 25a4, and the fifth cell contact region. 25a5 and sixth cell contact region 25a6.

  A pair of transistors formed in the first active region 13a through which the X1-X1 line passes are referred to as a first transistor Tr1 and a second transistor Tr2 from the left in the drawing, and a pair of transistors formed in the second active region 13b From the left of the figure, they may be referred to as a third transistor Tr3 and a fourth transistor Tr4.

  In the memory region of FIG. 1, a bit line 29 is meandered so as to pass over the cell contact region 25 at the center of the plurality of active regions 13 arranged in the X direction.

  Next, the structure of the semiconductor device 100 will be described with reference to FIGS. 2A and 2B. 2A is a cross-sectional view taken along line X1-X1 in FIG. 1, and FIG. 2B is a cross-sectional view taken along line Y1-Y1 in FIG.

  As described above, the element isolation region 12 (12a, 12b, 12c) is formed in the semiconductor substrate 1 to define the active region 13 (13a, 13b).

  In each active region 13, a word line trench 5 that also serves as a gate electrode of the transistor is formed so as to extend along the Y direction. The inner surface of the trench 5 is covered with a gate insulating film 6, and a conductive material that becomes a part of the word line 10 (WL10a, WL10b, WL10c, WL10d) is embedded inside the trench 5. A metal film or the like is laminated on the upper portion to constitute the word line 10 (WL10a, WL10b, WL10c, WL10d) extending in the Y direction. A first dummy word line DWL10a is provided between the second word line WL10b and the third word line WL10c.

  The semiconductor pillar located on the left side of the first word line WL10a becomes the first cell contact region 25a1, and a stacked diffusion layer 14a serving as one of the source / drain of the first transistor Tr1 is provided on the upper surface thereof. The semiconductor pillar located between the first word line WL10a and the second word line WL10b becomes the second cell contact region 25a2, and a stacked diffusion layer 14b serving as the other of the source / drain of the first transistor Tr1 is provided on the upper surface thereof. ing. The semiconductor pillar located on the right side of the second word line WL10b becomes the third cell contact region 25a3, and a stacked diffusion layer 14c serving as one of the source / drain of the second transistor Tr2 is provided on the upper surface thereof. The stacked diffusion layer 14b provided on the upper surface of the second cell contact region 25a2 also serves as the other of the source / drain of the second transistor Tr2.

  Similarly, the semiconductor pillar located on the left side of the third word line WL10c becomes the fourth cell contact region 25a4, and a stacked diffusion layer 14d serving as one of the source / drain of the third transistor Tr3 is provided on the upper surface thereof. The semiconductor pillar located between the third word line WL10c and the fourth word line WL10d becomes the fifth cell contact region 25a5, and a stacked diffusion layer 14e serving as the other of the source / drain of the third transistor Tr3 is provided on the upper surface thereof. ing. Further, the semiconductor pillar located on the right side of the fourth word line WL10b becomes the sixth cell contact region 25a6, and a stacked diffusion layer 14f serving as one of the source / drain of the fourth transistor Tr4 is provided on the upper surface thereof. Note that the stacked diffusion layer 14e provided on the upper surface of the fifth cell contact region 25a5 also serves as the other of the source / drain of the fourth transistor Tr4.

  The stacked diffusion layer 14a, the stacked diffusion layer 14b, the gate insulating film 6 positioned therebetween, and the first word line WL10a constitute a part of the first transistor Tr1. Further, the stacked diffusion layer 14b, the stacked diffusion layer 14c, the gate insulating film 6 positioned therebetween, and the second word line WL10b constitute a part of the second transistor Tr2. Furthermore, the stacked diffusion layer 14d, the stacked diffusion layer 14e, the gate insulating film 6 located between them, and the third word line WL10c constitute a part of the third transistor Tr3. The stacked diffusion layer 14e, the stacked diffusion layer 14f, the gate insulating film 6 positioned therebetween, and the fourth word line WL10d constitute a part of the fourth transistor Tr4.

  A liner film 19 is provided so as to cover the upper surface of each word line 10 and dummy word line DWL (not shown in FIG. 2A). A plurality of cell contact holes 25c penetrating the liner film 19 are formed. A cell contact plug 25b is formed in each cell contact hole 25c. The cell contact plug 25 b is connected to the stacked diffusion layer 14 on the corresponding cell contact region 25.

  For example, the first cell contact plug 25b1 formed in the first cell contact hole 25c1 is connected to the first stacked diffusion layer 14a on the first cell contact region 25a1. Similarly, the second, third, fourth, fifth and sixth cells formed in the second, third, fourth, fifth and sixth cell contacts 25c2, 25c3, 25c4, 25c5 and 25c6, respectively. The contact plugs 25b2, 25b3, 25b4, 25b5, and 25b6 are provided on the second, third, fourth, and fifth cell contact regions 25a2, 25a3, 25a4, 25a5, and 25a6, respectively. 4, connected to the fifth and sixth stacked diffusion layers 14b, 14c, 14d, 14e and 14f, respectively.

  A second interlayer insulating film 26 is provided so as to cover the cell contact plug 25b. A plurality of bit contact holes 28 a penetrating through the second interlayer insulating film 26 are formed. Bit contact plugs 28b are formed in the bit contact holes 28a, respectively. The bit contact plugs 28b connect between the corresponding cell contact plugs 25b and the bit lines 29, respectively.

  For example, a first bit contact plug 28b1 is formed in the first bit contact hole 28a1. The second cell contact plug 25b2 and the first bit line 29a are connected via the first bit contact plug 28b1. Similarly, a second bit contact 28a2 is provided, and the fifth cell contact plug 25b5 and the second bit line 29b are connected via the second bit contact plug 28b2.

  A third interlayer insulating film 27 is provided so as to cover the bit line 29. A plurality of capacitive contact holes 30 a are provided through the third interlayer insulating film 27. A capacitor contact plug 30b is formed in each capacitor contact hole 30a. The capacitor contact plug 30 b connects between the corresponding cell contact plug 25 b and the capacitor contact pad 31.

  For example, the first capacitor contact plug 30b1 formed in the first capacitor contact hole 30a1 connects the first cell contact plug 25b1 and the first capacitor contact pad 31a. Similarly, the second, third, and fourth capacitor contact plugs 30b2, 30b3, and 30b4 formed in the second, third, and fourth capacitor contact holes 30a2, 30a3, and 30a4 are third, fourth, and fourth, respectively. The 6-cell contact plugs 25b3, 25b4, and 25b6 are connected to the second, third, and fourth capacitor contact pads 31b, 31c, and 31d, respectively.

  A stopper film 32 is provided around the capacitor contact pad 31. A capacitor lower electrode 33 is provided on the capacitor contact pad 31. The lower electrode 33 has a crown shape. A capacitive insulating film 34 is formed so as to cover the inner surface and the outer peripheral surface of the lower electrode 33. An upper electrode 35 is provided on the capacitive insulating film 34 so as to embed the lower electrode 33, thereby forming a capacitor.

  Next, prior to the description of the manufacturing method of the semiconductor device 100 configured as described above, a cell contact mask (reticle) used for forming a cell contact hole will be described.

  As shown in FIG. 3, the cell contact mask has a checkered pattern of 4F pitch in which cell contact mask translucent portions 41 and cell contact mask light-shielding portions 42 each having a square of 2F are alternately arranged in the X direction and the Y direction. It consists of a pattern layout. When the translucent part 41 and the light shielding part 42 transfer the square mask (reticle) pattern 40 to the resist, the corners of the pattern are rounded due to the diffraction phenomenon of electromagnetic waves (exposure light), and the transfer pattern 43 is shown in FIG. As shown by the broken line in FIG. In other words, it is possible to form circular patterns arranged at substantially equal intervals along directions inclined by 45 degrees in the X direction and the Y direction, respectively, using the mask of FIG.

  FIG. 4 is a diagram showing the arrangement of cell contact holes formed using the cell contact mask of FIG. Corresponding to the transfer pattern 43, a circular cell contact hole pattern 44a is formed. In addition, a cell contact hole pattern 44b having curved four sides is also formed outside of the hatched circular region.

  The formation of these patterns 44a and 44b will be briefly described. First, a hard mask film made of a silicon oxide film (first mask film) is etched using the transfer pattern 43 transferred to the resist as a mask to form a silicon oxide film hard mask (first mask). The formed first masks are arranged at equal intervals along directions inclined 45 degrees in the X and Y directions, respectively. Next, a sidewall made of a silicon nitride film (second mask film) is formed around the formed first mask. The sidewalls are connected to adjacent sidewalls with respect to directions inclined 45 degrees in the X direction and the Y direction, respectively. Next, the first mask is removed. As a result, a sidewall 23a made of a silicon nitride film is formed in the hatched region in FIG. If the underlying layer is etched using the sidewall 23a as a mask (second mask), two cell contact hole patterns 44a and 44b are formed at a pitch of 4F.

  Thus, in the present embodiment, two cell contact hole patterns 44a and 44b can be formed on the 4F pitch using the 4F pitch checkered cell contact reticle pattern 40. That is, cell contacts can be formed at a density higher than the pattern density of the cell contact reticle pattern. Therefore, even if miniaturization advances and it becomes difficult to form one contact hole pattern at a 2F pitch by lithography technology, contact holes can be stably formed, and an improvement in yield can be expected.

  Hereinafter, a method for manufacturing the semiconductor device 100 will be described with reference to FIGS. 5A to 13B and FIGS. 2A and 2B. Here, each A figure is a longitudinal sectional view at a position corresponding to the X1-X1 line in FIG. 1, and each B figure is a longitudinal sectional view at a position corresponding to the Y1-Y1 line in FIG.

  First, as shown in FIGS. 5A and 5B, an element isolation region 12 embedded with an insulating film made of a silicon oxide film is formed in a semiconductor substrate 1 by a well-known STI method. As a result, the active region 13 which is surrounded by the element isolation region 12 and made of the substrate 1 is defined.

  Next, a pad oxide film (not shown) made of a silicon oxide film is formed on the entire surface of the semiconductor substrate 1, and an N well region and a P well region are formed by a known method through the oxide film.

  Then, the semiconductor substrate 1 is etched by a dry etching method to form a groove 5 for word lines. Then, a gate oxide film 6 is formed on the exposed surface of the active region 13 of the semiconductor substrate 1 including the inner surface of the trench 5 by using thermal oxidation and nitridation processes.

  Next, polysilicon 7, tungsten 8 and the like are deposited by, for example, the CVD method and etched back to form word lines WL10a, WL10b, WL10c, WL10d and dummy word lines DWL10a that also serve as gate electrodes. Then, a sidewall 11 is formed by depositing a silicon nitride film or the like so as to cover the word line WL10 and the dummy word line DWL10a and performing etch back.

  Then, a stacked diffusion layer 14 made of single crystal silicon is formed on the exposed upper surface of the semiconductor substrate 1 using a selective epitaxial method.

  Next, as shown in FIGS. 6A and 6B, a liner film 19 made of a silicon nitride film or the like is formed by, for example, a CVD method so as to cover the word line WL10 and the dummy word line DWL10a. Then, a first interlayer insulating film 17 is deposited on the liner film 19. Thereafter, CMP (Chemical Mechanical Polishing) is performed to flatten the surface of the first interlayer insulating film 17 until the liner film 19 is exposed. Then, a cap insulating film 18 is formed on the planarized first interlayer insulating film 17 by, for example, a CVD method.

  Next, as shown in FIGS. 7A and 7B, a stopper film 20 made of a silicon nitride film is formed on the cap insulating film 18. Further, a hard mask film (21) made of a silicon oxide film is formed on the stopper film 20, and a resist (22) is applied on the hard mask film. Then, using the cell contact mask (see FIG. 3) described above, the contact reticle pattern 40 is transferred to the resist to form the pattern-transferred resist 22. Further, using a dry etching technique, the hard mask film is etched using the resist 22 as a mask to form a pattern-transferred hard mask (first mask) 21. As described above, the hard masks 21 are arranged at predetermined intervals along a direction orthogonal to each other.

  Next, as shown in FIGS. 8A and 8B, the resist 22 is removed, and a sidewall film 23 made of a silicon nitride film is formed with a film thickness of about F / 4 nm, for example. As shown in FIG. 4, the film thickness is set so that adjacent protruding portions are connected to each other, but the region surrounded by the protruding portions is not completely embedded.

  Next, as shown in FIGS. 9A and 9B, the sidewall film 23 made of a silicon nitride film is etched back to form a sidewall 23a. At this time, the width of the sidewall 23a is about F / 4 which is the same as the film thickness.

  Next, as shown in FIGS. 10A and 10B, the hard mask 21 is immersed in a hydrofluoric acid solution and removed, for example. Subsequently, in order to remove the exposed portion of the stopper film 20, the sidewalls 23a of the silicon nitride film and the stopper film 20 are etched back. Finally, a part of the side wall 23a and the stopper film 20 covered therewith remain, and become a hard mask 24 for cell contact etching.

  Next, as shown in FIGS. 11A and 11B, the cap insulating film 18, the first interlayer insulating film 17, and the liner film 19 are penetrated by using a dry etching technique with the cell contact etching hard mask 24 as a mask. A cell contact hole 25c is formed. The surface of the stacked diffusion layer 14 is exposed at a portion where the cell contact 25c and the active region 13 intersect.

  Next, as shown in FIGS. 12A and 12B, polysilicon 25 doped with an N-type impurity (phosphorus or the like) is embedded in the cell contact 25c by using, for example, a CVD method.

  Next, as shown in FIGS. 13A and 13B, the excess polysilicon 25 on the first interlayer insulating film 17 is removed by, for example, CMP, and the polysilicon 25 is etched back. A part of the polysilicon 25 is left in the cell contact 25c to form a cell contact plug 25b.

  Next, as shown in FIGS. 2A and 2B, a second interlayer insulating film 26 is formed so as to cover the cell contact plug 25b. Then, a bit contact hole 28a penetrating the second interlayer insulating film 26 is formed, and the inside is filled with polysilicon or the like to form a bit contact plug 28b. As a result, the second cell contact plug 25b2 and the first bit line 29a are connected via the first bit contact plug 28b1. The fifth cell contact plug 25b5 and the second bit line 29b are connected through the second bit contact plug 28b2.

  Next, a third interlayer insulating film 27 is formed so as to cover the bit line 29. Then, a capacitor contact hole 30a penetrating the third interlayer insulating film 27 is formed, and a conductive material such as polysilicon is buried therein, thereby forming a capacitor contact plug 30b. As a result, the first cell contact plug 25b1 and the first capacitor contact pad 31a are connected via the first capacitor contact plug 30b1. Similarly, the third, fourth, and sixth cell contact plugs 25b3, 25b4, and 25b6 and the second, third, and fourth capacitors are connected via the second, third, and fourth capacitor contact plugs 30b2, 30b3, and 30b4. Contact pads 31b, 31c, and 31d are connected to each other.

  Next, a stopper film 32 is formed so as to cover the capacitor contact pad 31. The capacitor contact pad 31 is exposed, and the lower electrode 33 is formed thereon. After forming the capacitor insulating film 34 covering the inner surface and the outer peripheral surface of the lower electrode 33, the upper electrode 35 is formed on the capacitor insulating film 35 to form a capacitor.

  Thereafter, a multilayer wiring is formed by repeating a wiring formation process for forming a necessary wiring, a plug formation process for forming a plug connected to the wiring, and the like.

  As described above, the semiconductor device 100 is completed.

  As described above, in the method of manufacturing a semiconductor device according to the present embodiment, a 4F pitch checkered contact reticle pattern is used, and the hard mask 24 using the sidewalls 23 is used. A contact hole pattern can be formed. Even if miniaturization advances and it becomes difficult to form one contact hole pattern at a 2F pitch by lithography technology, contact holes can be formed stably, and an improvement in yield can be expected.

  Although the present invention has been described with reference to the embodiment, the present invention is not limited to the above embodiment, and various modifications and changes can be made without departing from the gist of the present invention.

  For example, in the above embodiment, the checkered cell contact mask is used, but the same applies even if a cell contact mask having a light shielding portion such as a circle arranged at a predetermined distance along a direction orthogonal to each other is used. Pattern transfer can be performed.

DESCRIPTION OF SYMBOLS 100 Semiconductor device 1 Semiconductor substrate 5 Groove 6 Gate insulating film 7 Polysilicon 8 Tungsten 10 Word line 11 Side wall 12 Element isolation region 12a First element isolation region 12b Second element isolation region 12c Third element isolation region 13 Active region 13a First 1 active region 13b second active region 14, 14a to 14f stacked diffusion layer 17 first interlayer film 18 cap insulating film 19 liner film 20 stopper film 21 hard mask 22 resist 23 sidewall film 23a sidewall 24 hard mask 25 cell contact region 25a1 to 25a6 cell contact region 25b1 to 25b6 cell contact plug 25c cell contact hole 26 second interlayer insulating film 27 third interlayer insulating film 28a1, 28a2 bit contact hole 28b1, 2 8b2 Bit contact plug 29a, 29b Bit line 30a1-30a4 Capacitance contact hole 30b1-30b4 Capacitance contact plug 31a-31d Capacitance contact pad 32 Stopper film 33 Lower electrode 34 Capacitance insulating film 35 Upper electrode 40 Mask pattern 41 Cell contact mask light transmitting part 42 Cell contact mask shading part 43 Transfer pattern 44a, 44b Cell contact hole pattern

Claims (6)

Forming a first mask film on the layer to be processed;
Patterning the first mask film to form a plurality of first masks arranged at substantially equal intervals along two orthogonal directions;
Forming a second mask film covering the first mask and the exposed layer to be processed;
Removing a part of the second mask film to form a plurality of sidewalls surrounding each of the plurality of first masks and interconnected with respect to the two orthogonal directions;
Removing the first mask;
Forming a hole in the layer to be processed using the sidewall as a processing mask;
A method for manufacturing a semiconductor device.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the hole is formed in a region inside each of the plurality of sidewalls and a region outside each of the plurality of sidewalls.   The checkerboard mask pattern is used for patterning of the first mask film, and the planar shape of the first mask is made close to a circle by utilizing a diffraction phenomenon of exposure light. 3. A method for manufacturing a semiconductor device according to 2.   4. The method of manufacturing a semiconductor device according to claim 3, wherein when the minimum processing dimension is F, a pattern repetition period of the checkered mask pattern is represented by 4F.   The method of manufacturing a semiconductor device according to claim 4, wherein an interval between the center positions of the holes is represented by 2F.   2. The processed layer includes an interlayer insulating film covering a transistor formed on a semiconductor substrate, and the hole is a contact hole reaching a source / drain region constituting the transistor. 6. A method for manufacturing a semiconductor device according to any one of 5 above.

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