CN109036321A - Display panel - Google Patents
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- CN109036321A CN109036321A CN201811121689.8A CN201811121689A CN109036321A CN 109036321 A CN109036321 A CN 109036321A CN 201811121689 A CN201811121689 A CN 201811121689A CN 109036321 A CN109036321 A CN 109036321A
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- 239000011159 matrix material Substances 0.000 claims abstract description 13
- 239000004973 liquid crystal related substance Substances 0.000 claims description 47
- 230000000875 corresponding effect Effects 0.000 claims description 8
- 230000005611 electricity Effects 0.000 claims description 6
- 230000008878 coupling Effects 0.000 claims description 5
- 238000010168 coupling process Methods 0.000 claims description 5
- 238000005859 coupling reaction Methods 0.000 claims description 5
- 230000009514 concussion Effects 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 230000002596 correlated effect Effects 0.000 claims description 3
- 101100006548 Mus musculus Clcn2 gene Proteins 0.000 description 11
- 101100006558 Mus musculus Clcn4 gene Proteins 0.000 description 11
- 101100006553 Mus musculus Clcn3 gene Proteins 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000006698 induction Effects 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000008771 sex reversal Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
A display panel includes a plurality of pixel matrices and a plurality of receiving circuits. Each pixel matrix comprises a plurality of first pixel circuits and a plurality of second pixel circuits. The plurality of first pixel circuits and the plurality of second pixel circuits are coupled to a first node. The receiving circuits are used for receiving a plurality of input signals and correspondingly outputting a plurality of data signals to a plurality of pixel matrixes according to the input signals. One of the receiving circuits outputs a first data signal to the first node, and the first data signal has an oscillating waveform. When the first data signal is less than or equal to a first preset voltage value and greater than or equal to a second preset voltage value, one of the plurality of first pixel circuits receives the first data signal. When the first data signal is larger than the first preset voltage value, one of the second pixel circuits receives the first data signal.
Description
Technical field
The present invention is in relation to a kind of display panel, espespecially a kind of display panel of wirelessly transmitting data signal.
Background technique
Large scale display panel is one of the design mainstream of display panel now.However, as panel size increases, panel
The impedance of internal cabling also increases with it, and then the problem of will cause distorted signals.In order to overcome foregoing problems, industry is by face
The active region of plate is divided into comprising several regions, and a receiving coil is placed in each region.In this way, in panel
All coils can receive data-signal simultaneously by way of wireless transmission, to update the display in aforementioned several regions simultaneously
Picture.
However, the data signal strength that receiving coil is induced is limited to its size.If the area of induction coil
It is too small, pixel circuit can not be charged to expected voltage level because data signal strength is insufficient.And if by the line of induction
The area of circle increases, and will increase the corresponding pixel circuit quantity of induction coil, has compressed the distribution of each pixel circuit instead
The Data writing time arrived, and then pixel circuit can not equally be charged to expected voltage level.
Summary of the invention
In view of this, how to provide the display panel with enough Data writing times, actually industry has to be solved ask
Topic.
The present invention provides a kind of display panel.Display panel includes multiple picture element matrixs and multiple reception circuits.Each picture
Prime matrix includes multiple first pixel circuits and multiple second pixel circuits.Plurality of first pixel circuit and multiple second
Pixel circuit is coupled to a first node.Multiple reception circuits are used to receive multiple input signals, and according to multiple input signals
It is corresponding to export multiple data-signals to multiple picture element matrixs.Wherein, multiple one of them for receiving circuit export one first data
Signal is to first node, and the first data-signal has a concussion waveform.When the first data-signal is less than or equal to one first in advance
If voltage value and when being greater than or equal to second preset voltage value, the one of them of multiple first pixel circuits receives the first data
Signal.When the first data-signal is greater than the first preset voltage value, the one of them of multiple second pixel circuits receives the first number
It is believed that number.
Each first pixel circuit and each second pixel circuit can be charged to expected electricity by above-mentioned display panel
Voltage level.
Below in conjunction with the drawings and specific embodiments, the present invention will be described in detail, but not as a limitation of the invention.
Detailed description of the invention
Fig. 1 is the simplified functional block diagram of display panel according to one embodiment of the invention.
Fig. 2 is the circuit diagram of the picture element matrix of Fig. 1.
Fig. 3 is the simplified timing variations figure of portion's dividing control signal of an operation embodiment of the display panel of Fig. 1.
Fig. 4 (a)~4 (d) is the part schematic equivalent circuit of picture element matrix.
Fig. 5 is the first sub-data signals, the second sub-data signals and the simplified timing variations figure of third sub-data signals.
Fig. 6 (a)~6 (b) is the simplified timing variations of data-signal of an operation embodiment of the display panel of Fig. 1
Figure.
Wherein, appended drawing reference:
100: display panel
110: picture element matrix
120: receiving circuit
210 [1]~210 [n]: the first pixel circuit
220 [1]~220 [n]: the second pixel circuit
230: mode switching circuit
212: the first rectification circuits
214: the first gray scale control circuits
216: the first reset circuits
222: the second rectification circuits
224: the second gray scale control circuits
226: the second reset circuits
GL, GL [1]~GL [M]: gate line
T1~T9: the first transistor~the 9th transistor
Tr: reset transistor
Tw: writing transistor
N1~N3: first node~third node
Clc1~Clc4: the first liquid crystal capacitance~the 4th liquid crystal capacitance
Vdata: data-signal
Vr: reset voltage
Vref1~Vref2: the first reference voltage~the second reference voltage
CT1~CT7: first control signal~the 7th control signal
CTr: reset control signal
CTw: write control signal
Tr1~Tr2: the first reset phase~the second reset phase
Tw1~Tw2: the first write phase~the second write phase
T1~T4: first time length~the 4th time span
Sdata1~Sdata3: the first sub-data signals~third sub-data signals
Specific embodiment
Structural principle and working principle of the invention are described in detail with reference to the accompanying drawing:
Fig. 1 is the simplified functional block diagram of display panel 100 according to one embodiment of the invention.Display panel 100 wraps
Containing multiple picture element matrixs 110, multiple reception circuits 120 and multiple gate line GL.The corresponding coupling of each picture element matrix 110
In a reception circuit 120, and the part of grid pole signal wire GL being coupled in multiple gate line GL.Multiple reception circuits
120 in a manner of wireless transmission for receiving multiple input signals, and according to the multiple data letters of the corresponding output of multiple input signals
Number Vdata is to multiple picture element matrixs 110.Other elements and connection to make simplified form and ease of explanation, in display panel 100
Relationship is not illustrated in Fig. 1.
Fig. 2 is the circuit diagram of the picture element matrix 110 of Fig. 1.Picture element matrix 110 includes multiple first pixel circuits 210
[1]~210 [n], multiple second pixel circuit 220 [1]~220 [n] and mode switching circuit 230, wherein n is positive integer.The
One pixel circuit 210 [1]~210 [n] and the second pixel circuit 220 [1]~220 [n] are all coupled to first node N1.Wherein
One pixel circuit 210 [1]~210 [n], the second pixel circuit 220 [1]~220 [n] and mode switching circuit 230 are coupled to
One node N1.
A reception circuit 120 corresponding to picture element matrix 110 is coupled to mode switching circuit 230, and receives circuit 120
For providing the data-signal Vdata of form of communication to mode switching circuit 230.Also that is, data-signal Vdata have shake back and forth
The waveform swung.
In addition, the picture element matrix 110 of Fig. 2 is further coupled to the part of grid pole signal wire in a plurality of gate line GL of Fig. 1
GL.For convenience of explanation, the part of grid pole signal wire GL that the picture element matrix 110 of Fig. 2 is coupled, referred to as gate line GL [1]
~GL [M], wherein M is positive integer.
Element number used in description of the invention and attached drawing and device number in index [1]~[n] and [1]~
[M] is intended merely to facilitate the other element of denotion and device, it is specific to be not intended that the quantity by aforementioned components and device is confined to
Number.In description of the invention and attached drawing, if not indicating the element number when using a certain element number or device number
Or the index of device number, then it is not special in element group belonging to denotion or device group for representing the element number or device number
Fixed any element or device.For example, the object that element number 210 [2] is censured is the first pixel circuit 210 [2], and element is compiled
Numbers 210 objects censured are then not specific any first pixel circuits 210 in the first pixel circuit 210 [1]~210 [n].
By taking the first pixel circuit 210 [1] as an example, the first pixel circuit 210 [1] includes first the 212, first ash of rectification circuit
Rank control circuit 214 and the first reset circuit 216.First rectification circuit 212 be coupled to first node N1 and second node N2 it
Between.When receive circuit 120 generate data-signal Vdata be less than or equal to the first preset voltage value (for example, 0V) and be greater than or
When equal to second preset voltage value (for example, -10V), first node N1 and second node N2 can be connected in the first rectification circuit 212.
In other words, when data-signal Vdata is greater than the first preset voltage value or less than the second preset voltage value, first is whole
Current circuit 212 will disconnect first node N1 and second node N2.
First gray scale control circuit 214 is coupled to second node N2, for receiving data-signal from second node N2
Vdata, and for determining grayscale value shown by the first pixel circuit 210 [1] according to data-signal Vdata.First resetting electricity
Road 216 is also coupled in second node N2, and when first node N1 and second node N2 is disconnected, the first reset circuit 216 can be incited somebody to action
First reference voltage Vref 1 is transferred to second node N2, to reset the first gray scale control circuit 214.
By taking the second pixel circuit 220 [1] as an example, the second pixel circuit 220 [1] includes second the 222, second ash of rectification circuit
Rank control circuit 22 and the second reset circuit 226.Second rectification circuit 222 be coupled to first node N1 and third node N3 it
Between.When data-signal Vdata is greater than the first preset voltage value, first node N1 and third can be connected in the second rectification circuit 222
Node N3.
In other words, when data-signal Vdata is less than or equal to the first preset voltage value, the second rectification circuit 222 can break
Open first node N1 and third node N3.
Second gray scale control circuit 224 is coupled to third node N3, for receiving data-signal from third node N3
Vdata, and for determining grayscale value shown by the second pixel circuit 220 [1] according to data-signal Vdata.Second resetting electricity
Road 226 is also coupled in third node N3, and when first node N1 and third node N3 is disconnected, the second reset circuit 226 can be incited somebody to action
Second reference voltage Vref 2 is transferred to third node N3, to reset the second gray scale control circuit 224.
In other words, if data-signal Vdata is in negative half-cycle, and the voltage level of data-signal Vdata is between first
Between preset voltage value and the second preset voltage value, then the first pixel circuit 210 [1] can receive data-signal Vdata, but second
Pixel circuit 220 [1] will not receive data-signal Vdata.
On the other hand, if data-signal Vdata is in positive half period, and the voltage level of data-signal Vdata is greater than the
One preset voltage value, then the second pixel circuit 220 [1] can receive data-signal Vdata, but the first pixel circuit 210 [1] will not
Receive data-signal Vdata.
It can be seen from the above, display panel 100 takes full advantage of the data-signal Vdata of positive half period and negative half-cycle to
One pixel circuit 210 [1] and the second pixel circuit 220 [1] carry out data write-in, without only utilizing positive half period or negative half period
The data-signal Vdata of phase carries out data write-in.Therefore, the first pixel circuit 210 [1] and the second pixel circuit 220 [1] all may be used
It is assigned to sufficient Data writing time.
Specifically, the first rectification circuit 212 of the first pixel circuit 210 [1] includes the first transistor T1, the second crystal
Pipe T2.The first transistor T1 includes first end, second end and control terminal, and wherein the first end of the first transistor T1 is coupled to first
Node N1.Second transistor T2 includes first end, second end, the first control terminal and the second control terminal, wherein second transistor T2
First end and the second control terminal be coupled to the control terminal and second end of the first transistor T1, the second end of second transistor T2 and
First control terminal is coupled to second node N2.
First gray scale control circuit 214 includes third transistor T3, the 4th transistor T4, the first liquid crystal capacitance Clc1 and the
Two liquid crystal capacitance Clc2.Third transistor T3 includes first end, second end and control terminal, and the first end of third transistor T3 couples
In second node N2, the control terminal of third transistor T3 is used to receive first control signal CT1 from gate line GL [1], the
The second end of three transistor T3 is then coupled to the first liquid crystal capacitance Clc1.4th transistor T4 includes first end, second end and control
End processed, the first end of the 4th transistor T4 are coupled to second node N2, and the control terminal of the 4th transistor T4 is used for from grid signal
Line GL [2] receives second control signal CT2, and the second end of the 4th transistor T4 is then coupled to the second liquid crystal capacitance Clc2.
First reset circuit 216 includes the 5th transistor T5.5th transistor T5 includes first end, second end and control
End.The first end of 5th transistor T5 is coupled to second node N2, and the control terminal of the 5th transistor T5 is used for from gate line
GL [3] receives third and controls signal CT3, and the second end of the 5th transistor T5 is for receiving the first reference voltage Vref 1.
Second rectification circuit 222 of the second pixel circuit 220 [1] includes the 6th transistor T6.6th transistor T6 includes
First end, second end and control terminal, wherein the first end of the 6th transistor T6 is coupled to third node N3, the 6th transistor T6's
Second end and control terminal are all coupled to first node N1.
Second gray scale control circuit 224 includes the 7th transistor T7, the 8th transistor T8, third liquid crystal capacitance Clc3 and the
Four liquid crystal capacitance Clc4.7th transistor T7 includes first end, second end and control terminal, and the first end of the 7th transistor T7 couples
In third node N3, the control terminal of the 7th transistor T7 is used to receive first control signal CT1 from gate line GL [1], the
The second end of seven transistor T7 is then coupled to third liquid crystal capacitance Clc3.8th transistor T8 includes first end, second end and control
End processed, the first end of the 8th transistor T8 are coupled to third node N3, and the control terminal of the 8th transistor T8 is used for from grid signal
Line GL [2] receives second control signal CT2, and the second end of the 8th transistor T8 is then coupled to the 4th liquid crystal capacitance Clc4.
Second reset circuit 226 includes the 9th transistor T9.9th transistor T9 includes first end, second end and control
End, wherein the first end of the 9th transistor T9 is coupled to third node N3, the control terminal of the 9th transistor T9 is used to believe from grid
Number line GL [3] receives third and controls signal CT3, and the second end of the 9th transistor T9 is coupled to the second reference voltage Vref 2.
In addition, the first pixel circuit 210 [2] and the second pixel circuit 220 [2] are coupled to third gate line GL
[3], the 4th gate line GL [4] and the 5th gate line GL [5], and respectively by third gate line GL [3], the 4th
Gate line GL [4] and the 5th gate line GL [5] receives third control signal CT3, the 4th control signal CT4 and the 5th
Control signal CT5.First pixel circuit 210 [3] and the second pixel circuit 220 [3] are coupled to the 5th gate line GL
[5], the 6th gate line GL [6] and the 7th gate line GL [7], and respectively by the 5th gate line GL [5], the 6th
Gate line GL [6] and the 7th gate line GL [7] receives the 5th control signal CT5, the 6th control signal CT6 and the 7th
Control signal CT7, and so on.
In addition, the first pixel circuit 210 [2]~210 [n] and the second pixel circuit 220 [2]~220 [n] are included
Element and connection type are similar to the first pixel circuit 210 [1] and the second pixel circuit 220 [1] respectively, rise to be succinct
See, does not repeat to repeat herein.
Mode switching circuit 230 includes reset transistor Tr and writing transistor Tw.Reset transistor Tr include first end,
Second end and control terminal, the first end of reset transistor Tr is for receiving reset voltage Vr, the second end coupling of reset transistor Tr
It is connected to first node N1, the control terminal of reset transistor Tr is for receiving reset control signal CTr.Writing transistor Tw includes the
One end, second end and control terminal, the first end of writing transistor Tw are used to write from the reception data-signal Vdata of circuit 120 is received
The second end for entering transistor Tw is coupled to first node N1, and the control terminal of writing transistor Tw is for receiving write control signal
CTw。
Mode switching circuit 230 is used for selectively outputting data signals Vdata or reset voltage Vr to first node N1,
To carry out data write-in or electricity to the first pixel circuit 210 [1]~210 [n] and the second pixel circuit 220 [1]~220 [n]
Ballast is set.The detailed mode of operation of mode switching circuit 230 will further illustrate in subsequent paragraph.
In implementation, the transistor T4 of the first transistor T1~the 4th, the 6th transistor T9 of transistor T6~the 9th, resetting crystal
Pipe Tr and writing transistor Tw can be realized with various suitable N-type transistors.5th transistor T5 can use bigrid
(dual-gate) N-type transistor is realized.
Fig. 3 is the simplified timing variations figure of portion's dividing control signal of an operation embodiment of the display panel 100 of Fig. 1.
The mode of operation of display panel 100 is further illustrated by Fig. 3 is arranged in pairs or groups with Fig. 2 below.In the first reset phase Tr1, write-in
Control signal CTw and second control signal CT2 is in forbidden energy level (for example, low voltage level), and reset control signal CTr,
First control signal CT1 and third control signal CT3 are in enable level (for example, high-voltage level).Therefore, reset transistor
Tr, third transistor T3, the 5th transistor T5, the 7th transistor T7 and the 9th transistor T9 are in the conductive state, and are written
Transistor Tw, the 4th transistor T4 and the 8th transistor T8 are in an off state.
At this point, the reset voltage Vr (for example, -20V) with lower voltage level can be transferred to first node N1, so that the
One transistor T1 is in the conductive state, and the 6th transistor T6 is in an off state.
Reset voltage Vr can be further transferred to the second control terminal of second transistor T2 by the first transistor T1.By double
The characteristic of grid N-type transistor is it is found that the critical voltage (threshold voltage) of second transistor T2 can be with the second crystal
The voltage swing that the second control terminal of pipe T2 receives presents negatively correlated.
For example, when the voltage of the second control terminal of second transistor T2 is -10V, critical voltage 10V.When second
When the voltage of the second control terminal of transistor T2 is -15V, critical voltage 20V.When the second control terminal of second transistor T2
Voltage be -20V when, critical voltage 35V.Therefore, apply sufficiently low electricity in the second control terminal of second transistor T2
Voltage level, can be so that the 5th transistor T5 be in an off state.
In the present embodiment, reset voltage Vr is low enough so that second transistor T2 is in an off state.Therefore, in first
In reset phase Tr1, the first pixel circuit 210 [1], the second pixel circuit 220 [1] and mode switching circuit 230 will form Fig. 4
(a) equivalent circuit.As shown in Fig. 4 (a), the first reference voltage Vref 1 can pass through the 5th transistor T5 and third transistor T3
It is transferred to the first liquid crystal capacitance Clc1, the second reference voltage Vref 2 can be transmitted by the 9th transistor T9 and the 7th transistor T7
To third liquid crystal capacitance Clc3.Therefore, the voltage value that the first liquid crystal capacitance Clc1 and third liquid crystal capacitance Clc3 are stored can quilt
Resetting.
Then, in the first write phase Tw1, write control signal CTw and first control signal CT1 are enable level,
Reset control signal CTr, second control signal CT2 and third control signal CT3 are forbidden energy level.Therefore, writing transistor Tw,
Third transistor T3 and the 7th transistor T7 are in the conductive state, and reset transistor Tr, the 4th transistor T4, the 5th transistor
T5, the 8th transistor T8 and the 9th transistor T9 are in an off state.
Therefore, in the first write phase Tw1, the first pixel circuit 210 [1], the second pixel circuit 220 [1] and mode
Switching circuit 230 will form the equivalent circuit of Fig. 4 (b).As shown in Fig. 4 (b), there is the data voltage Vdata warp of concussion waveform
After crossing the rectification of the first transistor T1 and the 6th transistor T6, the can be transferred to via second transistor T2 and third transistor T3
One liquid crystal capacitance Clc1, and third liquid crystal capacitance Clc3 is transferred to via the 7th transistor T7.
In the second reset phase Tr2, reset control signal CTr, second control signal CT2 and third control signal CT3
In enable level, and write control signal CTw and first control signal CT1 is in forbidden energy level.Therefore, reset transistor
Tr, the 4th transistor T4, the 5th transistor T5, the 8th transistor T8 and the 9th transistor T9 are in the conductive state, and third is brilliant
Body pipe T3 and the 7th transistor T7 are in an off state.
At this point, reset voltage Vr can be transferred to first node N1, so that the first transistor T1 is in the conductive state, and second
Transistor T2 and the 6th transistor T6 are in an off state.
Therefore, in the second reset phase Tr2, the first pixel circuit 210 [1], the second pixel circuit 220 [1] and mode
Switching circuit 230 will form the equivalent circuit of Fig. 4 (c).As shown in Fig. 4 (c), the first reference voltage Vref 1 can pass through the 5th crystalline substance
Body pipe T5 and the 4th transistor T4 is transferred to the second liquid crystal capacitance Clc2, and the second reference voltage Vref 2 can pass through the 9th transistor
T9 and the 8th transistor T8 are transferred to the 4th liquid crystal capacitance Clc4.Therefore, the second liquid crystal capacitance Clc2 and the 4th liquid crystal capacitance
The voltage value that Clc4 is stored can be reset.
Then, in the second write phase Tw2, write control signal CTw and second control signal CT2 are enable level,
And reset control signal CTr, first control signal CT1 and third control signal CT3 are forbidden energy level.Therefore, writing transistor
Tw, the 4th transistor T4 and the 8th transistor T8 are in the conductive state, and reset transistor Tr, third transistor T3, the 5th crystalline substance
Body pipe T5, the 7th transistor T7 and the 9th transistor T9 are in an off state.
Therefore, in the second write phase Tw2, the first pixel circuit 210 [1], the second pixel circuit 220 [1] and mode
Switching circuit 230 will form the equivalent circuit of Fig. 4 (d).As shown in Fig. 4 (d), there is the data voltage Vdata warp of concussion waveform
After crossing the rectification of the first transistor T1 and the 6th transistor T6, the can be transferred to via second transistor T2 and the 4th transistor T4
Two liquid crystal capacitance Clc2, and the 4th liquid crystal capacitance Clc4 is transferred to via the 6th transistor T6 and the 8th transistor T8.
After above-mentioned the first reset phase Tr1 to the second write phase Tw2, third controls signal CT3 to the 5th
The waveform for controlling signal CT5 can be similar to first control signal CT1 to third control signal CT3 in the first reset phase respectively
Waveform of the Tr1 into the second write phase Tw2, so that the first pixel circuit 210 [2] and the second pixel circuit 220 [2] execute phase
The first pixel circuit 210 [1] and the second pixel circuit 220 [1] are similar in the first reset phase Tr1 to the second write phase Tw2
Operation.
Then, the 5th control signal CT5 to the 7th controls the waveform of signal CT7, can also be similar to the first control letter respectively
Number CT1 to third control signal CT3 is in the first reset phase Tr1 to the waveform of the second write phase Tw2, so that the first pixel is electric
Road 210 [3] and the execution of the second pixel circuit 220 [3] are similar to the first pixel circuit 210 [1] and the second pixel circuit 220 [1]
In the first reset phase Tr1 to the operation of the second write phase Tw2, and so on.
Above-mentioned the first reset phase Tr1 to the second write phase Tw2 is suitable for nonpolarity reversion picture frame and polarity reversion
Picture frame.It is worth noting that, the first reference voltage Vref 1 has first voltage level in nonpolarity reversion picture frame, in polarity
Inverting has second voltage level in picture frame, and first voltage level is lower than second voltage level.Second reference voltage Vref 2 exists
There is tertiary voltage level in nonpolarity reversion picture frame, there is the 4th voltage level, and tertiary voltage in polarity reversion picture frame
Level is higher than the 4th voltage level.
For example, the first reference voltage Vref 1 is arranged to 5V in nonpolarity reversion picture frame in a certain embodiment,
It is arranged to 10V in polarity reversion picture frame.Second reference voltage Vref 2 is arranged to 5V in nonpolarity reversion picture frame, in pole
It is arranged to 0V in sex reversal picture frame.
In certain embodiments, the second gate of second transistor T2 is extremely coupled to first node N1.In this way, second
Transistor T2 can switch its switch state more quickly in response to the voltage change of first node N1.
In other embodiments, the transistor T5 of third transistor T3~the 5th and the 7th transistor T7~the 9th is brilliant
Body pipe T9 is realized with double gate transistor.The first control terminal of third transistor T3 and the 7th transistor T7 are coupled to grid
The first control terminal of signal wire GL [1], the 4th transistor T4 and the 8th transistor T8 are coupled to gate line GL [2], and the 5th
The first control terminal of transistor T5 and the 9th transistor T9 are coupled to gate line GL [3].Wherein, third transistor T3~the
Five transistor T5 and the 7th respective second control terminal of the transistor T9 of transistor T7~the 9th, are coupled to third transistor T3
The grid signal that~the five transistor T5 and the 7th respective first control terminal of the transistor T9 of transistor T7~the 9th are coupled
Line GL.In this way, which the transistor T5 of third transistor T3~the 5th and the 7th transistor T7~the can more effectively be turned off
Nine transistor T9, to reduce the electrical leakage quantity of the first liquid crystal capacitance Clc4 of liquid crystal capacitance C1c1~the 4th.
Below will with Fig. 5 and Fig. 6 (a)~6 (b) come further illustrate picture element matrix 110 in the first write phase Tw1 and
The mode of operation of second write phase Tw2.Data-signal Vdata include the first sub-data signals Sdata1, the second subnumber it is believed that
Number Sdata2 and third sub-data signals Sdata3.As shown in figure 5, the first sub-data signals Sdata1 and the second sub-data signals
Sdata2 has the waveform shaken back and forth, and third sub-data signals Sdata3 is then fixed voltage.Wherein, the first sub-data signals
Amplitude of the amplitude of Sdata1 less than the second sub-data signals Sdata2, and the voltage level etc. of third sub-data signals Sdata3
In the equilbrium position (equilibrium position) of the first sub-data signals Sdata1 or the second sub-data signals Sdata2
Voltage level.
In the present embodiment, the first sub-data signals Sdata1 shakes back and forth between 10V and -10V, the second subnumber it is believed that
It number is shaken back and forth between 15V and -15V, third sub-data signals Sdata3 is then maintained at 0V, but the present invention is not implemented with this
Example is limited.
In addition, the voltage level of third sub-data signals Sdata3 is equal to the first preset voltage value above-mentioned, and the first son
The lowest voltage level (also that is, valley) of data-signal Sdata1 is equal to the second preset voltage value above-mentioned.
Therefore, referring to Fig. 2, when the first sub-data signals Sdata1 is in positive half period, the first subnumber it is believed that
Number Sdata1 can be by the second rectification circuit 222 [1], but can not pass through the first rectification circuit 212 [1].When the first subdata
When signal Sdata1 is in negative half-cycle, the first sub-data signals Sdata1 can be by the first rectification circuit 212 [1], but nothing
Method passes through the second rectification circuit 222 [1].
In addition, the second sub-data signals Sdata2 can lead to when the second sub-data signals Sdata2 is in positive half period
The second rectification circuit 222 [1] is crossed, but the first rectification circuit 212 [1] can not be passed through.When the second sub-data signals Sdata2 is in
When negative half-cycle, the second sub-data signals Sdata2 can by the first transistor T1, but can make second transistor T2 because
Critical voltage rises and turns off.Therefore, when the second sub-data signals Sdata2 is in negative half-cycle, the second sub-data signals
Sdata2 can not can not also pass through the second rectification circuit 222 [1] by the first rectification circuit 212 [1].
In addition, third sub-data signals Sdata3 can be by the first rectification circuit 212 [1], but it can not be whole by second
Current circuit 222 [1].
In the first write phase Tw1 above-mentioned or the second write phase Tw2, data-signal Vdata is by the first subdata
Signal Sdata1, the second sub-data signals Sdata2 and third sub-data signals Sdata3 are respectively according to first time weight, the
Two time weightings and third time weighting composition.By adjustment first time weight, the second time weighting and third time weighting,
It can determine the gray-scale intensity that the first pixel circuit 210 [1] and the second pixel circuit 220 [1] are shown.
For example, in the first write phase Tw1 and the second write phase Tw2 of a certain embodiment, first time weight,
Two time weightings and third time weighting are as shown in following table one.In the case, rank is written in first in data-signal Vdata
Section Tw1 has waveform shown in Fig. 6 (a), and has waveform shown in Fig. 6 (b) in the second write phase Tw2.
The time weighting of table one, the first write phase and the second write phase
| First time weight | Second time weighting | Third time weighting | |
| First write phase | 0.5 | 0.5 | 0 |
| Second write phase | 0.5 | 0 | 0.5 |
As shown in Fig. 6 (a), in the first write phase Tw1, the first sub-data signals Sdata1 has first time length
T1, the second sub-data signals Sdata2 have the second time span T2, and first time length T1 is equal to the second time span T2.
In first time length T1, the first sub-data signals Sdata1 can be transferred to the first liquid crystal capacitance Clc1 and third
Liquid crystal capacitance Clc2.Therefore, the past first node N1 aerial drainage of positive charge meeting that the first liquid crystal capacitance Clc1 is stored, and third liquid crystal
Capacitor Clc3 can receive the positive charge from first node N1.
Then, in the second time span T2, the second sub-data signals Sdata2 can be transferred to third liquid crystal capacitance Clc3,
But not it is transferred to the first liquid crystal capacitance Clc1.Therefore, the positive charge that the first liquid crystal capacitance Clc1 is stored can stop toward first
Node N1 aerial drainage, but third liquid crystal capacitance Clc3 can continue to receive the positive charge from first node N1.
In this way, which it is bright that the first liquid crystal capacitance Clc1 can be used for grayscale in performance at the end of the first write phase Tw1
Degree, and third liquid crystal capacitance Clc3 can be used for showing high gray brightness.
On the other hand, as shown in Fig. 6 (b), in the second write phase Tw2, the first sub-data signals Sdata1 has the
Three time span T3, third sub-data signals Sdata3 have the 4th time span T4, and third time span T3 is equal to the 4th
Time span T4.
In third time span T3, the first sub-data signals Sdata1 can be transferred to the second liquid crystal capacitance Clc2 and the 4th
Liquid crystal capacitance Clc4.Therefore, the past first node N1 aerial drainage of positive charge meeting that the second liquid crystal capacitance Clc2 is stored, and the 4th liquid crystal
Capacitor Clc4 can receive the positive charge from first node N1.
Then, in the 4th time span T4, third sub-data signals Sdata3 can be transferred to the second liquid crystal capacitance Clc2,
But not it is transferred to the 4th liquid crystal capacitance Clc4.Therefore, the positive charge that the second liquid crystal capacitance Clc2 is stored will continue to toward first
Node N1 aerial drainage, but the 4th liquid crystal capacitance Clc4 can stop receiving the positive charge from first node N1.
In this way, which the second liquid crystal capacitance Clc2 can be used for showing high gray bright at the end of the second write phase Tw2
Degree, and the 4th liquid crystal capacitance Clc4 can be used for gray-scale intensity in performance.
In summary, when the first pixel circuit 210 [1] receives the first sub-data signals Sdata1 or third subnumber it is believed that
When number Sdata3, the first pixel circuit 210 [1] can be by the positive charge aerial drainage of storage to first node N1.Therefore, in the first write-in
In stage Tw1 and the second write phase Tw2, when the voltage level meeting negative of second node N2 is about first time weight and third
Between weight summation.
In addition, when the second pixel circuit 220 [1] receives the first sub-data signals Sdata1 or the second sub-data signals
When Sdata2, the second pixel circuit 220 [1] can receive the positive charge from first node N1.Therefore, in the first write phase
In Tw1 and the second write phase Tw2, the voltage level of third node N3 can be positively correlated with first time weight and the second time power
The summation of weight.
In conclusion display panel 100 can make full use of the data voltage Vdata of positive half period and negative half-cycle to come to
One pixel circuit 210 and the second pixel circuit 220 carry out data write-in, so having plenty of time to charge to liquid crystal capacitance
Expected voltage level.
In addition, though the first pixel circuit 210 receive the data-signal for being less than or equal to the first preset voltage value
Vdata, and the second pixel circuit 220 receive the data-signal Vdata for being greater than the first preset voltage value, but display panel 100
When determining gray-scale intensity that the first pixel circuit 210 and the second pixel circuit 220 are showed, it is not necessary to change data voltage
Vdata and only needs the amplitude for changing data voltage Vdata merely smaller and larger than the time scale of the first preset voltage value.Cause
This, data voltage Vdata is general string wave.And by data voltage Vdata by receive circuit 120 produced according to input signal
It is raw, so input signal is also general string wave, display panel 100 is enabled to generate input signal using simple circuit.
Some vocabulary is used in specification and claim to censure specific element.However, technical field
Middle tool usually intellectual is, it is to be appreciated that same element may be called with different nouns.Specification and claim
Not in such a way that the difference of title is as element is distinguished, but carry out the benchmark as differentiation with the difference of element functionally.
The "comprising" mentioned by specification and claim is open term, therefore should be construed to " including but not limited to ".Separately
Outside, " coupling " is herein comprising any direct and indirect connection means.Therefore, if it is described herein that first element is coupled to second yuan
Part, then representing first element can be directly connected by being electrically connected or being wirelessly transferred, and the signals connection type such as optical delivery
In second element, or by other elements or connection means, electrical property or signal are connected to the second element indirectly.
In addition, unless specified in the instructions, otherwise the term of any singular lattice all includes the connotation of multiple grid simultaneously.
Certainly, the present invention can also have other various embodiments, without deviating from the spirit and substance of the present invention, ripe
It knows those skilled in the art and makes various corresponding changes and modifications, but these corresponding changes and change in accordance with the present invention
Shape all should fall within the scope of protection of the appended claims of the present invention.
Claims (10)
1. a kind of display panel, characterized by comprising:
Multiple reception circuits, for receiving multiple input signals, and according to the corresponding multiple data-signals of output of those input signals；
And
Multiple picture element matrixs, wherein each picture element matrix includes:
Multiple first pixel circuits；
Multiple second pixel circuits；And
One mode switching circuit, wherein those first pixel circuits, those second pixel circuits and mode switching circuit coupling
In a first node；
Wherein, which receives one first data-signal, and first data-signal from multiple data-signal
With a concussion waveform, the mode switching circuit for selectively export first data-signal or a reset voltage to this
One node,
When first data-signal is less than or equal to one first preset voltage value and is greater than or equal to second preset voltage value,
The one of them of those the first pixel circuits receives first data-signal,
When first data-signal is greater than first preset voltage value, the one of them of those the second pixel circuits receive this
One data-signal.
2. display panel as described in claim 1, which is characterized in that wherein, each of those the first pixel circuits includes:
One first rectification circuit, is coupled between the first node and a second node, wherein when first data-signal is less than
Or be equal to first preset voltage value and be greater than or equal to second preset voltage value when, first rectification circuit be connected this first
Node and the second node, when first data-signal is greater than first preset voltage value or is less than second preset voltage value
When, which disconnects the first node and the second node；
One first gray scale control circuit, is coupled to the second node, for receiving first data-signal from the second node, and
For determining the grayscale value of first pixel circuit according to first data-signal；And
One first reset circuit, is coupled to the second node, wherein this first when the first node and the second node disconnect
One first reference voltage is transferred to the second node by reset circuit.
3. display panel as claimed in claim 2, which is characterized in that wherein, which includes:
One the first transistor includes a first end, a second end and a control terminal, wherein first end coupling of the first transistor
It is connected to the first node；
One second transistor, include a first end, a second end, one first control terminal and one second control terminal, wherein this second
The first end of transistor and second control terminal are coupled to control terminal and the second end of the first transistor, second crystalline substance
The second end of body pipe and first control terminal are coupled to the second node；
Wherein, which includes:
One first switch, includes a first end, a second end and a control terminal, the first end of the first switch be coupled to this
Two nodes, the control terminal of the first switch is for receiving a first control signal；
One first liquid crystal capacitance is coupled to the second end of the first switch；
One second switch, includes a first end, a second end and a control terminal, the first end of the second switch be coupled to this
Two nodes, the control terminal of the second switch is for receiving a second control signal；And
One second liquid crystal capacitance is coupled to the second end of the second switch；
Wherein, which includes:
One third switch, includes a first end, a second end and a control terminal, the first end of third switch be coupled to this
Two nodes, the control terminal of third switch is for receiving third control signal, and the second end of third switch is for connecing
Receive first reference voltage.
4. display panel as claimed in claim 3, which is characterized in that wherein, which additionally comprises one second control terminal,
The second switch additionally comprises one second control terminal, and third switch additionally comprises one second control terminal,
Wherein, second control terminal of the first switch, second control terminal of the second switch and third switch this
Two control terminals are respectively used to receive the first control signal, the second control signal and third control signal.
5. display panel as claimed in claim 3, which is characterized in that wherein, anti-in a nonpolarity reversion picture frame and a polarity
Turn in picture frame, which is respectively provided with a first voltage level and a second voltage level, and first voltage electricity
It is flat to be lower than the second voltage level.
6. display panel as claimed in claim 3, which is characterized in that wherein, which includes:
One Resetting Switching includes a first end, a second end and a control terminal, and the first end of the Resetting Switching is for receiving this
Reset voltage, the second end of the Resetting Switching are coupled to the first node, and the control terminal of the Resetting Switching is for receiving one
Reset control signal；And
One write switch includes a first end, a second end and a control terminal, and the first end of the write switch is for receiving this
First data-signal, the second end of the write switch are coupled to the first node, and the control terminal of the write switch is for connecing
Receive a write control signal.
7. display panel as claimed in claim 2, which is characterized in that wherein, the data-signal include one first subnumber it is believed that
Number, one second sub-data signals and a third sub-data signals；
Wherein, first sub-data signals and second sub-data signals have the waveform shaken back and forth, the third subnumber it is believed that
Number be a fixed voltage, and the amplitude of first sub-data signals be less than second sub-data signals amplitude.
8. display panel as claimed in claim 7, which is characterized in that wherein, in a write phase, the data-signal is by this
First sub-data signals, second sub-data signals and the third sub-data signals are respectively according to a first time weight, one the
Two time weightings and third time weighting composition, and the voltage level negative of the second node about the first time weight and
The summation of the third time weighting.
9. display panel as claimed in claim 8, which is characterized in that wherein, each of those the second pixel circuits includes:
One second rectification circuit is coupled between the first node and a third node, wherein when first data-signal is greater than
When first preset voltage value, which is connected the first node and the third node, when first data-signal
When less than or equal to first preset voltage value, which disconnects the first node and the third node；
One second gray scale control circuit is coupled to the third node, for receiving first data-signal from the third node, and
For determining the grayscale value of second pixel circuit according to first data-signal；And
One second reset circuit is coupled to the third node, wherein this second when the first node and the third node disconnect
One second reference voltage is transferred to the third node by reset circuit.
10. display panel as claimed in claim 9, which is characterized in that wherein, in the write phase, the third node
Voltage value can be positively correlated with the summation of the first time weight and second time weighting.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW107126938A TWI670701B (en) | 2018-08-02 | 2018-08-02 | Display panel |
| TW107126938 | 2018-08-02 |
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| CN109036321A true CN109036321A (en) | 2018-12-18 |
| CN109036321B CN109036321B (en) | 2021-03-16 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020224152A1 (en) * | 2019-05-08 | 2020-11-12 | 深圳市华星光电技术有限公司 | Driver chip waveform correction method and apparatus, and display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI712022B (en) * | 2020-01-09 | 2020-12-01 | 友達光電股份有限公司 | Display apparatus |
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| GB2300773A (en) * | 1994-06-06 | 1996-11-13 | Seiko Epson Corp | LCD display memory using access delay time simulators |
| US20040130513A1 (en) * | 2002-12-16 | 2004-07-08 | Seiko Epson Cororation | Method of driving electronic circuit, method of driving electronic apparatus, method of driving electro-optical apparatus, and electronic device |
| CN1758304A (en) * | 2004-10-04 | 2006-04-12 | 株式会社半导体能源研究所 | Display device and driving method |
| CN107945763A (en) * | 2018-01-05 | 2018-04-20 | 京东方科技集团股份有限公司 | Image element circuit, array base palte, display panel and display device |
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| JP4875248B2 (en) * | 2001-04-16 | 2012-02-15 | ゲットナー・ファンデーション・エルエルシー | Liquid crystal display |
| WO2008015813A1 (en) * | 2006-08-02 | 2008-02-07 | Sharp Kabushiki Kaisha | Active matrix substrate and display device with same |
| TWI612367B (en) * | 2017-01-04 | 2018-01-21 | 友達光電股份有限公司 | Pixel array structure |
| TWI622033B (en) * | 2017-07-05 | 2018-04-21 | 友達光電股份有限公司 | Wireless display with dual gate tft |
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- 2018-08-02 TW TW107126938A patent/TWI670701B/en active
- 2018-09-26 CN CN201811121689.8A patent/CN109036321B/en active Active
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| GB2300773A (en) * | 1994-06-06 | 1996-11-13 | Seiko Epson Corp | LCD display memory using access delay time simulators |
| US20040130513A1 (en) * | 2002-12-16 | 2004-07-08 | Seiko Epson Cororation | Method of driving electronic circuit, method of driving electronic apparatus, method of driving electro-optical apparatus, and electronic device |
| CN1758304A (en) * | 2004-10-04 | 2006-04-12 | 株式会社半导体能源研究所 | Display device and driving method |
| CN107945763A (en) * | 2018-01-05 | 2018-04-20 | 京东方科技集团股份有限公司 | Image element circuit, array base palte, display panel and display device |
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| WO2020224152A1 (en) * | 2019-05-08 | 2020-11-12 | 深圳市华星光电技术有限公司 | Driver chip waveform correction method and apparatus, and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109036321B (en) | 2021-03-16 |
| TW202008338A (en) | 2020-02-16 |
| TWI670701B (en) | 2019-09-01 |
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