CN109031823B

CN109031823B - Display screen, electronic equipment and control method thereof

Info

Publication number: CN109031823B
Application number: CN201810858392.3A
Authority: CN
Inventors: 杨乐
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2018-07-31
Filing date: 2018-07-31
Publication date: 2023-06-30
Anticipated expiration: 2038-07-31
Also published as: CN109031823A

Abstract

The application discloses display screen, including a plurality of gate lines, a plurality of data lines and a plurality of drive line, a plurality of gate lines and a plurality of data lines alternately insulating arrangement and form a plurality of sub-pixels of array arrangement, be equipped with first thin film transistor and pixel electric capacity in each sub-pixel, be equipped with photoelectric sensor in partial or whole sub-pixel in order to form discernment sub-pixel. In the same identification sub-pixel, the first thin film transistor comprises a grid electrode, a first end and a second end, the grid electrode of the first thin film transistor is electrically connected to the grid line, the first end of the first thin film transistor is electrically connected to the data line, the second end of the first thin film transistor is electrically connected to the pixel capacitor, the input end of the photoelectric sensor is electrically connected with the driving line, the output end of the photoelectric sensor is electrically connected to the second end of the first thin film transistor, and the photoelectric sensor is used for identifying target light carrying fingerprint information of a user. The screen occupation of the display screen is relatively high. The application also discloses electronic equipment and a control method thereof.

Description

Display screen, electronic equipment and control method thereof

Technical Field

The present disclosure relates to the field of electronic technologies, and in particular, to a display screen, an electronic device using the display screen, and a control method of the electronic device.

Background

The fingerprint identification component of the traditional electronic device occupies the space of the non-display area of the electronic device, so that the screen occupation ratio of the electronic device is limited to be improved. As the screen duty ratio of the electronic device is more and more demanded by users, how to reduce the area of the fingerprint recognition component occupying the non-display area of the electronic device so as to increase the screen duty ratio of the electronic device becomes a problem to be solved.

Disclosure of Invention

The application provides a display screen with a relatively high screen occupation, electronic equipment applying the display screen and a control method of the electronic equipment.

The embodiment of the application adopts the following technical scheme:

in one aspect, a display screen is provided, including a plurality of gate lines, a plurality of data lines, and a plurality of driving lines, where the gate lines and the data lines are alternately and insulated and arranged to form a plurality of sub-pixels arranged in an array, a first thin film transistor and a pixel capacitor are disposed in each sub-pixel, and a photoelectric sensor is disposed in some or all of the sub-pixels to form an identification sub-pixel;

in the same identification sub-pixel, the first thin film transistor includes a gate electrode, a first end and a second end, the gate electrode of the first thin film transistor is electrically connected to the gate line, the first end of the first thin film transistor is electrically connected to the data line, the second end of the first thin film transistor is electrically connected to the pixel capacitor, the input end of the photoelectric sensor is electrically connected to the driving line, the output end of the photoelectric sensor is electrically connected to the second end of the first thin film transistor, and the photoelectric sensor is used for identifying target light carrying fingerprint information of a user.

On the other hand, the electronic equipment comprises a controller and the display screen, wherein the controller is electrically connected with the display screen.

In still another aspect, there is further provided a control method of an electronic device, where the electronic device includes a controller and a display screen, where the display screen includes a plurality of gate lines, a plurality of data lines, and a plurality of driving lines, the plurality of gate lines and the plurality of data lines are arranged in an insulating manner in a crossing manner and form a plurality of sub-pixels arranged in an array, a first thin film transistor and a pixel capacitor are disposed in each of the sub-pixels, and a photoelectric sensor is disposed in some or all of the sub-pixels to form an identification sub-pixel;

in the same identification sub-pixel, the first thin film transistor includes a gate electrode, a first end and a second end, the gate electrode of the first thin film transistor is electrically connected to the gate line, the first end of the first thin film transistor is electrically connected to the data line, the second end of the first thin film transistor is electrically connected to the pixel capacitor, the input end of the photoelectric sensor is electrically connected to the driving line, the output end of the photoelectric sensor is electrically connected to the second end of the first thin film transistor, and the photoelectric sensor is used for identifying target light carrying fingerprint information of a user;

The frame time of the display screen comprises a display period and an identification period;

the control method of the electronic equipment comprises the following steps:

in a display period of the display screen, the controller loads a first signal on the grid line to turn on the first thin film transistor, and loads a gray scale voltage on the data line and transmits the gray scale voltage to the pixel capacitor so as to enable the identification sub-pixel to display;

in the identification period of the display screen, the controller loads a second signal on the grid line to open the first thin film transistor, and loads a driving signal on the driving line and transmits the driving signal to the photoelectric sensor so that the photoelectric sensor forms an electric signal according to the target light and outputs the electric signal through the data line.

In this application, because photoelectric sensor locates in the discernment subpixel, discernment subpixel is located in the display area of display screen, consequently by one or more the fingerprint identification module that photoelectric sensor formed can be located in the display area, the fingerprint identification module need not occupy the non-display area space of display screen, the non-display area of display screen can reduce in traditional display screen, the display area of display screen can increase in traditional display screen, thereby has improved the display screen and has used the display screen the screen ratio of electronic equipment's of display screen. The identification sub-pixel multiplexes the gate line, the first thin film transistor and the data line in the display circuit part and the identification circuit part to simplify the circuit of the identification sub-pixel, so that the circuit structure of the identification sub-pixel is simpler and the cost is lower.

Drawings

In order to more clearly illustrate the technical solutions of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained by those skilled in the art without the inventive effort.

Fig. 1 is a schematic structural diagram of an electronic device provided in the present application;

FIG. 2 is a front view of a display screen of the electronic device shown in FIG. 1;

FIG. 3 is a schematic diagram of a portion of the circuitry of the display screen of FIG. 2;

FIG. 4 is a schematic diagram of a portion of the circuitry of FIG. 3 that identifies a subpixel in one embodiment;

FIG. 5 is a timing diagram of the drive of the sub-pixel identifying circuit of FIG. 4 in one state of use;

FIG. 6 is a schematic diagram of a portion of the circuitry of FIG. 3 that identifies a subpixel in another embodiment;

FIG. 7 is a timing diagram of the drive of the sub-pixel identifying circuit of FIG. 6 in one state of use;

fig. 8 is a schematic structural diagram of a display screen provided in the present application in the first embodiment;

FIG. 9 is a schematic diagram of a portion of the structure of the array substrate of the display screen of FIG. 8 in one embodiment;

FIG. 10 is an exploded view of the structure of FIG. 9;

FIG. 11 is a schematic view of a portion of the structure of the array substrate of the display panel shown in FIG. 8 in another embodiment;

FIG. 12 is a schematic view of another part of the structure of the array substrate of the display panel shown in FIG. 8;

FIG. 13 is a schematic view of a portion of a color filter substrate of the display screen of FIG. 8;

fig. 14 is a schematic structural view of a display screen provided in the present application in a second embodiment;

FIG. 15 is a schematic view of a portion of the structure of the display screen of FIG. 14 in one embodiment;

FIG. 16 is an exploded view of the structure of FIG. 15;

FIG. 17 is a schematic view of a portion of the structure of the display screen of FIG. 14 in another embodiment;

FIG. 18 is a schematic view of a portion of the structure of the display screen of FIG. 14 in yet another embodiment;

FIG. 19 is a schematic view of another partial structure of the display screen of FIG. 14;

fig. 20 is a flowchart of a control method of an electronic device provided in the present application.

Detailed Description

Referring to fig. 1, fig. 1 is a schematic structural diagram of an electronic device 1000 provided in the present application.

The electronic device 1000 may be any device having communication and storage capabilities, such as: tablet computers, cell phones, electronic readers, remote controllers, personal computers (Personal Computer, PCs), notebook computers, vehicle-mounted devices, network televisions, wearable devices and the like.

The electronic device 1000 includes a display screen 100 and a controller 200. The controller 200 is electrically connected to the display 100. Electrical connections in this application include power connections and signal connections. The electronic device 1000 further includes a housing 300, the display 100 is mounted on the housing 300, and the controller 200 is accommodated in the housing 300.

Referring to fig. 2 and 3 together, fig. 2 is a front view of the display 100 of the electronic device 1000 shown in fig. 1, and fig. 3 is a schematic diagram of a part of the circuit of the display 100 shown in fig. 2.

The display screen 100 includes a display region 1001 and a non-display region 1002 disposed around the display region 1001. The display panel 100 includes a plurality of gate lines 10 and a plurality of data lines 20. "plurality" means two or more. The plurality of gate lines 10 are cross-insulatedly arranged with the plurality of data lines 20 and form a plurality of sub-pixels 1003 arranged in an array. The meaning of "plurality" is two or more. The two adjacent gate lines 10 and the two adjacent data lines 20 crossing the same define a region for disposing one of the sub-pixels 1003.

The display 100 further includes a gate driving circuit 30 and a data driving circuit 40. The gate driving circuit 30 and the data driving circuit 40 are electrically connected to the controller 200. The plurality of gate lines 10 are electrically connected to the gate driving circuit 30. The plurality of data lines 20 are electrically connected to the data driving circuit 40.

The sub-pixel 1003 is located within the display area 1001 of the display 100. The sub-pixel 1003 can be used to display a picture. A plurality of the subpixels 1003 constitute one pixel unit. For example, one of the pixel units includes three of the sub-pixels 1003, and the three sub-pixels 1003 are respectively used for displaying red (R), green (G) and blue (B) pictures. In another embodiment, one of the pixel units includes four sub-pixels 1003, and the four sub-pixels 1003 are respectively used for displaying red (R), green (G), blue (B) and white (W) pictures, or the four sub-pixels 1003 are respectively used for displaying red (R), green (G), blue (B) and yellow (Y) pictures.

A first thin film transistor (Thin Film Transistor, TFT) 50 and a pixel capacitor 60 are provided in each of the sub-pixels 1003. A photosensor 70 is provided in some or all of the subpixels 1003 to form an identification subpixel 1004. The photosensor 70 is used for identifying the target light carrying the fingerprint information of the user. When the light is reflected by the finger of the user to form the target light, the fingerprint lines of the finger of the user can be obtained by analyzing the distribution and the light intensity of the target light due to different reflection conditions of ridges and valleys in the fingerprint lines of the finger, so that the target light carries fingerprint information of the user. The identification sub-pixel 1004 can be used to identify fingerprint information of a user's finger.

In one embodiment, all the sub-pixels 1003 are provided with the photosensor 70, that is, all the sub-pixels 1003 are identification sub-pixels 1004, and the entire display area 1001 of the display screen 100 can perform target light identification. In another embodiment, a part of the sub-pixels 1003 are provided with the photo-sensor 70 to form the identification sub-pixels 1004, and the area of the display area 1001 of the display screen 100 where the identification sub-pixels 1004 are provided is capable of target light identification.

In this application, since the photoelectric sensor 70 is disposed in the identification sub-pixel 1004, the identification sub-pixel 1004 is disposed in the display area 1001 of the display screen 100, so that a fingerprint identification module formed by one or more photoelectric sensors 70 can be disposed in the display area 1001, the fingerprint identification module does not need to occupy the space of the non-display area 1002 of the display screen 100, the non-display area 1002 of the display screen 100 can be reduced compared with a conventional display screen, and the display area 1001 of the display screen 100 can be increased compared with a conventional display screen, thereby improving the screen ratio of the display screen 100 and the electronic device 1000 applying the display screen 100. As shown in fig. 1 and 2, the electronic device 1000 and the display screen 100 occupy a relatively large area, and even can realize a full-screen display.

As shown in fig. 2, in the identification sub-pixel 1004, the first thin film transistor 50 and the photosensor 70 are arranged in a plurality of positions. For example, the first thin film transistor 50 is arranged at the lower left corner of the identification subpixel 1004, and the photosensor 70 is positioned at the lower right corner, the upper left corner, or the upper right corner of the identification subpixel 1004.

It will be appreciated that in other embodiments, the light signal may be formed after being reflected by the palm or iris of the user, where the light signal carries palm print information or iris print information of the user. At this time, the plurality of photoelectric sensors are used for sensing palm texture or iris texture of the user, so that the electronic equipment obtains palm texture or iris texture images, and palm texture recognition or iris recognition is realized.

Referring to fig. 3 and 4 together, fig. 4 is a schematic diagram of a portion of the circuit of fig. 3 that identifies sub-pixel 1004 in one embodiment.

The first thin film transistor 50 includes a Gate 51 (G, also called a Gate), a first terminal 52, and a second terminal 53. In one embodiment, the first end 52 of the first thin film transistor 50 is a Source (S), and the second end 53 of the first thin film transistor 50 is a Drain (Drain, D). In another embodiment, the first end 52 of the first thin film transistor 50 is a drain, and the second end 53 of the first thin film transistor 50 is a source.

The photosensor 70 includes an input 71 and an output 72. The photosensor 70 is a unidirectional device, and current is transmitted in the direction of the input 71 to the output 72. When the photoelectric sensor 70 senses the target light, the target light is converted into an electrical signal, and the electrical signal is output by the output end 72.

In the same one of the identification sub-pixels 1004: the gate electrode 51 of the first thin film transistor 50 is electrically connected to the gate line 10, and the gate line 10 corresponds to the identification sub-pixel 1004. The gate line 10 may be loaded with a signal for turning on the first thin film transistor 50 to turn on the first and

second terminals

52 and 53 of the first thin film transistor 50. The gate line 10 may be loaded with a signal for turning off the first thin film transistor 50 to turn off the first and

second terminals

52 and 53 of the first thin film transistor 50.

The first end 52 of the first thin film transistor 50 is electrically connected to the data line 20, and the data line 20 corresponds to the identification sub-pixel 1004. The second terminal 53 of the first thin film transistor 50 is electrically connected to the pixel capacitor 60. When the pixel capacitor 60 is charged, the identification sub-pixel 1004 displays. As shown by the solid arrows in fig. 4, when the first thin film transistor 50 is turned on, the gray-scale signal loaded on the data line 20 enters the pixel capacitor 60 through the first thin film transistor 50, the pixel capacitor 60 is charged, and the identification sub-pixel 1004 displays. The display circuit portion of the identification sub-pixel 1004 includes the gate line 10, the first thin film transistor 50, the data line 20, and the pixel capacitor 60. The pixel capacitor 60 includes a pixel electrode 61, a common electrode 62, and a medium (i.e., a liquid crystal layer 63) disposed between the pixel electrode 61 and the common electrode 62. The pixel electrode 61 is connected to the second terminal 53 of the first thin film transistor 50. The common electrode 62 is connected to a common electrode line (not shown) of the display screen 100. When a gray scale signal is loaded on the data line 20 and a common voltage is loaded on the common electrode line, a voltage difference is formed at two ends of the pixel capacitor 60, and the pixel capacitor 60 is charged and displayed.

The display 100 further includes a plurality of driving lines 80. The plurality of driving lines 80 are electrically connected to the gate driving circuit 30 or the data driving circuit 40. In fig. 3, the plurality of driving lines 80 are electrically connected to the data driving circuit 40. The plurality of driving lines 80 may be integrated into one bus and then connected to the data driving circuit 40, so as to realize simultaneous driving. In other embodiments, a plurality of the driving lines 80 may be connected to the data driving circuit 40, respectively, to achieve separate driving, for example, row-by-row driving.

The input 71 of the photosensor 70 is electrically connected to the drive line 80. An output 72 of the photosensor 70 is electrically connected to the second terminal 53 of the first thin film transistor 50. As shown by the dotted arrow in fig. 4, when the driving line 80 is loaded with a driving signal and the first thin film transistor 50 is turned on, the photosensor 70 converts the received target light into an electrical signal, and the electrical signal is outputted from the data line 20. The display 100 recognizes a finger print of a user through the electrical signal. The identification circuit portion of the identification subpixel 1004 includes the gate line 10, the first thin film transistor 50, the driving line 80, the photosensor 70, and the data line 20.

In this application, the identification sub-pixel 1004 multiplexes the gate line 10, the first thin film transistor 50 and the data line 20 in the display circuit portion and the identification circuit portion, so as to simplify the circuit of the identification sub-pixel 1004, so that the circuit structure of the identification sub-pixel 1004 is simpler and the cost is lower.

Referring to fig. 4 and 5 together, fig. 5 is a timing diagram illustrating the driving of the circuit for identifying the sub-pixel 1004 shown in fig. 4 in a use state. In fig. 5, a change of a signal in the gate line 10, a change of a signal in the driving line 80, a change of a signal output from the data driving circuit 40 in the data line 20 (shown as 201), and a change of an electric signal formed from the photosensor 70 in the data line 20 (shown as 202) corresponding to one of the identification sub-pixels 1004 are schematically shown.

One frame time of the display screen 100 includes a display period and an identification period. The lengths of the display period and the identification period may be set according to requirements.

In the display period, the gate line 10 is used for loading a first signal to turn on the first thin film transistor 50, and the data line 20 is used for loading a gray scale voltage and transmitting the gray scale voltage to the pixel capacitor 60, so that the identification sub-pixel 1004 displays. The first thin film transistor 50 may be N-type or P-type. In the present application, the first signal for turning on the first thin film transistor 50 is a high level signal, taking the first thin film transistor 50 as an N-type example.

In the recognition period, the gate line 10 is used to load a second signal (e.g., a high level signal) to turn on the first thin film transistor 50, and the driving line 80 is used to load a driving signal and transmit the driving signal to the photosensor 70, so that the photosensor 70 forms an electrical signal according to the target light and outputs the electrical signal through the data line 20.

In one embodiment, the driving signal in the recognition period is a pulse signal. The change of the pulse amplitude of the electric signal feeds back the change of the target light. The controller 200 receives the electrical signal, and obtains fingerprint information of the user carried by the optical signal according to the electrical signal, thereby forming a fingerprint image of the user.

In this application, the driving signal is loaded on the gate line 10 in a time-sharing manner, the identification sub-pixel 1004 is displayed in the display period, and the fingerprint identification is performed on the identification sub-pixel 1004 in the identification period, so that the display screen 100 can give consideration to the display function and the identification function, thereby improving the use experience of the user.

Referring to fig. 6 and fig. 7 together, fig. 6 is a schematic diagram of a portion of the circuit for identifying the sub-pixel 1004 in the circuit shown in fig. 3 in another embodiment, and fig. 7 is a driving timing diagram of the circuit for identifying the sub-pixel 1004 in fig. 6 in a use state. Fig. 7 schematically illustrates the signal change in the gate line 10, the control line 110, the data line 20, and the driving line 80 corresponding to one of the identification sub-pixels 1004.

The identification sub-pixel 1004 is further provided with a second thin film transistor 90. The second thin film transistor 90 includes a gate electrode 91, a first end 92, and a second end 93. The first end 92 of the second thin film transistor 90 is connected to the second end 53 of the first thin film transistor 50. The second terminal 93 of the second thin film transistor 90 is connected to the pixel capacitor 60. The gate electrode 91 of the second thin film transistor 90 is configured to receive a control signal through a control line 110. The control line 110 is electrically connected to the gate driving circuit 30 or the data driving circuit 40. The control line 110 is electrically connected to the data driving circuit 40 for illustration. In the display period, the control signal turns on the second thin film transistor 90. In the recognition period, the control signal turns off the second thin film transistor 90. For example, the second thin film transistor 90 is of N type, and the control signal is a high level signal in the display period and a low level signal in the identification period.

In this embodiment, the display 100 controls the on/off state of the second thin film transistor 90 by the control signal, so that the pixel capacitor 60 is connected to the first thin film transistor 50 in the display period, and is disconnected from the first thin film transistor 50 in the identification period, so that the identification sub-pixel 1004 realizes display within one frame time of the display 100.

It can be appreciated that, when the sub-pixel 1003 of the non-identification sub-pixel 1004 is included in the display screen 100, the driving manner of the sub-pixel 1003 in the display period may be designed with reference to the display period of the identification sub-pixel 1004; the sub-pixel 1003 may not be driven for the recognition period.

In this application, the structure of the display 100 has various embodiments, for example:

in a first embodiment:

referring to fig. 8 to 10 together, fig. 8 is a schematic structural diagram of a display panel 100 according to a first embodiment, fig. 9 is a schematic structural diagram of a portion of an array substrate 1 of the display panel 100 shown in fig. 8 in an example, and fig. 10 is an exploded structural diagram of the structure shown in fig. 9.

For simplicity of illustration, components such as the sharing wires and the storage capacitors that may be present are omitted in the present embodiment, however, those skilled in the art should be able to determine the positions and the necessity of the omitted components according to the prior art, so that the description is omitted.

The display screen 100 includes an array substrate 1, a color film substrate 2, a liquid crystal layer 63, and a backlight module 3. The array substrate 1 is arranged opposite to the color film substrate 2. The liquid crystal layer 63 is located between the color film substrate 2 and the array substrate 1. The backlight module 3 is located at a side of the array substrate 1 away from the color film substrate 2, and the backlight module 3 is configured to provide a backlight source for the display screen 100. Meanwhile, when the user's finger touches the identification sub-pixel 1004 (see fig. 2) or is located above the identification sub-pixel 1004, the backlight light emitted by the backlight module 3 is reflected by the user's finger to form the target light, the target light carries fingerprint information of the user, and the target light can enter the identification sub-pixel 1004, so that the photoelectric sensor 70 in the identification sub-pixel 1004 forms a corresponding electrical signal according to the target light, and the electronic device 1000 can identify the fingerprint of the user according to the electrical signal. The display 100 may further include a cover plate 4, where the cover plate 4 is located at a side of the color film substrate 2 away from the array substrate 1. The cover plate 4 may be a glass cover plate.

It should be understood that, in this application, the display 100 has a display surface, the projections of the adjacent two gate lines 10 and the adjacent two data lines 20 intersecting with the two gate lines on the display surface together define a sub-pixel projection area, and the portions of the projections of the respective components of the display 100 on the display surface falling into the sub-pixel projection area together form the sub-pixel 1003. Each subpixel 1003 of the display 100 includes a portion of the array substrate 1, a portion of the color film substrate 2, and a portion of the liquid crystal layer 63 in the corresponding region.

The array substrate 1 is provided with the first thin film transistor 50 and the photosensor 70. The first thin film transistor 50 and the photosensor 70 are arranged in the same layer. Since the first thin film transistor 50 and the photo sensor 70 are disposed in the same layer, the first thin film transistor 50 and the photo sensor 70 can multiplex the thickness space of the array substrate 1, thereby reducing the overall thickness of the display 100.

Referring to fig. 9, the array substrate 1 includes a first substrate 11, a gate 51 of the first thin film transistor 50, a gate insulating layer 12, a semiconductor layer 54 of the first thin film transistor 50, a first end 52 and a second end 53 of the first thin film transistor 50, an output end 72 of the photosensor 70, an interlayer dielectric layer 13, a photosensitive layer 73 of the photosensor 70, and an input end 71 of the photosensor 70.

The gate electrode 51 of the first thin film transistor 50 is located on the first surface 111 of the first substrate 11. The gate insulating layer 12 is located on the first surface 111 and covers the gate 51 of the first thin film transistor 50. The semiconductor layer 54 of the first thin film transistor 50 is located on the surface 121 of the gate insulating layer 12 remote from the first substrate 11. The projection of the semiconductor layer 54 of the first thin film transistor 50 on the first surface 111 may cover the projection of the gate electrode 51 of the first thin film transistor 50 on the first surface 111. The first end 52 and the second end 53 of the first thin film transistor 50 are located on the surface 121 of the gate insulating layer 12 remote from the first substrate 11, and the first end 52 and the second end 53 of the first thin film transistor 50 are connected to two ends of the semiconductor layer 54 of the first thin film transistor 50, respectively. The output 72 of the photosensor 70 is located on the surface 121 of the gate insulating layer 12 remote from the first substrate 11, and the output 72 of the photosensor 70 is connected to the second end 53 of the first thin film transistor 50. The interlayer dielectric layer 13 is located on a side of the gate insulating layer 12 away from the first substrate 11, and covers the semiconductor layer 54, the first end 52, the second end 53, and the output end 72 of the photosensor 70 of the first thin film transistor 50. The interlayer dielectric layer 13 is an insulating layer. The interlayer dielectric layer 13 is provided with a first through hole 131, and the first through hole 131 is opposite to the output end 72 of the photoelectric sensor 70. In other words, the first through hole 131 exposes the output end 72 of the photosensor 70. The photosensitive layer 73 of the photosensor 70 is partially or entirely filled in the first through hole 131 and is connected to the output end 72 of the photosensor 70. The input 71 of the photosensor 70 is located on a surface 132 of the interlayer dielectric layer 13 remote from the gate insulating layer 12 and covers the photosensitive layer 73 of the photosensor 70.

In this embodiment, the partial layer structure of the first thin film transistor 50 and the partial layer structure of the photosensor 70 may share the same manufacturing process, so as to simplify the manufacturing process of the array substrate 1 and improve the manufacturing efficiency of the array substrate 1.

Optionally, the first end 52 and the second end 53 of the first thin film transistor 50 and the output end 72 of the photosensor 70 are formed by the same etching process. In other words, the second end 53 of the first thin film transistor 50 is integrally formed with the output end 72 of the photosensor 70. In the fabrication process, a complete conductive material layer may be laid on the side of the gate insulating layer 12 away from the first substrate 11, and then etched to form the first end 52 and the second end 53 of the first thin film transistor 50 and the output end 72 of the photosensor 70 at a time.

Alternatively, the target light identified by the photosensor 70 may be visible light or invisible light. When the target light may be visible light, the backlight light emitted by the backlight module 3 is visible light. When the target light may be invisible light, the backlight light emitted by the backlight module 3 includes visible light and invisible light.

For example, the target light is visible light, and the photosensitive layer 73 of the photosensor 70 generates a photoelectric effect when sensing the visible light. For example, the photosensitive layer 73 of the photosensor 70 may employ a silicon-rich compound including, but not limited to, silicon-rich silicon oxide (SiOx), silicon-rich silicon nitride (SiNy), silicon-rich silicon oxynitride (SiOxNy), and the like. The input end 71 of the photosensor 70 is made of transparent conductive material. The transparent conductive material may be, but is not limited to, indium Tin Oxide (ITO). The target light passes through the input end 71 of the photosensor 70 into the photosensitive layer 73 of the photosensor 70.

A light shielding layer is required to be disposed on a side of the photosensitive layer 73 of the photosensor 70 facing the backlight module 3. The light shielding layer is provided with various implementations, for example:

referring to fig. 9 and 10, the output end 72 of the photosensor 70 is made of a light-shielding conductive material. The projection of the output 72 of the photosensor 70 onto the first surface 111 covers the projection of the photosensitive layer 73 of the photosensor 70 onto the first surface 111. At this time, the output end 72 of the photosensor 70 may serve as a light shielding layer, and the output end 72 of the photosensor 70 may prevent the backlight light emitted from the backlight module 3 from interfering with the identification of the photosensor 70.

Alternatively, referring to fig. 11, fig. 11 is a schematic diagram illustrating a part of the structure of the array substrate 1 of the display panel 100 shown in fig. 8 in another embodiment. The array substrate 1 further comprises a wire 17. The wire 17 is located on the first surface 111 of the first substrate 11. The lead 17 is made of a light shielding material. The projection of the wire 17 onto the first surface 111 covers the projection of the photosensitive layer 73 of the photosensor 70 onto the first surface 111. The wires 17 can prevent the backlight light emitted from the backlight module 3 from interfering with the identification of the photoelectric sensor 70. At this time, the conductive wire 17 may serve as a light shielding layer, and the output end 72 of the photosensor 70 may be made of a transparent conductive material or an opaque conductive material. The wires 17 may be traces for transmitting other signals. The conductive line 17 may be formed on the same layer as the gate electrode 51 by the same etching process.

In other embodiments, the target light is invisible light, and the photoelectric effect occurs when the photosensitive layer 73 of the photosensor 70 senses the invisible light. For example, the target light may be infrared light, near infrared light, ultraviolet light, or ultraviolet light. The material of the photosensitive layer 73 of the photosensor 70 may be a material having a special response to infrared rays or near infrared rays, such as lead sulfide (PbS), or a semiconductor material having a response to ultraviolet rays or near ultraviolet rays, such as Indium Tin Zinc Oxide (ITZO) or Indium Gallium Zinc Oxide (IGZO).

Referring to fig. 9 and fig. 10 together, in one embodiment, the interlayer dielectric layer 13 is further provided with a second via 133. The second through hole 133 is opposite to the first end 52 of the first thin film transistor 50. The second via hole 133 exposes a portion of the first end 52 of the first thin film transistor 50. The array substrate 1 further includes a first electrode 14. The first electrode 14 is located on a surface 132 of the interlayer dielectric layer 13 away from the gate insulating layer 12, and is connected to the first end 52 of the first thin film transistor 50 through the second via hole 133. The first electrode 14 is connected to the data line 20. The first electrode 14 and the input 71 of the photosensor 70 may be formed by the same etching process. Alternatively, the data line 20 may be disposed in the same layer as the first electrode 14 and formed by the same etching process.

In other embodiments, the data line 20 may be disposed on the same layer as the first end 52 of the first thin film transistor 50. The data line 20 is directly connected to the first end 52 of the first thin film transistor 50. The data line 20 may be formed by the same etching process as the first end 52 of the first thin film transistor 50. In comparison with the foregoing embodiments, in the present embodiment, the array substrate 1 does not need to provide the first electrode 14 and the second through hole 133, and the structure of the array substrate 1 is simplified.

Referring to fig. 9 and fig. 10 together, in one embodiment, a third via 134 is further formed on the interlayer dielectric layer 13. The third through hole 134 is opposite to the second terminal 53 of the first thin film transistor 50. The third via 134 exposes a portion of the second end 53 of the first thin film transistor 50. The array substrate 1 further includes a second electrode 15, where the second electrode 15 is located on a surface 132 of the interlayer dielectric layer 13 away from the gate insulating layer 12, and is connected to the second end 53 of the first thin film transistor 50 through the third via 134. The second electrode 15 and the input 71 of the photosensor 70 may be formed by the same etching process. The second electrode 15 is connected to the pixel capacitance 60.

Referring to fig. 12, fig. 12 is a schematic diagram illustrating another part of the structure of the array substrate 1 of the display panel 100 shown in fig. 8 in one embodiment. The structure shown in fig. 12 can be combined with the structure shown in fig. 8, or can be combined with the structure shown in fig. 11.

The array substrate 1 is further provided with a second thin film transistor 90, specifically: the array substrate 1 further includes a gate electrode 91 of the second thin film transistor 90, a semiconductor layer 94 of the second thin film transistor 90, first and second ends 92 and 93 of the second thin film transistor 90, and a pixel electrode 61.

The gate electrode 91 of the second thin film transistor 90 is located on the first surface 111 of the first substrate 11. The gate electrode 91 of the second thin film transistor 90 and the gate electrode 51 of the first thin film transistor 50 are disposed in the same layer, and may be formed by the same etching process. The gate insulating layer 12 also covers the gate electrode 91 of the second thin film transistor 90. The semiconductor layer 94 of the second thin film transistor 90 is located on the surface 121 of the gate insulating layer 12 remote from the first substrate 11. The projection of the semiconductor layer 94 of the second thin film transistor 90 on the first surface 111 may cover the projection of the gate electrode 91 of the second thin film transistor 90 on the first surface 111. The semiconductor layer 94 of the second thin film transistor 90 and the semiconductor layer 54 of the first thin film transistor 50 are disposed in the same layer, and may be formed by the same etching process. The first end 92 and the second end 93 of the second thin film transistor 90 are located on the surface 121 of the gate insulating layer 12 away from the first substrate 11, and the first end 92 and the second end 93 of the second thin film transistor 90 are respectively connected to two ends of the semiconductor layer 94 of the second thin film transistor 90. The first end 92 and the second end 53 of the second thin film transistor 90 and the first end 52 and the second end 53 of the first thin film transistor 50 are disposed in the same layer, and may be formed by the same etching process.

The interlayer dielectric layer 13 also covers the semiconductor layer 94, the first end 92 and the second end 93 of the second thin film transistor 90. The interlayer dielectric layer 13 is provided with a fifth via 136, and the fifth via 136 is opposite to the first end 92 of the second thin film transistor 90. The second electrode 15 is also connected to the first end 92 of the second thin film transistor 90 through the fifth via 136. The interlayer dielectric layer 13 is further provided with a sixth via hole 137, and the sixth via hole 137 is opposite to the second terminal 93 of the second thin film transistor 90. The pixel electrode 61 is located on a surface 132 of the interlayer dielectric layer 13 away from the gate insulating layer 12, and is connected to the second end 93 of the second thin film transistor 90 through the sixth via hole 137. The pixel electrode 61 and the second electrode 15 are arranged in the same layer, and may be formed by the same etching process.

In other embodiments, the first end 92 of the second thin film transistor 90 is directly connected to the second end 53 of the first thin film transistor 50. In comparison with the foregoing embodiments, in the present embodiment, the array substrate 1 does not need to provide the second electrode 154 and the fifth through hole 136, and the structure of the array substrate 1 is simplified.

In other embodiments, when the display 100 is not provided with the second thin film transistor 90, the pixel electrode 61 is directly connected to the second electrode 15 (or the second end 53 of the first thin film transistor 50).

Referring to fig. 12 and fig. 13 together, fig. 13 is a schematic view illustrating a part of the structure of the color film substrate 2 of the display screen 100 shown in fig. 8. The structure of the color film substrate 2 shown in fig. 13 can be combined with the structure of the array substrate 1 shown in fig. 12.

The color film substrate 2 includes a second substrate 21, a color resist layer 22, and a common electrode layer 23. The color resist layer 22 is laminated on the second substrate 21, and the common electrode layer 23 is located on a side of the color resist layer 22 away from the second substrate 21. The common electrode 62, the pixel electrode 61, and the liquid crystal layer 63 (see fig. 8) between the common electrode 62 and the pixel electrode 61 together form the pixel capacitance 60.

Wherein the color resist layer 22 comprises color blocks and a black matrix. The color block is transparent to visible light. The black matrix blocks visible light. When the target light is visible light, the projection of the photosensitive layer 73 of the photosensor 70 on the second substrate 21 falls within the projection range of the color block on the second substrate 21. When the target light is invisible light, the projection of the photosensitive layer 73 of the photosensor 70 on the second substrate 21 may fall within the projection range of the color block on the second substrate 21, or may fall within the projection range of the black matrix on the second substrate 21.

In a second embodiment:

referring to fig. 14 to 16 together, fig. 14 is a schematic structural view of a display 100 according to a second embodiment of the present application, fig. 15 is a schematic structural view of a portion of the display 100 shown in fig. 14 in an example, and fig. 16 is an exploded structural view of the structure shown in fig. 15.

The display 100 according to the present embodiment is different from the display 100 according to the first embodiment in that: the photoelectric sensor 70 is disposed on the color film substrate 2. For simplicity of illustration, components such as the sharing wires and the storage capacitors that may be present are omitted in the present embodiment, however, those skilled in the art should be able to determine the positions and the necessity of the omitted components according to the prior art, so that the description is omitted.

The display screen 100 includes an array substrate 1 and a color film substrate 2 disposed opposite to each other. The array substrate 1 is provided with the first thin film transistor 50. The color film substrate 2 is provided with the photoelectric sensor 70. At this time, the photosensor 70 and the first thin film transistor 50 may be partially or entirely overlapped to multiplex the space in the length and width of the display screen 100, thereby improving the aperture ratio of the display screen 100. The display 100 further includes a liquid crystal layer 63, a backlight module 3, and a cover plate 4.

The array substrate 1 includes a first base material 11, a gate electrode 51 of the first thin film transistor 50, a gate insulating layer 12, a semiconductor layer 54 of the first thin film transistor 50, first and second ends 52 and 53 of the first thin film transistor 50, an interlayer dielectric layer 13, and a third electrode 16.

The gate electrode 51 of the first thin film transistor 50 is located on the first surface 111 of the first substrate 11. The gate insulating layer 12 is located on the first surface 111 and covers the gate 51 of the first thin film transistor 50. The semiconductor layer 54 of the first thin film transistor 50 is located on the surface 121 of the gate insulating layer 12 remote from the first substrate 11. The projection of the semiconductor layer 54 of the first thin film transistor 50 on the first surface 111 may cover the projection of the gate electrode 51 of the first thin film transistor 50 on the first surface 111. The first end 52 and the second end 53 of the first thin film transistor 50 are located on the surface 121 of the gate insulating layer 12 remote from the first substrate 11, and the first end 52 and the second end 53 of the first thin film transistor 50 are connected to two ends of the semiconductor layer 54 of the first thin film transistor 50, respectively. The interlayer dielectric layer 13 is located on a side of the gate insulating layer 12 away from the first substrate 11 and covers the semiconductor layer 54, the first end 52 and the second end 53 of the first thin film transistor 50. The interlayer dielectric layer 13 is provided with a fourth through hole 135, and the fourth through hole 135 is opposite to the second end 53 of the first thin film transistor 50. The third electrode 16 is located on a surface 132 of the interlayer dielectric layer 13 away from the gate insulating layer 12, and is connected to the second end 53 of the first thin film transistor 50 through the fourth via hole 135.

The color film substrate 2 includes a second base material 21, an input end 71 of the photoelectric sensor 70, a photosensitive layer 73 of the photoelectric sensor 70, a support column 24, and an output end 72 of the photoelectric sensor 70.

The input 71 of the photosensor 70 is located on the side of the second substrate 21 facing the first substrate 11. The photosensitive layer 73 of the photosensor 70 is located on a surface 711 of the input end 71 of the photosensor 70 remote from the second substrate 21. The support column 24 is located on the side of the second substrate 21 facing the first substrate 11, and the support column 24 faces the third electrode 16. The output end 72 of the photosensor 70 is located on the surface 731 of the photosensitive layer 73 of the photosensor 70, which is far away from the second substrate 21, and the output end 72 of the photosensor 70 is partially erected on the support column 24 to abut against the third electrode 16. At this time, the photosensor 70 is electrically connected to the second terminal 53 of the first thin film transistor 50.

In this embodiment, when the user identifies the fingerprint, the distance between the user fingerprint and the photoelectric sensor 70 is smaller, so that the loss of the target light carrying the user fingerprint information in the transmission process is small, thereby improving the identification accuracy and the imaging quality.

When the target light is visible light, the input end 71 of the photosensor 70 is made of transparent conductive material. The output 72 of the photosensor 70 is made of a light-shielding conductive material. The projection of the output 72 of the photosensor 70 onto the second substrate 21 covers the projection of the photosensitive layer 73 of the photosensor 70 onto the second substrate 21. Alternatively, the output end 72 of the photosensor 70 is made of a transparent conductive material, and a light shielding member is disposed on a side of the output end 72 of the photosensor 70 away from the photosensitive layer 73 of the photosensor 70 to shield visible light.

When the target light is invisible light, the input end 71 of the photosensor 70 may be made of a transparent conductive material or an opaque conductive material, and the output end 72 of the photosensor 70 may be made of a transparent conductive material or an opaque conductive material.

The material arrangement of the photosensitive layer 73 of the photosensor 70 according to the present embodiment is referred to as the material arrangement of the photosensitive layer 73 of the photosensor 70 according to the first embodiment.

Referring to fig. 15 and fig. 16, in one embodiment, a second via 133 is further formed on the interlayer dielectric layer 13. The second through hole 133 is opposite to the first end 52 of the first thin film transistor 50. The array substrate 1 further includes a first electrode 14. The first electrode 14 is located on a surface 132 of the interlayer dielectric layer 13 away from the gate insulating layer 12, and is connected to the first end 52 of the first thin film transistor 50 through the second via hole 133. The first electrode 14 is connected to the data line 20. The first electrode 14 and the third electrode 16 may be formed by the same etching process. Alternatively, the data line 20 may be disposed in the same layer as the first electrode 14 and formed by the same etching process.

Referring to fig. 15 and fig. 16, in one embodiment, a third via 134 is further formed on the interlayer dielectric layer 13. The third through hole 134 is opposite to the second terminal 53 of the first thin film transistor 50. The array substrate 1 further comprises a second electrode 15. The second electrode 15 is located on a surface 132 of the interlayer dielectric layer 13 away from the gate insulating layer 12, and is connected to the second end 53 of the first thin film transistor 50 through the third via 134. The second electrode 15 is connected to the pixel capacitance 60. The second electrode 15 and the third electrode 16 may be formed by the same etching process.

In one embodiment, referring to fig. 15 and fig. 16, the color filter substrate 2 further includes a color resist layer 22. The color resist layer 22 is located on the second surface 211 of the second substrate 21 facing the first substrate 11. The color resist layer 22 includes a black matrix and color resist blocks.

The color resist layer 22 is provided with a first hole 221. The first hole 221 extends to the second surface 211, and the photosensor 70 is partially located in the first hole 221. At this time, the distance between the photoelectric sensor 70 and the user fingerprint is closer, which is beneficial to improving the recognition accuracy of the user fingerprint. Moreover, the color blocking layer 22 does not block the target light, and the target light may be visible light or invisible light.

Wherein, the color film substrate 2 further comprises a flat layer 25. The planarization layer 25 is located on a side of the color resist layer 22 away from the first substrate 11. The planar layer 25 is provided with a second hole 251. The second hole 251 communicates with the first hole 221. The photosensor 70 is partially located in the second hole 251.

The support posts 24 and the planarization layer 25 may be formed by the same etching process. At this time, the preparation process of the array substrate 1 is relatively simple, which is beneficial to reducing the cost of the array substrate 1.

The input 71 of the photosensor 70 is located in the first hole 221. The photosensitive layer 73 of the photosensor 70 is located in the second hole 251. The output 72 of the photosensor 70 is located on the side of the planarization layer 25 remote from the color resist layer 22.

In another embodiment, referring to fig. 17, fig. 17 is a schematic structural diagram of a portion of the display 100 shown in fig. 14 in another embodiment. This embodiment differs from the previous embodiments in that: the input 71 of the photosensor 70 and the photosensitive layer 73 are located in the first hole 221. The output 72 of the photosensor 70 is partially located in the second hole 251. The hole wall of the second hole 251 may be substantially flush with the side surface of the support column 24, so that the output end 72 of the photoelectric sensor 70 is not easy to break during forming, and the yield of the display screen 100 is improved.

In yet another embodiment, referring to fig. 18, fig. 18 is a schematic structural diagram of a portion of the display 100 shown in fig. 14 in yet another embodiment. The color film substrate 2 further includes a color resist layer 22. The color resist layer 22 is located on the second surface 211 of the second substrate 21 facing the first substrate 11. The color resist layer 22 includes a black matrix 222 and color resist blocks 223. This embodiment differs from the previous embodiments in that: the photosensor 70 is located on a side of the color resist layer 22 away from the second substrate 21. When the target light is visible light, the photosensitive layer 73 of the photosensor 70 is disposed opposite to the color block 223. In other words, the projection of the photosensitive layer 73 of the photosensor 70 on the second surface 211 falls within the projection range of the color block 223 on the second surface 211. When the target light is invisible light, the relative positional relationship between the photosensor 70, the color block 223 and the black matrix 222 is not strictly limited.

Referring to fig. 19 together, fig. 19 is a schematic diagram illustrating another part of the structure of the display 100 shown in fig. 14. The structure shown in fig. 19 can be combined with the structure shown in fig. 15, the structure shown in fig. 17, and the structure shown in fig. 18.

The array substrate 1 further includes a second thin film transistor 90, specifically: the array substrate 1 further includes a gate electrode 91 of the second thin film transistor 90, a semiconductor layer 94 of the second thin film transistor 90, first and second ends 92 and 93 of the second thin film transistor 90, and a pixel electrode 61.

The gate electrode 91 of the second thin film transistor 90 is located on the first surface 111 of the first substrate 11. The gate electrode 91 of the second thin film transistor 90 and the gate electrode 51 of the first thin film transistor 50 are disposed in the same layer, and may be formed by the same etching process. The gate insulating layer 12 also covers the gate electrode 91 of the second thin film transistor 90. The semiconductor layer 94 of the second thin film transistor 90 is located on the surface 121 of the gate insulating layer 12 remote from the first substrate 11. The projection of the semiconductor layer 94 of the second thin film transistor 90 on the first surface 111 may cover the projection of the gate electrode 91 of the second thin film transistor 90 on the first surface 111. The semiconductor layer 94 of the second thin film transistor 90 and the semiconductor layer 54 of the first thin film transistor 50 are disposed in the same layer, and may be formed by the same etching process. The first end 92 and the second end 93 of the second thin film transistor 90 are located on the surface 121 of the gate insulating layer 12 away from the first substrate 11, and the first end 92 and the second end 93 of the second thin film transistor 90 are respectively connected to two ends of the semiconductor layer 94 of the second thin film transistor 90. The first end 92 and the second end 93 of the second thin film transistor 90 and the first end 52 and the second end 53 of the first thin film transistor 50 are disposed in the same layer, and may be formed by the same etching process.

The color film substrate 2 further comprises a common electrode layer 23. The common electrode layer 23 is located on a side of the color resist layer 22 away from the second substrate 21. The common electrode 62, the pixel electrode 61, and the liquid crystal layer 63 between the common electrode 62 and the pixel electrode 61 together form the pixel capacitance 60.

Referring to fig. 20, fig. 20 is a flowchart of a control method of an electronic device provided in the present application.

The control method of the electronic device is applied to the electronic device 1000 described above (refer to fig. 1 to 19).

The electronic device 1000 includes a controller 200 and a display panel 100, and the display panel 100 includes a plurality of gate lines 10, a plurality of data lines 20, and a plurality of driving lines 80. The plurality of gate lines 10 are cross-insulatedly arranged with the plurality of data lines 20 and form a plurality of sub-pixels 1003 arranged in an array. A first thin film transistor 50 and a pixel capacitor 60 are provided in each of the sub-pixels 1003. A photosensor 70 is provided in some or all of the subpixels 1003 to form an identification subpixel 1004.

In the same identification sub-pixel 1004, the first thin film transistor 50 includes a gate electrode 51, a first end 52 and a second end 53, the gate electrode 51 of the first thin film transistor 50 is electrically connected to the gate line 10, the first end 52 of the first thin film transistor 50 is electrically connected to the data line 20, the second end 53 of the first thin film transistor 50 is electrically connected to the pixel capacitor 60, the input end 71 of the photosensor 70 is electrically connected to the driving line 80, the output end 72 of the photosensor 70 is electrically connected to the second end 53 of the first thin film transistor 50, and the photosensor 70 is used for identifying a target light carrying fingerprint information of a user.

One frame time of the display screen 100 includes a display period and an identification period.

The control method of the electronic equipment comprises the following steps:

001: in the display period of the display screen 100, the controller 200 loads a first signal on the gate line 10 to turn on the first thin film transistor 50, and the controller 200 loads a gray scale voltage on the data line 20 and transmits the gray scale voltage to the pixel capacitor 60 to cause the identification sub-pixel 1004 to display;

003: in the recognition period of the display screen 100, the controller 200 loads a second signal on the gate line 10 to turn on the first thin film transistor 50, and the controller 200 loads a driving signal on the driving line 80 and transmits the driving signal to the photosensor 70, so that the photosensor 70 forms an electrical signal according to the target light and outputs through the data line 20.

Optionally, a second thin film transistor 90 is further disposed in the identification subpixel 1004. The second thin film transistor 90 includes a gate electrode 91, a first end 92, and a second end 93. The first end 92 of the second thin film transistor 90 is connected to the second end 53 of the first thin film transistor 50. The second terminal 93 of the second thin film transistor 90 is connected to the pixel capacitor 60. The gate electrode 91 of the second thin film transistor 90 is electrically connected to the control line 110.

The control method of the electronic equipment further comprises the following steps:

in a display period of the display screen 100, a control signal capable of turning on the second thin film transistor 90 is loaded on the control line 110, so that the gray scale voltage is transmitted to the pixel capacitor 60 through the second thin film transistor 90;

during the recognition period of the display 100, a control signal capable of turning off the second thin film transistor 90 is loaded on the control line 110 to disconnect the pixel capacitor 60 from the first thin film transistor 50.

In this embodiment, the display 100 controls the on/off state of the second transistor according to the control signal, so that the pixel capacitor 60 is connected to the first thin film transistor 50 in the display period, and is disconnected from the first thin film transistor 50 in the identification period, so that the identification sub-pixel 1004 realizes display within one frame time of the display 100.

The foregoing has outlined rather broadly the more detailed description of embodiments of the present application, wherein specific examples are provided herein to illustrate the principles and embodiments of the present application, the above examples being provided solely to assist in the understanding of the methods of the present application and the core ideas thereof; in the case of no conflict, the embodiments of the present application and features of the embodiments may be combined with each other; meanwhile, as those skilled in the art will have modifications in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.

Claims

1. The display screen is characterized by comprising a plurality of grid lines, a plurality of data lines and a plurality of driving lines, wherein the grid lines and the data lines are alternately and insulating arranged to form a plurality of sub-pixels arranged in an array, a first thin film transistor and a pixel capacitor are arranged in each sub-pixel, and a photoelectric sensor is arranged in part or all of the sub-pixels to form an identification sub-pixel;

in the same identification sub-pixel, the first thin film transistor includes a gate electrode, a first end and a second end, the gate electrode of the first thin film transistor is electrically connected to the gate line, the first end of the first thin film transistor is electrically connected to the data line, the second end of the first thin film transistor is electrically connected to the pixel capacitor, the input end of the photoelectric sensor is electrically connected to the driving line, the output end of the photoelectric sensor is electrically connected to the second end of the first thin film transistor, and the photoelectric sensor is used for identifying target light carrying fingerprint information of a user; the pixel capacitor comprises a pixel electrode, a public electrode and a liquid crystal layer positioned between the pixel electrode and the public electrode, wherein the pixel electrode is connected to the second end of the first thin film transistor, the public electrode is connected to a public electrode wire of the display screen, when a gray-scale signal is loaded on the data wire, and when a public voltage is loaded on the public electrode wire, a voltage difference is formed at two ends of the pixel capacitor, and the pixel capacitor is charged and displays.

2. The display screen of claim 1, wherein a frame time of the display screen includes a display period and an identification period;

in the display period, the gate line is used for loading a first signal to turn on the first thin film transistor, and the data line is used for loading a gray scale voltage and transmitting the gray scale voltage to the pixel capacitor so as to enable the identification sub-pixel to display;

in the identification period, the gate line is used for loading a second signal to turn on the first thin film transistor, and the driving line is used for loading a driving signal and transmitting the driving signal to the photoelectric sensor so that the photoelectric sensor forms an electric signal according to the target light and outputs the electric signal through the data line.

3. The display screen of claim 2, wherein a second thin film transistor is further provided in the identification sub-pixel, the second thin film transistor including a gate electrode, a first terminal and a second terminal, the first terminal of the second thin film transistor being connected to the second terminal of the first thin film transistor, the second terminal of the second thin film transistor being connected to the pixel capacitance, the gate electrode of the second thin film transistor being configured to receive a control signal through a control line, the control signal turning on the second thin film transistor during the display period, and the control signal turning off the second thin film transistor during the identification period.

4. The display screen of claim 3, further comprising a gate driving circuit and a data driving circuit, wherein the plurality of gate lines are electrically connected to the gate driving circuit, the plurality of data lines are electrically connected to the data driving circuit, the driving lines are electrically connected to the gate driving circuit or the data driving circuit, and the control lines are electrically connected to the data driving circuit or the data driving circuit.

5. A display screen according to any one of claims 1 to 4, wherein the display screen comprises an array substrate provided with the first thin film transistor and the photosensor, the first thin film transistor and the photosensor being arranged in the same layer.

6. The display screen of claim 5, wherein the array substrate comprises:

a first substrate;

the grid electrode of the first thin film transistor is positioned on the first surface of the first substrate;

a gate insulating layer on the first surface and covering the gate of the first thin film transistor;

the semiconductor layer of the first thin film transistor is positioned on the surface of the gate insulating layer away from the first substrate, and the projection of the semiconductor layer of the first thin film transistor on the first surface covers the projection of the gate electrode of the first thin film transistor on the first surface;

The first end and the second end of the first thin film transistor are positioned on the surface of the gate insulating layer far away from the first substrate, and the first end and the second end of the first thin film transistor are respectively connected with the two ends of the semiconductor layer of the first thin film transistor;

the output end of the photoelectric sensor is positioned on the surface, far away from the first substrate, of the gate insulating layer, and the output end of the photoelectric sensor is connected with the second end of the first thin film transistor;

the interlayer dielectric layer is positioned on one side, far away from the first substrate, of the gate insulating layer and covers the semiconductor layer, the first end, the second end and the output end of the photoelectric sensor of the first thin film transistor, and is provided with a first through hole, and the first through hole is opposite to the output end of the photoelectric sensor;

the photosensitive layer of the photoelectric sensor is partially or completely filled in the first through hole and is connected with the output end of the photoelectric sensor; and

the input end of the photoelectric sensor is positioned on the surface of the interlayer dielectric layer far away from the gate insulating layer and covers the photosensitive layer of the photoelectric sensor.

7. The display screen of claim 6, wherein the first and second ends of the first thin film transistor and the output end of the photosensor are formed by a same etching process.

8. The display screen of claim 6, wherein the target light is visible light, the photosensitive layer of the photosensor is a photoelectric effect when sensing the visible light, and the input end of the photosensor is made of transparent conductive material.

9. A display screen as recited in claim 8, wherein the output of the photosensor is of a light-blocking conductive material, and wherein a projection of the output of the photosensor onto the first surface covers a projection of the photosensitive layer of the photosensor onto the first surface.

10. The display screen of claim 8, wherein the array substrate further comprises wires, the wires being located on the first surface, the wires employing a light shielding material, a projection of the wires on the first surface covering a projection of a photosensitive layer of the electrical sensor on the first surface.

11. The display screen of claim 6, wherein the interlayer dielectric layer is further provided with a second through hole, the second through hole is opposite to the first end of the first thin film transistor, the array substrate further comprises a first electrode, the first electrode is located on the surface of the interlayer dielectric layer away from the gate insulating layer, the first end of the first thin film transistor is connected through the second through hole, and the first electrode is connected to the data line.

12. The display screen of any one of claims 6 to 11, wherein a third via is further provided on the interlayer dielectric layer, the third via being opposite to the second end of the first thin film transistor, the array substrate further comprising a second electrode, the second electrode being located on a surface of the interlayer dielectric layer remote from the gate insulating layer and connected to the second end of the first thin film transistor through the third via, the second electrode being connected to the pixel capacitor.

13. A display screen according to any one of claims 1 to 4, wherein the display screen comprises an array substrate and a color film substrate which are arranged opposite to each other, the array substrate being provided with the first thin film transistor, the color film substrate being provided with the photosensor.

14. A display screen as recited in claim 13, wherein,

the array substrate includes:

a first substrate;

an interlayer dielectric layer which is positioned on one side of the gate insulating layer far away from the first substrate and covers the semiconductor layer, the first end and the second end of the first thin film transistor, wherein the interlayer dielectric layer is provided with a fourth through hole, and the fourth through hole is opposite to the second end of the first thin film transistor;

the third electrode is positioned on the surface of the interlayer dielectric layer far away from the gate insulating layer and is connected with the second end of the first thin film transistor through the fourth through hole;

the color film substrate comprises:

a second substrate;

the input end of the photoelectric sensor is positioned at one side of the second substrate facing the first substrate;

the photosensitive layer of the photoelectric sensor is positioned on the surface of the input end of the photoelectric sensor far away from the second substrate;

the support column is positioned on one side of the second substrate facing the first substrate and is opposite to the third electrode; and

The output end of the photoelectric sensor is positioned on the surface, far away from the second substrate, of the photosensitive layer of the photoelectric sensor, and the output end part of the photoelectric sensor is arranged on the support column in a building manner so as to prop against the third electrode.

15. A display screen as recited in claim 14, wherein the input of the photosensor is a transparent conductive material and the output of the photosensor is a light blocking conductive material, and wherein a projection of the output of the photosensor onto the second substrate covers a projection of the photosensitive layer of the photosensor onto the second substrate.

16. The display screen of claim 15, wherein the color film substrate further comprises a color blocking layer on a second surface of the second substrate facing the first substrate, the color blocking layer having a first aperture extending to the second surface, the photosensor portion being located in the first aperture.

17. The display screen of claim 16, wherein the color film substrate further comprises a flat layer, the flat layer is located on a side of the color resistance layer away from the first substrate, the flat layer is provided with a second hole, the second hole is communicated with the first hole, and the photoelectric sensor is partially located in the second hole.

18. The display screen of claim 17, wherein the input of the photosensor is located in the first aperture, the output of the photosensor is located in the second aperture, and the output of the photosensor is located on a side of the planar layer remote from the color blocking layer.

19. A display screen as recited in claim 17, wherein the input of the photosensor and photosensitive layer are located in the first aperture and the output portion of the photosensor is located in the second aperture.

20. A display screen as recited in any one of claims 17-19, wherein the support posts and the planar layer are formed by a same etching process.

21. The display screen of claim 14, wherein the color filter substrate further comprises a color blocking layer, the color blocking layer is disposed on a second surface of the second substrate facing the first substrate, the color blocking layer comprises a black matrix and a color block, the photosensor is disposed on a side of the color blocking layer away from the second substrate, and the photosensitive layer of the photosensor is disposed opposite to the color block when the target light is visible light.

22. The display screen of claim 14, wherein the interlayer dielectric layer is further provided with a second through hole, the second through hole is opposite to the first end of the first thin film transistor, the array substrate further comprises a first electrode, the first electrode is located on the surface of the interlayer dielectric layer away from the gate insulating layer, the first end of the first thin film transistor is connected through the second through hole, and the first electrode is connected to the data line.

23. The display screen of claim 14 or 22, wherein a third via is further provided on the interlayer dielectric layer, the third via being opposite to the second end of the first thin film transistor, the array substrate further comprising a second electrode, the second electrode being located on a surface of the interlayer dielectric layer away from the gate insulating layer and connected to the second end of the first thin film transistor through the third via, the second electrode being connected to the pixel capacitor.

24. An electronic device comprising a controller and the display of any one of claims 1 to 23, the controller being electrically connected to the display.

25. The control method of the electronic equipment is characterized by comprising a controller and a display screen, wherein the display screen comprises a plurality of grid lines, a plurality of data lines and a plurality of driving lines, the grid lines and the data lines are alternately and insulating arranged to form a plurality of sub-pixels arranged in an array, a first thin film transistor and a pixel capacitor are arranged in each sub-pixel, and a photoelectric sensor is arranged in part or all of the sub-pixels to form an identification sub-pixel;

In the same identification sub-pixel, the first thin film transistor includes a gate electrode, a first end and a second end, the gate electrode of the first thin film transistor is electrically connected to the gate line, the first end of the first thin film transistor is electrically connected to the data line, the second end of the first thin film transistor is electrically connected to the pixel capacitor, the input end of the photoelectric sensor is electrically connected to the driving line, the output end of the photoelectric sensor is electrically connected to the second end of the first thin film transistor, and the photoelectric sensor is used for identifying target light carrying fingerprint information of a user; the pixel capacitor comprises a pixel electrode, a common electrode and a liquid crystal layer positioned between the pixel electrode and the common electrode, wherein the pixel electrode is connected to the second end of the first thin film transistor, the common electrode is connected to a common electrode line of the display screen, when a gray-scale signal is loaded on the data line and a common voltage is loaded on the common electrode line, a voltage difference is formed at two ends of the pixel capacitor, and the pixel capacitor is charged and displays;

The control method of the electronic equipment comprises the following steps:

26. The method of claim 25, wherein a second thin film transistor is further disposed in the identification sub-pixel, the second thin film transistor including a gate electrode, a first terminal and a second terminal, the first terminal of the second thin film transistor being connected to the second terminal of the first thin film transistor, the second terminal of the second thin film transistor being connected to the pixel capacitor, the gate electrode of the second thin film transistor being electrically connected to a control line,

loading a control signal capable of opening the second thin film transistor on the control line in a display period of the display screen so that the gray scale voltage is transmitted to the pixel capacitor through the second thin film transistor;

and loading a control signal capable of closing the second thin film transistor on the control line in an identification period of the display screen so as to disconnect the pixel capacitor from the first thin film transistor.