CN109031223A - Based on the control of the T/R component of ARM and FPGA architecture and monitoring method - Google Patents

Abstract

The invention belongs to radars and control protection field, relate generally in phased-array radar system the malfunction monitoring of TR component and control guard method, including T/R component master control protect control monitoring, manipulation therefore inspection, frequency synthesizer manipulate therefore inspection and power supply therefore examine.Separate modular can carry out self-test and respond failure, take self-shield measure in time.The status information and fault message that module collects modules at different levels by polling mode are protected in master control, are completed fault diagnosis, are judged whether to take second protection measure, are finally concentrated and are reported information.This inquiry step by step, real-time response, the control guard method concentrating diagnosis, uniformly reporting are taken, reduces the time overhead of module response failure to the maximum extent, it is ensured that each module works safe and reliable, improves the signal stabilization under strong electromagnetic interference environment.

Description

Based on the control of the T/R component of ARM and FPGA architecture and monitoring method

Technical field

The invention belongs to radar controls to protect field.

Background technique

Currently, there is also larger gap, this performances for domestic and advanced country in terms of generalization test and trouble hunting Are as follows: standard, the monitoring range for lacking standardization are small, technological means is backward, do not have compatibility, System Expansion ability is poor therefore It is low etc. to hinder diagnosis efficiency, to development & production, debugging verifying, ensures that maintenance brings a series of problems.According to correlative study, advanced event Barrier monitoring technology can greatly improve maintenance efficiency, and Percent Isolated improves 30% or more, and 20% or more saving is subsequent Maintenance cost, advanced fault monitoring system can effectively improve with safeguards system performance, therefore increasingly by country weight Depending on and continue to develop.Contain active circuit in each antenna element channel of Connectors for Active Phased Array Radar antenna array, for receiving It is then T/R component for the phased array antenna for sending out unification.Array antenna complicated composition, this is former to the locking of fault point and failure The investigation of cause increases difficulty, it is to be ensured that the normal work of whole system needs to carry out the working index of modules real-time Monitoring, can analyzing failure cause, take corresponding safeguard measure rapidly.This fault monitoring system should cope with possibility The strong electromagnetic interference environment of appearance has stronger robustness.Because internal module is large number of, the monitoring of module status is answered When minimizing system bulk and additional communication equipment expense, communication bottom is taken in traditional T/R component faults monitoring and control It for the mode of Ethernet, needs to increase the additional network equipment, further increases the complexity of system, and when centralization is handed over It changes planes once being destroyed, the malfunction monitoring of all devices is paralysed.CAN bus can be supported effectively as a kind of fieldbus Distributed communication and real-time control have many advantages, such as connectable device mostly and strong interference immunity, and extendible ability is strong, is not required to simultaneously It wants additional equipment to support, is suitably applied equipment fault and is monitored and controlled in scene.

The present invention is based on ARM and FPGA architecture, propose a kind of fault monitoring method for being effectively directed to T/R component, The mode for taking CAN and Ethernet to combine on communication mode, it is internal that inducing classification is carried out to fault level, it is classified in guard method Setting, can complete the real-time monitoring and protection to T/R component, and state and fault message can be timely feedbacked to the aobvious control of host computer Platform.

Summary of the invention

The technical problem to be solved by the present invention is in view of the deficiencies of the prior art, propose a kind of pair of T/R component real-time monitoring With control guard method.

The method achieve the real time monitorings to TR component, to the real-time response of control command, and can position T/R event in time Easily and effectively human cost and time cost is greatly saved in barrier component, latch fault status information.In order to solve current difficulty Point, the present invention, which is used, carries out T/R components multiple in array antenna by monitoring bus based on arm processor and FPGA processor Failure and state collection, monitoring are recorded and are reported, and are classified to fault level, using second class protection Disposal Measures, realize T/ The control of R component is protected.Monitoring uses arm processor and FPGA processor framework with control module, can carry out to T/R component On-line real time monitoring, reports the failure and status information of T/R component in real time, and takes corresponding safeguard measure, avoids T/R group The damage of part, can quickly locate the failure of specific component in T/R component, and then quickly cope with problem, ensure entire The operation of system steadily.In order to reduce the influence in failure and status information transmission process by communication link fails, communicate Bottom, for the reliability for improving CAN bus, takes Redundancy Design, using complete two by the way of CAN and Ethernet CAN bus works at the same time, and when wherein a CAN bus breaks down, is able to carry out switching, system function is unaffected.

By ethernet communication between master control guarantor and host computer indication control board, with each T/R assembly module of junior and power module Between pass through CAN bus communicate.After completion self-test is protected in master control, if working condition is normal, the control life of host computer is waited always It enables, electrifying startup, operating mode selection including power supply and component；If operation irregularity, reporting fault information.Master control is protected successively All modules of poll junior obtain the working state index and fault message of each module, according to each module failure information and failure Coupled relation, analyzing failure cause judge whether to take second protection measure, obtained status information and fault message are sent To host computer.T/R component faults monitoring modular is made of ARM and FPGA, is communicated by the CAN interface of ARM with master control guarantor, FPGA It is communicated by UART interface and ARM.ARM is stored in iron by one group of phase initial correction code that serial ports inputs distal end interactive interface In electrical storage, phase initial correction code in ferroelectric memory is sent to FPGA when booting.ARM is from 6 IP of outside reading Location indication signal forms the local address of oneself.After completing self-test, ADC is capable of the working index of real-time acquisition component inside ARM, The working indexs such as the pulse current of T/R component, temperature, exciting power, output power, reflection power and voltage are monitored, FPGA can parse pulse width period signal to calculate pulse width, period and duty ratio, and pass through UART for these state indexs It is sent to ARM；ARM is by analyzing and determining, when monitoring index takes corresponding safeguard measure, the shape at storage current failure moment extremely State information.Information reporting is protected to master control when receiving master control and protecting polling order.The FPGA processor of component is responsible for wave beam control The operation of system and STC control.When wave beam controls, FPGA receives the phase initial correction code that ARM is sent, and it is total to receive outside 485 The serial phase shifting control message that line is sent into, message include phase shift code A, phase shift code B, frequency code and the signals such as enabled, will be parsed Phase shift code and respective frequencies phase initial correction code carry out subtraction, by obtained phase shifter control signal carry out string turn Union, and chronologically require that successively phase shifter control signal A and phase shifter control signal B are exported to phase shifter and controlled accordingly End processed, to complete wave beam control function；When STC is controlled, FPGA parses the STC curve data in adjustable attenuation message and deposits In internal register, STC curve data is 128 rank, 6 amplitude control codes, when STC access code changes, with pulsewidth week The failing edge of phase initial trigger signal is initial time, successively exports 128 rank amplitude control signals to numerical control by the interval of 3us Attenuator control terminal, to complete STC control function.Frequency synthesizer component internal ARM is in real time to 20 frequency multiplication states, crystal oscillator state, lock Phase source 1,2, power of phase locked source, two power, power amplifier output power, power amplifier temperature are monitored, the initial work of frequency synthesizer component Make in two operating modes, if detecting 2 failure of phase locked source or two power failures, phase locked source is controlled by GPIO and is opened It closes and realizes operating mode switching, start an operating mode.Large power supply is responsible for for three-phase 380V/50Hz alternating current being changed into Low-voltage DC, it is necessary to the electrical performance indexes of large power supply component are monitored, and take protection in the event of a failure Measure.The index of monitoring includes inputting/(protecting when overrate ± 10%) under proteciton, output over-voltage protection is (more than setting Protected when definite value+5%), output under-voltage protection (being protected when more than setting value -10%), output overcurrent protection (be more than rated current Current limliting when 10%, overcurrent protection when more than 15%) and overheating protection.When receiving the polling order of master control guarantor, by state and Fault information reporting is protected to master control.In addition, the switching on and shutting down of power supply have a distant control function, opening of receiving that indication control board issues is protected in master control After shutdown command, immediately passes through CAN bus and be transferred to power supply, realize remote control switch function.

The beneficial effects of the present invention are designing a kind of pair of T/R component faults guard method is monitored and controlled, component is real When respond failure, take safeguard measure time overhead to reach Millisecond, master control is protected to sub-ordinate components polling cycle down to 2 seconds, most The stabilization trouble free service of system is ensured to limits.The communication mode combined using CAN and Ethernet, reduces monitoring system Volume, cost and risk, take the mode of Redundancy Design, enhance the robustness of system.This method can be completed to T/R group The real-time monitoring and protection of part and other systems equipment, it is ensured that equipment is safe and reliable, be also beneficial to fault point and Determine failure cause.

Detailed description of the invention

Fig. 1 system structure diagram.

Fig. 2 inside modules functional schematic.

Specific embodiment

Master control protects processing unit and uses ARM architecture processor, and T/R component uses ARM+FPGA processor architecture, mainly relates to And Peripheral Interface have GPIO, IIC, UART, CAN, Ethernet, ADC.The state index of T/R component internal real-time monitoring has arteries and veins Rush electric current, temperature, exciting power, output power, reflection power, pulse voltage, pulse width period, pulse duty cycle.In the design ARM selects TM4C1294NCPDT chip, is mainly responsible for monitoring state index and takes control safeguard measure, the chip interior collection At Peripheral Interface abundant, meets the needs of data communication and protection control in system.FPGA selects XC6SLX9- 2CSG324I is mainly responsible for parsing pulse width period signal, obtains pulse width period and duty ratio index, is also responsible for completing wave beam control It is controlled with STC.

On internal system data interactive mode, by ethernet communication between master control guarantor and host computer indication control board, with junior It is communicated between each T/R assembly module and power module by CAN bus.CAN interface transmission rate uses 1Mbps bit rate, together When using ARM two controllers of CAN0 and CAN1, master control protect by CAN bus collect various components failure and state letter Breath, while master control is completed by CAN bus and protects the decentralization of decision, while establishing two-way CAN interface communication, improve CAN Communicate reliability.In internal monitoring and control circuit, GPIO can complete reading to low and high level and split inside ARM The on-off control function of pass, trouble light etc.；ADC module has 12 conversion accuracies, while going back a built-in temperature sensor, and 4 The sample sequence of a band buffering can carry out quick sampling to simulation input source without using controller.Each sample sequence hair The contents such as the raw device all priority of its input source of flexibly configurable, trigger event, the generation of interruption, sequencer.Make simultaneously Two ADC module of energy, by the way of ADC0 and ADC1 time-sharing multiplex, the sampling of achievable 16 tunnel simulation source, including pulse altogether Electric current, temperature, exciting power, output power and reflection power etc.；I2C can be configured to I2C0~I2C9 in piece, pass through I2C bus Read phase only pupil filter code word in ferroelectric memory；UART interface can be configured to UART0~UART7 in piece, realize phase by UART The input of position initial correction code and the interaction of ARM and FPGA data；Ethernet controller is by a fully-integrated media in piece Access controller and network physical interface device composition.Ethernet controller follows the specification of IEEE 802.3, supports completely 10base-T and 100BASE-TX standard, master control, which is protected, is transmitted to rear end for the failure of T/R component and status information by Ethernet Host computer, while passing through the control command of Ethernet reception host computer.FPGA is mainly responsible for parsing pulse width period signal, wave beam control The operation of system and STC control.XC6SLX9-2CSG324I is calculated pulse width, period and is accounted for by parsing pulse width period signal Empty ratio crosses pulsewidth or takes corresponding safeguard measure to avoid the damage of T/R component when crossing duty ratio；XC6SLX9-2CSG324I The control to phase shifter is realized by parsing serial phase shifting control message, realizes wave beam control function；XC6SLX9- 2CSG324I realizes the control to attenuator by parsing serial adjustable attenuation message, realizes STC control function.

Claims (3)

1. based on the control of the T/R component of ARM and FPGA architecture and monitoring method, it is characterised in that: monitored including master control guarantor's control, T/R component manipulates therefore inspection, frequency synthesizer manipulate therefore inspection and power supply therefore examine；Separate modular can carry out self-test and respond failure, in time Take self-shield measure；The status information and fault message that module collects modules at different levels by polling mode are protected in master control, complete event Barrier diagnosis, judges whether to take second protection measure, finally concentrates and reports information；Take this inquiry, real-time response, collection step by step Middle diagnosis, the control guard method uniformly reported, reduce the time overhead of module response failure to the maximum extent.

2. according to claim 1 based on the control of the T/R component of ARM and FPGA architecture and monitoring method, it is characterised in that: Control monitoring is protected in the master control are as follows: passes through each assembly module of ethernet communication and junior and power supply between host computer indication control board It is communicated between module by CAN bus；After completing self-test, if working condition is normal, the control command of host computer is waited always, Electrifying startup, operating mode selection including power supply and component；If operation irregularity, reporting fault information；Master control guarantor successively takes turns All modules of junior are ask, the working state index and fault message of each module are obtained, according to each module failure information and failure coupling Conjunction relationship, analyzing failure cause judge whether to take second protection measure, obtained status information and fault message are sent to Host computer.

3. according to claim 1 based on the control of the T/R component of ARM and FPGA architecture and monitoring method, it is characterised in that: The T/R component manipulates therefore detecting method are as follows: T/R component faults monitoring modular is made of ARM and FPGA, passes through the CAN interface of ARM Guarantor communicates with master control, and FPGA is communicated by UART interface and ARM；After completing self-test, ADC being capable of real-time acquisition component inside ARM Working index；FPGA can parse pulse width period signal to calculate pulse width, period and duty ratio, and by UART by this A little state indexs are sent to ARM；ARM is by analyzing and determining, when monitoring index takes corresponding safeguard measure, the current event of storage extremely Hinder the status information at moment；Information reporting is protected to master control when receiving master control and protecting polling order；FPGA parses serial phase shift Code word is controlled to control phase shifter, realizes wave beam control, serial adjustable attenuation code word is parsed and realizes STC control.