CN109001612A - The method and apparatus of signal wire S parameter in a kind of test pcb board - Google Patents
The method and apparatus of signal wire S parameter in a kind of test pcb board Download PDFInfo
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- CN109001612A CN109001612A CN201810552602.6A CN201810552602A CN109001612A CN 109001612 A CN109001612 A CN 109001612A CN 201810552602 A CN201810552602 A CN 201810552602A CN 109001612 A CN109001612 A CN 109001612A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
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Abstract
The embodiment of the present application provides a kind of method and device for testing signal wire S parameter in pcb board, which comprises calibration auxiliary cable and signal path；Test model topology is determined, according to topological structure test model connection signal channel；Test probe is connected with calibrated cable respectively, forms test terminal with PNA；It determines that test probe point location is set according to the position of test target on PCB tabula rasa, overall S parameter, test probe S parameter is measured according to topological structure, and save S parameter file；It goes embedding according to overall S parameter, test probe S parameter, determines the test waveform figure of test target S parameter；The test method and device that the application proposes, principle is simple, strong operability, total S parameter value of practical cabling in pcb board can not only be tested to obtain, unit S parameter can also be obtained by calculation, whether meet design object with the finished product that this verifies PCB stack-design and subsequent manufacture, it is also possible to the performance of the method combination simulating, verifying test probe.
Description
Technical field
The present invention relates to signal integrity technical fields, more particularly to a kind of side of signal wire S parameter in test pcb board
Method and device.
Background technique
As each bus communication speed of server is higher and higher, whether the characteristic impedance of their practical cablings in pcb board
Become abnormal important in accordance with design value.Moreover, the requirement to PCB material is also increasingly stringenter, and is in particular in actually to walk
The characteristic impedance of line and insertion loss.Therefore the practical manifestation of PCB signal lead is wanted to know about it is necessary to extract its S parameter and carry out
Analysis.
We are analyzed by the S parameter of the distinctive signal line (analog board interior cabling) of measurement edges of boards design at present, are believed
The specification of number line is identical with cabling practical in plate, but cannot embody the true environment of practical cabling in plate completely.Although also can
Specific loss situation of certain signal wire under certain frequency is obtained, but cannot reflect actual signal wired link whole chain under certain frequency
Path loss consumes situation, cannot reflect influence of the factors such as PCB via hole, ink to whole link.As it can be seen that current test method can only be tested
Demonstrate,prove certain class signal wire situations such as specific loss, is more verifying material property, cannot reflect actual signal cabling under certain frequency
Situations such as loss of whole link.Current test method can not extract the S parameter of the whole link of signal.
Therefore, a kind of method and apparatus for testing signal wire S parameter in pcb board are needed, can test to obtain real in pcb board
Total S parameter value of border cabling, the intuitive loss for reflecting the whole link of actual signal cabling, is current urgent problem to be solved.
Summary of the invention
In view of the deficiencies of the prior art, the present invention provides the methods and dress of signal wire S parameter in a kind of test pcb board
It sets, can test to obtain total S parameter value of practical cabling in pcb board, unit S parameter can also be obtained by calculation, tested with this
Whether card PCB stack-design and the finished product of subsequent manufacture meet design object, it is also possible to the test of the method combination simulating, verifying
The performance of probe.
In a first aspect, a kind of method for testing signal wire S parameter in pcb board is provided, the method includes
Calibration auxiliary cable and signal path；
Test model topology is determined, according to topological structure test model connection signal channel；
Test probe is connected with calibrated cable respectively, forms test terminal with PNA；
It determines that test probe point location is set according to the position of test target on PCB tabula rasa, totality S is measured according to topological structure
Parameter, test probe S parameter, and save S parameter file；
It goes embedding according to overall S parameter, test probe S parameter, determines the test waveform figure of test target S parameter.
With reference to first aspect, in the first possible implementation of the first aspect, the calibration auxiliary cable and letter
Number channel, comprising:
Test auxiliary cable is connected with PNA；
First signal path and third signal path are connected to E-CAL calibration module；
Measure is clicked in PNA display panel, VNA prompt is completed；
Above-mentioned behaviour successively is completed to the first signal path and second signal channel, the first signal path and fourth signal channel
Make.Auxiliary cable and four signal path calibrations are completed, the influence of cable and PNA is eliminated.
With reference to first aspect and its above-mentioned implementation, in the second possible implementation of the first aspect, described
Test model topology is determined, according to topological structure test model connection signal channel, comprising:
Determine BAL-BAL test model in PNA；
According to topological structure test model, successively by the first signal path and second signal channel, third signal path and
Fourth signal channel joins end to end.
With reference to first aspect and its above-mentioned implementation, in a third possible implementation of the first aspect, described
Test probe is connected with calibrated cable respectively, forms test terminal with PNA, comprising:
By two tests probe respectively with the first signal path/third signal path and second signal channel/fourth signal
The calibrated cable connection in channel.
With reference to first aspect and its above-mentioned implementation, in a fourth possible implementation of the first aspect, described
It determines that test probe point location is set according to the position of test target on PCB tabula rasa, overall S parameter is measured according to topological structure, is surveyed
Probe header S parameter, and save S parameter file, comprising:
According to the position of test target on PCB tabula rasa, the position at first and last end is determined, determine that probe point location is set with this；
A test target is surveyed with test probe point, crawl saves the wave file as SNP after picture waveform stabilization is shown in PNA
Format, i.e., overall S parameter file；
Two test probes are connected according to topological structure, test target is surveyed with test probe point, shows picture waveform in PNA
It is SNP format that crawl, which saves the wave file, after stabilization, i.e. test probe S parameter file.
With reference to first aspect and its above-mentioned implementation, in the fifth possible implementation of the first aspect, described
It goes embedding according to overall S parameter, test probe S parameter, determines the test waveform figure of test target S parameter, comprising:
According to overall S parameter, test probe S parameter with PLTS software carry AFR function go it is embedding, determine test target S join
Number test waveform figure.
With reference to first aspect and its above-mentioned implementation, in the sixth possible implementation of the first aspect, described
Method further include:
According to specific value and test target total length of the test target S parameter under certain frequency, confirm that PCB tabula rasa is practical
Cabling unit S parameter.
Second aspect provides a kind of for testing the device of signal wire S parameter in pcb board, comprising:
Calibration unit, the calibration unit is for calibrating auxiliary cable and signal path；
Determination unit, the determination unit connect according to topological structure test model and believe for determining test model topology
Number channel；
Connection unit, the connection unit are used to respectively connect test probe with calibrated cable, form and survey with PNA
Try terminal；
The determination unit is also used to determine that test probe point location is set according to the position of test target on PCB tabula rasa, root
Overall S parameter, test probe S parameter are measured according to topological structure, and saves S parameter file；
The determination unit is also used to go embedding according to overall S parameter, test probe S parameter, determines test target S parameter
Test waveform figure.
In conjunction with second aspect, in the first possible implementation of the second aspect, the calibration unit is specifically used for:
Test auxiliary cable is connected with PNA；
First signal path and third signal path are connected to E-CAL calibration module；
Measure is clicked in PNA display panel, VNA prompt is completed；
Above-mentioned behaviour successively is completed to the first signal path and second signal channel, the first signal path and fourth signal channel
Make.
It is in a second possible implementation of the second aspect, described in conjunction with second aspect and its above-mentioned implementation
Determination unit is specifically used for:
Determine BAL-BAL test model in PNA；
According to topological structure test model, successively by the first signal path and second signal channel, third signal path and
Fourth signal channel joins end to end.
It is in the third possible implementation of the second aspect, described in conjunction with second aspect and its above-mentioned implementation
Connection unit is specifically used for:
By two tests probe respectively with the first signal path/third signal path and second signal channel/fourth signal
The calibrated cable connection in channel.
It is in the fourth possible implementation of the second aspect, described in conjunction with second aspect and its above-mentioned implementation
Determination unit also particularly useful for:
According to the position of test target on PCB tabula rasa, the position at first and last end is determined, determine that probe point location is set with this；
A test target is surveyed with test probe point, crawl saves the wave file as SNP after picture waveform stabilization is shown in PNA
Format, i.e., overall S parameter file；
Two test probes are connected according to topological structure, test target is surveyed with test probe point, shows picture waveform in PNA
It is SNP format that crawl, which saves the wave file, after stabilization, i.e. test probe S parameter file.
It is in a fifth possible implementation of the second aspect, described in conjunction with second aspect and its above-mentioned implementation
Determination unit also particularly useful for:
According to overall S parameter, test probe S parameter with PLTS software carry AFR function go it is embedding, determine test target S join
Number test waveform figure.
It is in a fifth possible implementation of the second aspect, described in conjunction with second aspect and its above-mentioned implementation
Confirmation unit is also used to:
According to specific value and test target total length of the test target S parameter under certain frequency, confirm that PCB tabula rasa is practical
Cabling unit S parameter.
The third aspect provides a kind of controlled terminal, comprising:
Processor, memory, wherein
The memory is used to store computer program,
The processor from memory for calling and running the computer program, so that terminal device executes above-mentioned end
The method of end equipment.
Therefore, the test method and device that the application proposes, principle is simple, strong operability, can not only test to obtain PCB
Total S parameter value of practical cabling, can also be obtained by calculation unit S parameter in plate, with this verify PCB stack-design and after
Whether the finished product of continuous manufacture meets design object, it is also possible to the performance of the method combination simulating, verifying test probe.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, for those of ordinary skill in the art
Speech, without creative efforts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is the schematic flow chart of the method for the application one embodiment.
Fig. 2 is connection topology when the whole link totality S parameter of the application is tested.
Connection topology when Fig. 3 is the test of the application Fixture S parameter.
Fig. 4 is the schematic block diagram of the device of the application one embodiment.
Fig. 5 is SDD21 Wave data in the S parameter of the application FixtureA+FixtureB.
Fig. 6 is that the application test target S parameter goes embedding rear and goes embedding preceding waveform diagram.
Fig. 7 is a kind of structural schematic diagram of controlled terminal provided in an embodiment of the present invention.
Specific embodiment
Technical solution in order to enable those skilled in the art to better understand the present invention, below in conjunction with of the invention real
The attached drawing in example is applied, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described implementation
Example is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
Technical staff's every other embodiment obtained without making creative work, all should belong to protection of the present invention
Range.Technical solution in order to enable those skilled in the art to better understand the present invention, below in conjunction with of the invention real
The attached drawing in example is applied, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described implementation
Example is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
Technical staff's every other embodiment obtained without making creative work, all should belong to protection of the present invention
Range.
It should be understood that first, second of described in the text etc. is intended merely to refer to and distinguish different signals, instruction etc., wherein
The first, second equal restriction without sequencing.
The S parameter of coupon design lines can be tested with standard loss test probe, practical cabling is (following in palette
Realtrace first and last end) can not be designed as the pattern terminated that can pop one's head in standard loss.It would therefore be desirable to by real
Border lead cabling is drawn, therefore is tested probe and obtained test target using TDR testing impedance probe (hereinafter referred to as Fixture)
DUT (Device Under Test) S parameter.
Fig. 1 is the schematic flow chart of the method for the application one embodiment.Wherein, Fig. 1 executing subject can be one kind
For testing the device of signal wire S parameter in pcb board.
As shown in Figure 1, this method 100 includes:
Step 110, calibration auxiliary cable and signal path；
Step 120, test model topology is determined, according to topological structure test model connection signal channel；
Step 130, test probe is connected with calibrated cable respectively, forms test terminal with PNA；
Step 140, determine that test probe point location is set according to the position of test target on PCB tabula rasa, according to topological structure
Overall S parameter, test probe S parameter are measured, and saves S parameter file；
Step 150, it goes embedding according to overall S parameter, test probe S parameter, determines the test waveform of test target S parameter
Figure.
Optionally, as the application one embodiment, the calibration auxiliary cable and signal path, comprising:
Test auxiliary cable is connected with PNA；
First signal path 1 and third signal path 3 are connected to E-CAL calibration module；
Measure is clicked in PNA display panel, VNA prompt is completed；
Successively the first signal path 1 and second signal channel 2, the first signal path 1 and fourth signal channel 4 are completed
State operation.
Optionally, as the application one embodiment, the determining test model topology, according to topological structure test model
Connection signal channel, comprising:
Determine BAL-BAL test model in PNA；
According to topological structure test model, successively by the first signal path 1 and second signal channel 2, third signal path 3
It joins end to end with fourth signal channel 4.
Optionally, described to connect test probe with calibrated cable respectively as the application one embodiment, with
PNA composition test terminal, comprising:
Two test probes are believed with 1/ third signal path 3 of the first signal path and second signal channel 2/ the 4th respectively
The calibrated cable connection in number channel 4.
Optionally, as the application one embodiment, the position according to test target on PCB tabula rasa determines that test is visited
Head point location is set, and measures overall S parameter, test probe S parameter according to topological structure, and save S parameter file, comprising:
According to the position of test target on PCB tabula rasa, the position at first and last end is determined, determine that probe point location is set with this；
A test target is surveyed with test probe point, crawl saves the wave file as SNP after picture waveform stabilization is shown in PNA
Format, i.e., overall S parameter file；
Two test probes are connected according to topological structure, test target is surveyed with test probe point, shows picture waveform in PNA
It is SNP format that crawl, which saves the wave file, after stabilization, i.e. test probe S parameter file.
Optionally, described that embedding, determination is gone according to overall S parameter, test probe S parameter as the application one embodiment
The test waveform figure of test target S parameter, comprising:
According to overall S parameter, test probe S parameter with PLTS software carry AFR function go it is embedding, determine test target S join
Number test waveform figure.
Optionally, as the application one embodiment, the method also includes:
According to specific value and test target total length of the test target S parameter under certain frequency, confirm that PCB tabula rasa is practical
Cabling unit S parameter.
Fig. 2 shows connection topology when the test of whole link totality S parameter, company when Fig. 3 shows the test of Fixture S parameter
Connect topology.
Specific method includes the following steps:
(1) PNA is switched on, auxiliary cable and signal path is calibrated；
(2) selection selection BAL-BAL test model topology, communication channel select 1 and 3 pair 2 and 4；
(3) two TDR Test probe FixtureA is connected with calibrated cable respectively with FixtureB, is formed with PNA
Test terminal；The position of DUT is found on PCB tabula rasa；
(4) test topology structure according to Fig.2, carries out the overall S parameter test of DUT+FixtureA+FixtureB,
After waveform in PNA keeps stablizing, grabs and save as .SNP formatted file；
(5) the test probe Fixture S parameter that topological structure carries out FixtureA+FixtureB according to Fig.3, is surveyed
Examination grabs after waveform in PNA keeps stablizing and saves as .SNP formatted file；
(6) AFR function is carried with PLTS software go embedding, influence of the removal Fixture to test target DUT S parameter；
(7) in the test target DUT S parameter waveform after removal Fixture influences, check some S parameter in certain frequency
Under numerical value and preservation go it is embedding after S parameter file, can be completed test target DUT S parameter test.
It should be understood that the file grabbed in step (4) is the overall S parameter of DUT+FixtureA+FixtureB,
Contain the S parameter of two test probes (FixtureA and FixtureB).In step (5) (i.e. by two TDR Test probe
FixtureA and FixtureB) it is terminated in a manner of Fig. 3, connection type follows overall topology.Stabilization to be terminated and PNA
After display waveform is stablized, waveform SNP file is grabbed, so that it may obtain the S parameter information of two probes.Then according to overall S parameter,
The S parameters of two test probes obtain test target DUT S parameter, carry out embedding test result being made to be more in line with test target
The actual value of DUT makes probe influence to be preferably minimized.Go it is embedding after, so that it may obtain test target DUT S parameter data wave
Shape, we are checked the specific value of some DUT S parameter of test target under target frequency in going embedding rear waveform diagram, are verified with this
Whether PCB stack-design, production are qualified, and so far the S parameter test job of test target DUT is completed.
Fig. 4 shows the schematic block diagram of the device of the application one embodiment.
As shown in figure 4, the device 400 includes:
Calibration unit 410, the calibration unit is for calibrating auxiliary cable and signal path；
Determination unit 420, the determination unit are connected for determining test model topology according to topological structure test model
Signal path；
Connection unit 430, the connection unit is used to respectively connect test probe with calibrated cable, with PNA group
At test terminal；
The determination unit is also used to determine that test probe point location is set according to the position of test target on PCB tabula rasa, root
Overall S parameter, test probe S parameter are measured according to topological structure, and saves S parameter file；
The determination unit is also used to go embedding according to overall S parameter, test probe S parameter, determines test target S parameter
Test waveform figure.
Optionally, as the application one embodiment, the calibration unit 410 is specifically used for:
Test auxiliary cable is connected with PNA；
First signal path 1 and third signal path 3 are connected to E-CAL calibration module；
Measure is clicked in PNA display panel, VNA prompt is completed；
Successively the first signal path 1 and second signal channel 2, the first signal path 1 and fourth signal channel 4 are completed
State operation.
Optionally, as the application one embodiment, the determination unit 420 is specifically used for:
Determine BAL-BAL test model in PNA；
According to topological structure test model, successively by the first signal path 1 and second signal channel 2, third signal path 3
It joins end to end with fourth signal channel 4.
Optionally, as the application one embodiment, the connection unit 420 is specifically used for:
Two test probes are believed with 1/ third signal path 3 of the first signal path and second signal channel 2/ the 4th respectively
The calibrated cable connection in number channel 4.
Optionally, as the application one embodiment, the determination unit also particularly useful for:
According to the position of test target on PCB tabula rasa, the position at first and last end is determined, determine that probe point location is set with this；
A test target is surveyed with test probe point, crawl saves the wave file as SNP after picture waveform stabilization is shown in PNA
Format, i.e., overall S parameter file；
Two test probes are connected according to topological structure, test target is surveyed with test probe point, shows picture waveform in PNA
It is SNP format that crawl, which saves the wave file, after stabilization, i.e. test probe S parameter file.
Optionally, as the application one embodiment, the determination unit 420 also particularly useful for:
According to overall S parameter, test probe S parameter with PLTS software carry AFR function go it is embedding, determine test target S join
Number test waveform figure.
Optionally, as the application one embodiment, the confirmation unit 420 is also used to:
According to specific value and test target total length of the test target S parameter under certain frequency, confirm that PCB tabula rasa is practical
Cabling unit S parameter.
Fig. 5 shows SDD21 Wave data in the S parameter of FixtureA+FixtureB.
Fig. 6 shows that test target S parameter goes embedding rear and goes embedding preceding waveform diagram.Wherein, upper and lower two waveform diagrams are gone respectively
It is embedding after and go it is embedding before waveform diagram.
It is not satisfactory that Fig. 5, Fig. 6 can be seen that the test result in legend, and therefore, the test method and system can be with
Verifying used test probe (Fixture) if appropriate for do S parameter test or be only suitable for which frequency range carrying out test ability in
Obtain desired result.
Fig. 7 is a kind of structural schematic diagram of controlled terminal 700 provided in an embodiment of the present invention, which can be with
For executing the present processes.
Wherein, which may include: processor 710, memory 720 and communication unit 730.These components
It is communicated by one or more bus, it will be understood by those skilled in the art that the structure of server shown in figure is not
The restriction to the application is constituted, it is also possible to hub-and-spoke configuration either busbar network, can also include more than illustrating
Or less component, perhaps combine certain components or different component layouts.
Wherein, which can be used for executing instruction for storage processor 710, and memory 720 can be by any class
The volatibility or non-volatile memory device or their combination of type are realized, such as static random access memory (SRAM), electricity
Erasable Programmable Read Only Memory EPROM (EEPROM), Erasable Programmable Read Only Memory EPROM (EPROM), programmable read only memory
(PROM), read-only memory (ROM), magnetic memory, flash memory, disk or CD.When executing instruction in memory 720
When being executed by processor 710, so that terminal 700 some or all of is able to carry out in following above method embodiment step.
Processor 710 is the control centre for storing equipment, utilizes each of various interfaces and the entire electronic equipment of connection
A part by running or execute the software program and/or module that are stored in memory 720, and calls and is stored in storage
Data in device, to execute the various functions and/or processing data of electronic equipment.The processor can be by integrated circuit
(Integrated Circuit, abbreviation IC) composition, such as the IC that can be encapsulated by single are formed, can also be by more of connection
The encapsulation IC of identical function or different function and form.For example, processor 710 can only include central processing unit
(Central Processing Unit, abbreviation CPU).In the application embodiment, CPU can be single operation core, can also
To include multioperation core.
Communication unit 730, for establishing communication channel, so that the storage equipment be allow to be led to other equipment
Letter.Receive the user data or send user data to other equipment that other equipment are sent.
Therefore, the embodiment of the present application the utility model has the advantages that the application propose test method and device, principle is simple, operability
By force, the total S parameter value that can not only test to obtain practical cabling in pcb board, can also be obtained by calculation unit S parameter, with
Whether this verifying PCB stack-design and the finished product of subsequent manufacture meet design object.In addition, it is also possible to which the method combines emulation
The performance of validation test probe, the attainable technical effect of the present embodiment institute may refer to it is described above, it is no longer superfluous herein
It states.
It is required that those skilled in the art can be understood that the technology in the embodiment of the present application can add by software
The mode of general hardware platform realize.Based on this understanding, the technical solution in the embodiment of the present application substantially or
Say that the part that contributes to existing technology can be embodied in the form of software products, which is stored in
Such as USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory in one storage medium
The various media that can store program code such as (RAM, Random Access Memory), magnetic or disk, including it is several
Instruction is used so that a computer equipment (can be personal computer, server or the second equipment, the network equipment etc.) is held
Row all or part of the steps of the method according to each embodiment of the present invention.
Same and similar part may refer to each other between each embodiment in this specification.Implement especially for terminal
For example, since it is substantially similar to the method embodiment, so being described relatively simple, related place is referring in embodiment of the method
Explanation.
In several embodiments provided herein, it should be understood that disclosed systems, devices and methods, it can be with
It realizes by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the unit
It divides, only a kind of logical function partition, there may be another division manner in actual implementation, such as multiple units or components
It can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, it is shown or
The mutual coupling, direct-coupling or communication connection discussed can be through some interfaces, the indirect coupling of device or unit
It closes or communicates to connect, can be electrical property, mechanical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
In network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme
's.
It, can also be in addition, the functional units in various embodiments of the present invention may be integrated into one processing unit
It is that each unit physically exists alone, can also be integrated in one unit with two or more units.
Although by reference to attached drawing and combining the mode of preferred embodiment to the present invention have been described in detail, the present invention
It is not limited to this.Without departing from the spirit and substance of the premise in the present invention, those of ordinary skill in the art can be to the present invention
Embodiment carry out various equivalent modifications or substitutions, and these modifications or substitutions all should in covering scope of the invention/appoint
What those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, answer
It is included within the scope of the present invention.Therefore, protection scope of the present invention is answered described is with scope of protection of the claims
It is quasi-.
Claims (10)
1. a kind of method of signal wire S parameter in test pcb board characterized by comprising
Calibration auxiliary cable and signal path；
Test model topology is determined, according to topological structure test model connection signal channel；
Test probe is connected with calibrated cable respectively, forms test terminal with PNA；
It determines that test probe point location is set according to the position of test target on PCB tabula rasa, totality S ginseng is measured according to topological structure
Number, test probe S parameter, and save S parameter file；
It goes embedding according to overall S parameter, test probe S parameter, determines the test waveform figure of test target S parameter.
2. the method according to claim 1, wherein calibration auxiliary cable and signal path, comprising:
Test auxiliary cable is connected with PNA；
First signal path and third signal path are connected to E-CAL calibration module；
Measure is clicked in PNA display panel, VNA prompt is completed；
Aforesaid operations successively are completed to the first signal path and second signal channel, the first signal path and fourth signal channel.
3. method according to claim 1 or 2, which is characterized in that the determining test model topology, according to topological structure
Test model connection signal channel, comprising:
Determine BAL-BAL test model in PNA；
According to topological structure test model, successively by the first signal path and second signal channel, third signal path and the 4th
Signal path joins end to end.
4. according to the method in any one of claims 1 to 3, which is characterized in that it is described will test probe respectively and school
Quasi- cable connection forms test terminal with PNA, comprising:
By two tests probe respectively with the first signal path/third signal path and second signal channel/fourth signal channel
Calibrated cable connection.
5. method according to claim 1 to 4, which is characterized in that described according to test target on PCB tabula rasa
Position determine that a test probe point location is set, overall S parameter, test probe S parameter are measured according to topological structure, and save S ginseng
Number file, comprising:
According to the position of test target on PCB tabula rasa, the position at first and last end is determined, determine that probe point location is set with this；
A test target is surveyed with test probe point, crawl saves the wave file as SNP lattice after picture waveform stabilization is shown in PNA
Formula, i.e., overall S parameter file；
Two test probes are connected according to topological structure, test target is surveyed with test probe point, shows picture waveform stabilization in PNA
It is SNP format that crawl, which saves the wave file, afterwards, i.e. test probe S parameter file.
6. the method according to any one of claims 1 to 5, which is characterized in that described to be visited according to overall S parameter, test
Head S parameter is gone embedding, determines the test waveform figure of test target S parameter, comprising:
According to overall S parameter, test probe S parameter with PLTS software carry AFR function go it is embedding, determine test target S parameter survey
Try waveform diagram.
7. method according to any one of claim 1 to 6, which is characterized in that the method also includes:
According to specific value and test target total length of the test target S parameter under certain frequency, the practical cabling of PCB tabula rasa is confirmed
Unit S parameter.
8. a kind of device for for testing signal wire S parameter in pcb board characterized by comprising
Calibration unit, the calibration unit is for calibrating auxiliary cable and signal path；
Determination unit, the determination unit are logical according to topological structure test model connection signal for determining test model topology
Road；
Connection unit, the connection unit are used to respectively connect test probe with calibrated cable, form test eventually with PNA
End；
The determination unit is also used to determine that a test probe point location is set according to the position of test target on PCB tabula rasa, according to opening up
Structure measurement totality S parameter, test probe S parameter are flutterred, and saves S parameter file；
The determination unit is also used to go embedding according to overall S parameter, test probe S parameter, determines the test of test target S parameter
Waveform diagram.
9. device according to claim 8, which is characterized in that the calibration unit is specifically used for:
Test auxiliary cable is connected with PNA；
First signal path and third signal path are connected to E-CAL calibration module；
Measure is clicked in PNA display panel, VNA prompt is completed；
Aforesaid operations successively are completed to the first signal path and second signal channel, the first signal path and fourth signal channel.
10. device according to claim 8 or claim 9, which is characterized in that the determination unit is specifically used for:
The determination unit is specifically used for:
Determine BAL-BAL test model in PNA,
According to topological structure test model, successively by the first signal path and second signal channel, third signal path and the 4th
Signal path joins end to end；
By two tests probe respectively with the first signal path/third signal path and second signal channel/fourth signal channel
Calibrated cable connection,
According to the position of test target on PCB tabula rasa, the position at first and last end is determined, determine that probe point location is set with this,
A test target is surveyed with test probe point, crawl saves the wave file as SNP lattice after picture waveform stabilization is shown in PNA
Formula, i.e., overall S parameter file；
Two test probes are connected according to topological structure, test target is surveyed with test probe point, shows picture waveform stabilization in PNA
It is SNP format that crawl, which saves the wave file, afterwards, i.e. test probe S parameter file；
According to overall S parameter, test probe S parameter with PLTS software carry AFR function go it is embedding, determine test target S parameter survey
Try waveform diagram；
According to specific value and test target total length of the test target S parameter under certain frequency, the practical cabling of PCB tabula rasa is confirmed
Unit S parameter.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110441628A (en) * | 2019-07-29 | 2019-11-12 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | High speed connector performance test methods, apparatus and system |
| CN111929558A (en) * | 2020-09-28 | 2020-11-13 | 浙江铖昌科技有限公司 | Self-calibration-based de-embedding method, system, storage medium and terminal |
| CN112345912A (en) * | 2020-09-25 | 2021-02-09 | 曙光信息产业(北京)有限公司 | Material characteristic testing method and device, electronic equipment and storage medium |
| CN112416690A (en) * | 2020-12-09 | 2021-02-26 | 海光信息技术股份有限公司 | Integrated mainboard for testing and testing device |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005058482A1 (en) * | 2005-01-03 | 2006-07-13 | Agilent Technologies, Inc. (n.d.Ges.d.Staates Delaware), Palo Alto | Multi-well calibration simplification using the "unknown-pass" method |
| CN101093237A (en) * | 2006-06-21 | 2007-12-26 | 中兴通讯股份有限公司 | Method and system for measuring echo return loss in Ethernet |
| CN103063999A (en) * | 2012-12-21 | 2013-04-24 | 上海宏力半导体制造有限公司 | De-embedding method |
| CN104297597A (en) * | 2014-10-20 | 2015-01-21 | 中国电子科技集团公司第四十一研究所 | New method for testing clamp effect in dual-port-removed network |
| CN104849585A (en) * | 2015-04-16 | 2015-08-19 | 中国电子科技集团公司第四十一研究所 | System and method for optical device S parameter measurement based on vector network analyzer |
| CN105137196A (en) * | 2015-08-25 | 2015-12-09 | 浪潮电子信息产业股份有限公司 | Simple SAS and SATA signal routing impedance test method |
| CN106911404A (en) * | 2017-03-08 | 2017-06-30 | 中国空间技术研究院 | A kind of method of testing of the transponder channel frequence response based on arrow net |
| CN106933723A (en) * | 2017-03-10 | 2017-07-07 | 郑州云海信息技术有限公司 | A kind of measurement result storage method for being applied to Network Analyzer |
| CN206523565U (en) * | 2017-03-04 | 2017-09-26 | 郑州云海信息技术有限公司 | USB Channel depletion measurement jigs |
| CN107861050A (en) * | 2017-11-13 | 2018-03-30 | 中国电子科技集团公司第四十研究所 | A kind of method that On-wafer measurement is carried out using vector network analyzer |
| CN107884626A (en) * | 2017-12-30 | 2018-04-06 | 贵州师范大学 | A kind of S parameter automatic measurement method based on fissipation factor |
| CN107943641A (en) * | 2017-11-16 | 2018-04-20 | 郑州云海信息技术有限公司 | A kind of method and device for generating multiport S parameter document |
-
2018
- 2018-05-31 CN CN201810552602.6A patent/CN109001612A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005058482A1 (en) * | 2005-01-03 | 2006-07-13 | Agilent Technologies, Inc. (n.d.Ges.d.Staates Delaware), Palo Alto | Multi-well calibration simplification using the "unknown-pass" method |
| CN101093237A (en) * | 2006-06-21 | 2007-12-26 | 中兴通讯股份有限公司 | Method and system for measuring echo return loss in Ethernet |
| CN103063999A (en) * | 2012-12-21 | 2013-04-24 | 上海宏力半导体制造有限公司 | De-embedding method |
| CN104297597A (en) * | 2014-10-20 | 2015-01-21 | 中国电子科技集团公司第四十一研究所 | New method for testing clamp effect in dual-port-removed network |
| CN104849585A (en) * | 2015-04-16 | 2015-08-19 | 中国电子科技集团公司第四十一研究所 | System and method for optical device S parameter measurement based on vector network analyzer |
| CN105137196A (en) * | 2015-08-25 | 2015-12-09 | 浪潮电子信息产业股份有限公司 | Simple SAS and SATA signal routing impedance test method |
| CN206523565U (en) * | 2017-03-04 | 2017-09-26 | 郑州云海信息技术有限公司 | USB Channel depletion measurement jigs |
| CN106911404A (en) * | 2017-03-08 | 2017-06-30 | 中国空间技术研究院 | A kind of method of testing of the transponder channel frequence response based on arrow net |
| CN106933723A (en) * | 2017-03-10 | 2017-07-07 | 郑州云海信息技术有限公司 | A kind of measurement result storage method for being applied to Network Analyzer |
| CN107861050A (en) * | 2017-11-13 | 2018-03-30 | 中国电子科技集团公司第四十研究所 | A kind of method that On-wafer measurement is carried out using vector network analyzer |
| CN107943641A (en) * | 2017-11-16 | 2018-04-20 | 郑州云海信息技术有限公司 | A kind of method and device for generating multiport S parameter document |
| CN107884626A (en) * | 2017-12-30 | 2018-04-06 | 贵州师范大学 | A kind of S parameter automatic measurement method based on fissipation factor |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110441628A (en) * | 2019-07-29 | 2019-11-12 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | High speed connector performance test methods, apparatus and system |
| CN112345912A (en) * | 2020-09-25 | 2021-02-09 | 曙光信息产业(北京)有限公司 | Material characteristic testing method and device, electronic equipment and storage medium |
| CN111929558A (en) * | 2020-09-28 | 2020-11-13 | 浙江铖昌科技有限公司 | Self-calibration-based de-embedding method, system, storage medium and terminal |
| CN111929558B (en) * | 2020-09-28 | 2021-01-15 | 浙江铖昌科技股份有限公司 | Self-calibration-based de-embedding method, system, storage medium and terminal |
| CN112416690A (en) * | 2020-12-09 | 2021-02-26 | 海光信息技术股份有限公司 | Integrated mainboard for testing and testing device |
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