CN108988797B - Low noise amplifier and electronic device - Google Patents
Low noise amplifier and electronic device Download PDFInfo
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- CN108988797B CN108988797B CN201810609088.5A CN201810609088A CN108988797B CN 108988797 B CN108988797 B CN 108988797B CN 201810609088 A CN201810609088 A CN 201810609088A CN 108988797 B CN108988797 B CN 108988797B
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- 239000003990 capacitor Substances 0.000 claims description 16
- 230000001939 inductive effect Effects 0.000 claims description 13
- 230000002708 enhancing effect Effects 0.000 claims description 7
- 230000003139 buffering effect Effects 0.000 claims description 4
- 230000000903 blocking effect Effects 0.000 claims 1
- 239000000872 buffer Substances 0.000 abstract description 5
- 230000003014 reinforcing effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
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- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
- H03F3/16—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
- H03F3/165—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices with junction-FET's
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
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Abstract
The embodiment of the application provides a low noise amplifier and electronic equipment, and the low noise amplifier includes: input, output, common source unit, common gate unit, input impedance matching unit, output impedance matching unit, gain enhancement unit is used for to load through the input voltage of input impedance matching unit strengthens the processing, common source unit is used for converting the input voltage after the reinforcing into input current, common gate unit is used for right input current buffers, and right the output voltage of output with input voltage keeps apart, input impedance unit does the equivalent impedance of input, output impedance matching does the equivalent impedance of output has higher current efficiency and good input/output matching.
Description
Technical Field
The embodiment of the application relates to the technical field of circuits, in particular to a low-noise amplifier and electronic equipment.
Background
Low-noise amplifier (LNA) is mainly used in a communication system to amplify a signal received from an antenna for processing by a subsequent electronic device. Since the signal from the antenna is typically very weak, the low noise amplifier is typically located very close to the antenna to reduce the loss of the signal through the transmission line.
Since the lna is located in the first stage of the whole receiver in close proximity to the antenna, its characteristics directly affect the quality of the received signal of the whole receiver. To ensure that the signal received by the antenna is correctly recovered at the final stage of the receiver, a good low noise amplifier needs to amplify the signal while producing as little noise and distortion as possible.
However, the existing low noise amplifier has technical defects to be improved, such as low current efficiency or poor input/output matching.
Disclosure of Invention
Accordingly, one of the technical problems to be solved by the embodiments of the present application is to provide a low noise amplifier and an electronic device, so as to overcome or alleviate the above technical drawbacks in the prior art.
The embodiment of the application provides a low noise amplifier, it includes: the input end, the output end, the common source unit, the common gate unit, the input impedance matching unit, the output impedance matching unit and the gain enhancement unit, the gain enhancement unit is used for enhancing the input voltage loaded to the input impedance matching unit through the input end, the common source unit is used for converting the enhanced input voltage into the input current, the common gate unit is used for buffering the input current and isolating the output voltage of the output end from the input voltage, the input impedance unit is the equivalent impedance of the input end, and the output impedance matching is the equivalent impedance of the output end.
The embodiment of the application also provides electronic equipment which comprises the low noise amplifier. Such as an intelligent terminal or server.
In the technical solution provided in the embodiment of the present application, the low noise amplifier includes: the input end, output end, common source unit, common grid unit, input impedance matching unit, output impedance matching unit, gain enhancement unit is used for carrying out enhancement processing to the input voltage that loads to input impedance matching unit through the input end, common source unit is used for converting the input voltage after the reinforcing into input current, common grid unit is used for right input current buffers, and right the output voltage of output end with input voltage keeps apart, input impedance unit is the equivalent impedance of input end, output impedance matching is the equivalent impedance of output end, has higher current efficiency and good input-output matching.
Drawings
Some specific embodiments of the present application will be described in detail hereinafter by way of illustration and not limitation with reference to the accompanying drawings. The same reference numbers in the drawings identify the same or similar elements or components. Those skilled in the art will appreciate that the drawings are not necessarily drawn to scale. In the drawings:
fig. 1 is a schematic structural diagram of a low noise amplifier according to an embodiment of the present application;
FIG. 2 is a schematic structural diagram of a second LNA in accordance with an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a medium-low noise amplifier according to a third embodiment of the present application.
Detailed Description
It is not necessary for any particular embodiment of the invention to achieve all of the above advantages at the same time.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
In order to make those skilled in the art better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application shall fall within the scope of the protection of the embodiments in the present application.
The following further describes specific implementations of embodiments of the present application with reference to the drawings of the embodiments of the present application.
Fig. 1 is a schematic structural diagram of a low noise amplifier according to an embodiment of the present application; in this embodiment, a description will be given taking an example in which the low noise amplifier can realize a function equivalent to that of the low noise amplifier alone.
Referring to fig. 1, the low noise amplifier includes: the first common source unit is used for converting an input voltage Vi into an input current, the first common gate unit is used for buffering the input current and isolating an output voltage Vo of the first output end from the first input voltage, the first input impedance unit is an equivalent impedance of the first input end, and the output impedance is matched with the equivalent impedance of the output end.
Optionally, in any embodiment of the present application, a first end of the first common source unit is connected to a second end of the first common gate unit, a second end of the first common gate unit is connected to the first output impedance matching unit, and a third end of the first common source unit is connected to the first voltage Vdd.
Optionally, in any embodiment of the present application, the third terminal of the first common gate unit is connected to a first voltage.
In a specific application scenario, the first common-source cell is the second NMOS transistor M0, and the first common-gate cell is the first NMOS transistor M1. Referring to fig. 1 again, the first ends of the first NMOS transistor and the second NMOS transistor are drain ends, the second ends of the first NMOS transistor and the second NMOS transistor are source ends, and the third ends of the first NMOS transistor and the second NMOS transistor are gate ends.
Meanwhile, in this specific application scenario, the first input impedance matching unit includes: a first equivalent inductance L1 and a second equivalent inductance L2; the second output impedance matching unit includes: a zeroth equivalent inductance L0 and a zeroth equivalent capacitance C0.
Based on the specific type selection of the devices in the specific application scenario, the connection relationship of each device is as follows:
the source end of the first NMOS tube is connected with the drain end of the second NMOS unit, the drain end of the first NMOS tube is connected with the first output impedance matching unit, and the gate end of the first NMOS tube is connected with the first voltage Vdd. Specifically, the drain terminal of the first NMOS transistor is connected to the zeroth equivalent inductor L0 in the first output impedance matching unit, and further connected to the first voltage Vdd through the zeroth equivalent inductor L0 in the first output impedance matching unit, and the gate terminal of the first NMOS transistor is connected to the first voltage Vdd. Specifically, one end of the zeroth equivalent inductor L0 is connected to the first voltage Vdd, and the other end is connected to the drain of the first NMOS transistor. One end of the zeroth equivalent capacitor C0 is connected to the drain of the first NMOS transistor, and the other end of the zeroth equivalent capacitor C0 is used as a first output end for transmitting a first output voltage Vo, i.e., an output voltage of the first output end.
The source end of the second NMOS tube is connected with the first input impedance matching unit, and the gate end of the second NMOS tube is connected with an input voltage Vi through the first input impedance matching unit. Specifically, the source end of the second NMOS transistor is connected to the second equivalent inductor L2 in the first input impedance matching unit, and the gate end of the second NMOS transistor is connected to the input voltage Vi through the first equivalent inductor L1 in the first input impedance matching unit.
For the circuit of fig. 1 described above, the following relationship exists:
Av＝gmn*ZL
in the above formula (1), gmn represents transconductance of the second NMOS transistor, Av represents voltage gain of the whole circuit, ZL represents capacitance reactance of the zeroth equivalent capacitor, un represents mobility of the second NMOS transistor, cox represents oxide layer parameter of the second NMOS transistor, W/L represents width-to-length ratio of the second NMOS transistor, and Id represents current of the second NMOS transistor.
In the circuit structure shown in the embodiment of fig. 1, the first common source unit is configured to convert an input voltage Vi into an input current, the first common gate unit is configured to buffer the input current and isolate an output voltage Vo of the first output terminal from the first input voltage, the first input impedance unit is an equivalent impedance of the first input terminal, and the output impedance is matched with the equivalent impedance of the output terminal, so that input/output impedance matching is better achieved, and meanwhile, noise is low.
FIG. 2 is a schematic structural diagram of a second LNA in accordance with an embodiment of the present invention; in this embodiment, a description will be given taking an example in which the low noise amplifier can realize a function equivalent to that of the low noise amplifier alone.
Referring to fig. 2, the low noise amplifier includes a second common source unit, a second common gate unit, a second input impedance matching unit, and a second output impedance matching unit, where the second common source unit is configured to convert an input voltage Vi into an input current, the second common gate unit is configured to buffer the input current and isolate an output voltage Vo of the output terminal from the input voltage, the second input impedance unit is an equivalent impedance of the input terminal, and the output impedance matching is an equivalent impedance of the output terminal.
Specifically, in this embodiment, a first end of the second common-source unit is connected to the first end of the second common-gate unit, a second end of the second common-source unit is grounded, and a third end of the second common-source unit is connected to the input voltage.
Specifically, in this embodiment, the second terminal of the second common-gate unit is connected to the first voltage Vdd, and the third terminal of the second common-gate unit is connected to the third terminal of the second common-source unit. In addition, the circuit shown in fig. 2 is further provided with a feedback resistor R1, and the feedback resistor R1 is spanned between the gate terminal and the drain terminal of the second PMOS transistor and the second NMOS transistor.
In a specific application scenario, the second common-source unit is a third NMOS transistor M0, the second common-gate unit is a fourth PMOS transistor M1, a first end of the third NMOS transistor is a drain terminal, a second end of the third NMOS transistor is a source terminal, a third end of the third NMOS transistor is a gate terminal, a first end of the fourth PMOS transistor is a drain terminal, a second end of the third NMOS transistor is a source terminal, and a third end of the third NMOS transistor is a gate terminal. The drain terminal of the third NMOS tube is connected with the drain terminal of the fourth PMOS tube, the source terminal of the third NMOS tube is grounded, and the gate terminal of the third NMOS tube is connected with the input voltage Vi.
The second input impedance matching unit comprises a first equivalent inductor L1, the second output impedance matching unit comprises a zero equivalent capacitor C0, the gate terminal of the third NMOS is connected with the input voltage Vi through the first equivalent inductor L1, and the drain terminal of the fourth PMOS forms the output terminal and transmits the output voltage Vo through the zero equivalent capacitor C0. It should be noted that, although the reference numerals of the first equivalent inductor L1 included in the second input impedance matching unit and the reference numeral of the zeroth equivalent capacitor C0 included in the second output impedance matching unit are the same as those of the related devices in fig. 1, they do not necessarily represent the same impedance values or the same devices.
For the circuit of fig. 1 described above, the following relationship exists:
Av＝(gmn+gmp)*ZL
in the above formula (2), gmp represents transconductance of the fourth PMOS transistor, gmn represents transconductance of the third NMOS transistor, Av represents voltage gain of the whole circuit, ZL represents impedance of a feedback resistor, up represents mobility of the fourth PMOS transistor, cox "represents an oxide layer parameter of the fourth PMOS transistor, W/L" represents a width-to-length ratio of the fourth PMOS transistor, and Id "represents current of the fourth PMOS transistor. un represents the mobility of the third NMOS tube, cox ' represents the oxide layer parameter of the third NMOS tube, W/L ' represents the width-to-length ratio of the third NMOS tube, and Id ' represents the current of the third NMOS tube.
In the embodiment shown in fig. 2, in comparison with the above formula (2), since the second common-source unit is used to convert the input voltage Vi into the input current, the second common-gate unit is used to buffer the input current and isolate the output voltage Vo of the output terminal from the input voltage, the second input impedance unit is the equivalent impedance of the input terminal, and the output impedance is matched with the equivalent impedance of the output terminal, so that higher current efficiency can be achieved.
FIG. 3 is a schematic structural diagram of a low/medium noise amplifier according to a third embodiment of the present application; as shown in fig. 3, in the present embodiment, the low noise amplifier includes: the input end, the output end, a third common source unit, a third common gate unit, a third input impedance matching unit, a third output impedance matching unit and a gain enhancement unit, wherein the gain enhancement unit is used for enhancing the input voltage loaded to the third input impedance matching unit through the input end, the third common source unit is used for converting the enhanced input voltage into the input current, the third common gate unit is used for buffering the input current and isolating the output voltage of the output end from the input voltage, the input impedance unit is the equivalent impedance of the input end, and the output impedance matching is the equivalent impedance of the output end.
In this embodiment, the second end of the third common-gate unit is connected to the first end of the third common-source unit, the first end of the third common-gate unit is connected to the third output impedance matching unit, and the third end of the third common-source unit is connected to the first voltage Vdd.
In this embodiment, a second end of the third common-source unit is connected to the third input impedance matching unit, and a third end of the third common-source unit is connected to the gain enhancement unit.
In this embodiment, the third input impedance matching unit is connected to the third terminal of the third common-source unit through a second capacitor.
In a specific application scenario, the third common-gate unit is a fifth NMOS transistor M1, and the third common-source unit is a sixth NMOS transistor M0. And the first ends of the fifth NMOS tube and the sixth NMOS tube are drain ends, the second ends are source ends, and the third ends are grid ends. .
In this embodiment, a source terminal of the fifth NMOS transistor is connected to a drain terminal of the sixth NMOS transistor, a drain terminal of the fifth NMOS transistor is connected to the third output impedance matching unit, and a gate terminal of the fifth NMOS transistor is connected to the first voltage Vdd.
In this embodiment, a source end of the sixth NMOS transistor is connected to the third input impedance matching unit, and a gate end of the sixth NMOS transistor is connected to the gain enhancing unit.
In this embodiment, the gain enhancement unit includes: the third capacitor C3, the first resistor R1, and the amplifying tube M3, where the third capacitor C3 and the first resistor R1 are both connected to a third end (e.g., a gate end) of the amplifying tube M3(PMOS tube), a second end (e.g., a source end) of the amplifying tube is electrically connected to the second voltage VDD, and a first end (e.g., a drain end) of the amplifying tube is connected to a second end (e.g., a source end) of the fifth NMOS tube. Meanwhile, the third capacitor C3 is connected to the first equivalent inductive reactance L1 and the second capacitor C2.
In this embodiment, the third input impedance matching unit is connected to the gate terminal of the sixth NMOS through a second capacitor C2.
In this embodiment, the third output impedance matching unit includes a zero equivalent inductive reactance L0 and a zero equivalent capacitive reactance C0, one end of the zero equivalent inductive reactance is connected to the drain of the fifth NMOS transistor, the other end of the zero equivalent inductive reactance is connected to the first voltage Vdd, one end of the zero equivalent capacitive reactance is connected to the drain of the fifth NMOS transistor, and the other end of the zero equivalent capacitive reactance is used as an output end for outputting the voltage Vo.
In this embodiment, the third input impedance matching unit includes a first equivalent inductive reactance L1 and a second equivalent inductive reactance L2, the first equivalent inductive reactance is connected to the gate terminal of the sixth NMOS transistor, and the second equivalent inductive reactance is connected to the source terminal of the sixth NMOS transistor.
For the circuit of fig. 3 described above, the following relationship exists:
Av＝(gmn+gmp)*ZL
in the above formula (3), gmn represents the transconductance of the fifth NMOS transistor, gmp represents the transconductance of the amplifier transistor M3, Av represents the voltage gain of the whole circuit, ZL represents the impedance of the feedback resistor, un represents the mobility of the fifth NMOS transistor, cox ' represents the oxide layer parameter of the fifth NMOS transistor, W/L ' represents the width-to-length ratio of the fifth NMOS transistor, and Id ' represents the current of the fifth NMOS transistor. Up represents the mobility of the amplifier tube M3, cox "represents the oxide layer parameter of the amplifier tube M3, W/L" represents the width-to-length ratio of the amplifier tube M3, and Id "represents the current of the amplifier tube M3.
Referring to the above equation (3), compared to the circuit structures of fig. 1 and 2, the circuit structure of fig. 3 combines the structures of the circuits of fig. 1 and 2, and can achieve better input/output impedance matching and higher current efficiency.
The above-described embodiments of the apparatus are merely illustrative, and the modules described as separate components may or may not be physically separate, and the components displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the embodiments of the present application, and are not limited thereto; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (8)
1. A low noise amplifier, comprising: the input impedance matching circuit comprises an input end, an output end, a common source unit, a common grid unit, an input impedance matching unit, an output impedance matching unit and a gain enhancing unit, wherein the gain enhancing unit is used for enhancing input voltage loaded to the input impedance matching unit through the input end, the common source unit is used for converting the enhanced input voltage into input current, the common grid unit is used for buffering the input current and isolating the output voltage of the output end from the input voltage, the input impedance unit is equivalent impedance of the input end, and the output impedance matching is equivalent impedance of the output end; wherein the gain enhancing unit comprises: one end of the third capacitor and one end of the first resistor are both connected with the grid end of the amplifier tube, the other end of the first resistor is connected with the ground, the other end of the third capacitor is connected with the input end of the common source unit, the source end of the amplifier tube is electrically connected with a second voltage, and the drain end of the amplifier tube is connected with the connection node of the common source unit and the common grid unit; the third capacitor is used for blocking direct current, the first resistor is used for dividing voltage, and the amplifying tube is used for amplifying.
2. The lna of claim 1, wherein the first terminal of the common gate unit is connected to the first terminal of the common source unit, the second terminal of the common gate unit is connected to the output impedance matching unit, and the third terminal of the common gate unit is connected to a second voltage.
3. The low noise amplifier of claim 1, wherein the second terminal of the common source unit is connected to the input impedance matching unit, and the third terminal of the common source unit is connected to the gain enhancement unit.
4. The low noise amplifier of claim 1, wherein the common source unit is an NMOS transistor.
5. The low noise amplifier of claim 1, wherein the input impedance matching unit is connected to the third terminal of the common source unit through a second capacitor.
6. The low noise amplifier of claim 1, wherein the input impedance matching unit comprises a first equivalent inductive reactance connected to the third terminal of the common source unit and a second equivalent inductive reactance connected to the second terminal of the common source unit.
7. The lna of claim 1, wherein the output impedance matching unit comprises a zeroth equivalent inductive reactance and a zeroth equivalent capacitive reactance, one end of the zeroth equivalent inductive reactance is connected to the second end of the common gate unit, the other end of the zeroth equivalent inductive reactance is connected to the second voltage, one end of the zeroth equivalent capacitive reactance is connected to the second end of the common gate unit, and the other end of the zeroth equivalent capacitive reactance is used as the output end.
8. An electronic device comprising a low noise amplifier according to any one of claims 1 to 7.
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| US20180123523A1 (en) * | 2016-10-27 | 2018-05-03 | Qualcomm Incorporated | Low gain linearization for high signal-to-noise ratio |
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| CN102394571A (en) * | 2011-10-28 | 2012-03-28 | 电子科技大学 | In-chip integrated low noise amplifier |
| CN102497167A (en) * | 2011-12-09 | 2012-06-13 | 电子科技大学 | Radio-frequency ultra-wideband low-noise amplifier based on inductance compensation |
| CN104158497A (en) * | 2013-05-14 | 2014-11-19 | 上海华虹宏力半导体制造有限公司 | Low noise amplifier |
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Address after: Room 1201, No.2, Lane 908, Xiuwen Road, Minhang District, Shanghai, 201199 Patentee after: SHANGHAI AWINIC TECHNOLOGY Co.,Ltd. Country or region after: China Address before: Room 303-39, building 33, 680 Guiping Road, Xuhui District, Shanghai 200233 Patentee before: SHANGHAI AWINIC TECHNOLOGY Co.,Ltd. Country or region before: China |