CN108986758B - Power-on time sequence control circuit, driving method thereof, printed circuit board and display panel - Google Patents
Power-on time sequence control circuit, driving method thereof, printed circuit board and display panel Download PDFInfo
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- CN108986758B CN108986758B CN201810810868.6A CN201810810868A CN108986758B CN 108986758 B CN108986758 B CN 108986758B CN 201810810868 A CN201810810868 A CN 201810810868A CN 108986758 B CN108986758 B CN 108986758B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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Abstract
The invention discloses a power-on time sequence control circuit, a driving method thereof, a printed circuit board and a display panel, comprising the following steps: the device comprises a first control module, a second control module and a boosting module; the first control module is used for generating a power supply control signal of a power supply control signal end according to a first control signal of the first control signal end and generating a digital voltage signal of a digital voltage signal end at the same time; the second control module is respectively connected with the power supply control signal end and the power supply voltage signal end and is used for generating a power supply voltage signal of the power supply voltage signal end according to the power supply control signal of the power supply control signal end; the boosting module is respectively connected with the power supply voltage signal end and the analog voltage signal end and is used for generating an analog voltage signal of the analog voltage signal end according to the power supply voltage signal of the power supply voltage signal end. Because the digital voltage signal is started before the analog voltage signal in the invention, the image abnormal fault caused by the power-on time sequence in the prior art is effectively improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a power-on time sequence control circuit, a driving method thereof, a printed circuit board and a display panel.
Background
Liquid Crystal Display (LCD) panels have low power consumption, low radiation, low manufacturing cost, and the like, and are widely used in various electronic devices, such as displays, televisions, mobile phones, and digital cameras.
The power-on timing parameters are particularly important because the power-on timing directly affects whether the lcd panel is operating normally. Specifically, in an analog voltage signal (AVDD) and a digital voltage signal (DVDD) as power-on timing parameters, the AVDD is used to generate a reference voltage for a gamma (gamma) circuit chip, and the DVDD is used to provide a digital circuit operating voltage for a timing-control (timing-control) circuit chip, a source (source) driving circuit chip, and a gamma circuit chip. In the prior art, the AVDD is obtained by boosting a power supply voltage signal (Panel _ VCC) through a power management system chip (PMU IC), and the DVDD is obtained by stepping down the Panel _ VCC through a low dropout regulator (LDO), so that the DVDD is delayed a little from a start position of a rising edge of the AVDD, that is, the AVDD is started before the DVDD. However, if the AVDD is first activated and the DVDD is not yet activated, the gamma circuit chip is not yet activated, and the AVDD provides the reference voltage signal, which may cause the gamma circuit chip to malfunction, thereby causing various image abnormalities.
Disclosure of Invention
The embodiment of the invention provides a power-on time sequence control circuit, a driving method thereof, a printed circuit board and a display panel, which are used for improving the image abnormal fault caused by the power-on time sequence.
The embodiment of the invention provides a power-on time sequence control circuit, which comprises: the device comprises a first control module, a second control module and a boosting module;
the first control module is respectively connected with a first control signal end, a power supply control signal end and a digital voltage signal end and is used for generating a power supply control signal of the power supply control signal end according to a first control signal of the first control signal end and generating a digital voltage signal of the digital voltage signal end at the same time;
the second control module is respectively connected with the power supply control signal end and the power supply voltage signal end and is used for generating a power supply voltage signal of the power supply voltage signal end according to a power supply control signal of the power supply control signal end;
the boosting module is respectively connected with the power supply voltage signal end and the analog voltage signal end and is used for generating an analog voltage signal of the analog voltage signal end according to the power supply voltage signal of the power supply voltage signal end.
In a possible implementation manner, in the power-on timing sequence control circuit provided in the embodiment of the present invention, the second control module is further connected to the first control signal terminal, and is configured to control the power supply voltage signal terminal to output no signal through the first control signal of the first control signal terminal.
In a possible implementation manner, in the power-on timing control circuit provided in an embodiment of the present invention, the first control module includes: the circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first triode, a first field effect transistor, a first capacitor and a second capacitor;
one end of the first resistor is connected with the first control signal end, and the other end of the first resistor is grounded;
one end of the second resistor is connected with the first control signal end, the other end of the second resistor is connected with the base electrode of the first triode, the collector electrode of the first triode is connected with the first node, and the emitter electrode of the first triode is grounded;
one end of the third resistor is connected with the first node, and the other end of the third resistor is connected with the second node;
one end of the fourth resistor is connected with the first starting voltage end, and the other end of the fourth resistor is connected with the first node;
one end of the fifth resistor is connected with the first starting voltage end, and the other end of the fifth resistor is connected with the second node;
one end of the first capacitor is connected with the first starting voltage end, and the other end of the first capacitor is connected with the second node;
the grid electrode of the first field effect transistor is connected with the second node, the first pole of the first field effect transistor is connected with the first starting voltage end, and the second pole of the first field effect transistor is respectively connected with the power supply control signal end, the digital voltage signal end and the second starting voltage end;
one end of the second capacitor is connected with the power supply control signal end, the digital voltage signal end and the second starting voltage end respectively, and the other end of the second capacitor is connected with the second node.
In a possible implementation manner, in the power-on timing control circuit provided in an embodiment of the present invention, the second control module includes: the circuit comprises a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a third capacitor, a fourth capacitor, a fifth capacitor, a second triode, a second field effect transistor and a first diode;
one end of the sixth resistor is connected with the power supply control signal end, and the other end of the sixth resistor is connected with the third node;
one end of the seventh resistor is connected with the third starting voltage end, and the other end of the seventh resistor is connected with the fourth node;
one end of the eighth resistor is connected with a fourth starting voltage end, and the other end of the eighth resistor is connected with the fourth node;
one end of the ninth resistor is connected with the fourth node, and the other end of the ninth resistor is connected with the fifth node;
one end of the tenth resistor is connected with the fourth node, and the other end of the tenth resistor is connected with the sixth node;
one end of the eleventh resistor is connected with the fifth node, and the other end of the eleventh resistor is connected with the sixth node;
the base electrode of the second triode is connected with the third node, the collector electrode of the second triode is connected with the fifth node, and the emitter electrode of the second triode is grounded;
the anode of the first diode is connected with the fifth node, and the cathode of the first diode is connected with the sixth node;
the grid electrode of the second field effect transistor is connected with the sixth node, the first pole of the second field effect transistor is connected with the fourth node, and the second pole of the second field effect transistor is connected with the power supply voltage signal end;
one end of the third capacitor is connected with the third node, and the other end of the third capacitor is grounded;
one end of the fourth capacitor is connected with the fourth node, and the other end of the fourth capacitor is connected with the sixth node;
and one end of the fifth capacitor is connected with the sixth node, and the other end of the fifth capacitor is connected with the power supply voltage signal end.
In a possible implementation manner, in the power-on timing control circuit provided in an embodiment of the present invention, the second control module includes: the circuit comprises a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a third capacitor, a fourth capacitor, a fifth capacitor, a second triode, a second field effect transistor and a first diode;
one end of the sixth resistor is connected with the power supply control signal end, and the other end of the sixth resistor is connected with the third node;
one end of the seventh resistor is connected with the third starting voltage end, and the other end of the seventh resistor is connected with the fourth node;
one end of the eighth resistor is connected with a fourth starting voltage end, and the other end of the eighth resistor is connected with the fourth node;
one end of the ninth resistor is connected with the fourth node, and the other end of the ninth resistor is connected with the fifth node;
one end of the tenth resistor is connected with the fourth node, and the other end of the tenth resistor is connected with the sixth node;
one end of the eleventh resistor is connected with the fifth node, and the other end of the eleventh resistor is connected with the sixth node;
one end of the twelfth resistor is connected with the first control signal end, and the other end of the twelfth resistor is grounded;
one end of the thirteenth resistor is connected with the first control signal end, and the other end of the thirteenth resistor is connected with the third node;
the base electrode of the second triode is connected with the third node, the collector electrode of the second triode is connected with the fifth node, and the emitter electrode of the second triode is grounded;
the anode of the first diode is connected with the fifth node, and the cathode of the first diode is connected with the sixth node;
the grid electrode of the second field effect transistor is connected with the sixth node, the first pole of the second field effect transistor is connected with the fourth node, and the second pole of the second field effect transistor is connected with the power supply voltage signal end;
one end of the third capacitor is connected with the third node, and the other end of the third capacitor is grounded;
one end of the fourth capacitor is connected with the fourth node, and the other end of the fourth capacitor is connected with the sixth node;
and one end of the fifth capacitor is connected with the sixth node, and the other end of the fifth capacitor is connected with the power supply voltage signal end.
In a possible implementation manner, in the power-on timing control circuit provided in an embodiment of the present invention, the boost module includes: a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a fourteenth capacitor, a fifteenth capacitor, a second diode, an inductance coil and a panel signal control chip;
one end of the inductance coil is connected with the power supply voltage signal end, and the other end of the inductance coil is connected with a seventh node;
the anode of the second diode is connected with the seventh node, and the cathode of the second diode is respectively connected with the analog voltage signal end and the tone modulation signal end;
one end of the sixth capacitor is connected with the power supply voltage signal end, and the other end of the sixth capacitor is grounded;
one end of the seventh capacitor is connected with the seventh node through the fourteenth resistor, and the other end of the seventh capacitor is grounded;
one end of the eighth capacitor is connected with the analog voltage signal end and the tone modulation signal end respectively, and the other end of the eighth capacitor is grounded;
one end of the ninth capacitor is connected with the analog voltage signal end and the tone modulation signal end respectively, and the other end of the ninth capacitor is grounded;
one end of the tenth capacitor is connected with the analog voltage signal end and the tone modulation signal end respectively, and the other end of the tenth capacitor is grounded;
one end of the eleventh capacitor is connected with the eighth node, and the other end of the eleventh capacitor is grounded;
one end of the fifteenth resistor is connected with the analog voltage signal end and the tone modulation signal end respectively, and the other end of the fifteenth resistor is connected with the eighth node;
one end of the sixteenth resistor is connected with the eighth node, and the other end of the sixteenth resistor is grounded;
the first pin of the panel signal control chip is grounded through the twelfth capacitor, the second pin is grounded, the third pin is grounded through the thirteenth capacitor, the fourth pin is connected with the ninth node, the fifth pin is connected with the tenth node, the sixth pin is grounded through the eighteenth resistor, the nineteenth resistor and the twentieth resistor which are connected in parallel, the seventh pin is connected with the seventh node, the eighth pin is grounded, and the ninth pin is grounded;
one end of the fourteenth capacitor is connected with the ninth node, the other end of the fourteenth capacitor is grounded, and the ninth node is connected with the first signal end;
one end of the fifteenth capacitor is connected with the tenth node, and the other end of the fifteenth capacitor is grounded;
one end of the seventeenth resistor is connected with the tenth node, and the other end of the seventeenth resistor is connected with the second signal end.
Based on the same inventive concept, the embodiment of the invention also provides a printed circuit board, which comprises the power-on sequence control circuit.
In a possible implementation manner, in the printed circuit board provided in the embodiment of the present invention, the printed circuit board further includes a main chip, where the main chip is connected to the first control signal terminal of the power-on timing control circuit, and is configured to provide the first control signal to the first control signal terminal.
Based on the same inventive concept, the embodiment of the invention also provides a display panel, which comprises the printed circuit board.
Correspondingly, an embodiment of the present invention further provides a method for driving the power-on timing control circuit, including:
the first control module generates a power supply control signal of a power supply control signal end according to a first control signal of a first control signal end, and simultaneously generates a digital voltage signal of a digital voltage signal end;
the second control module generates a power supply voltage signal of a power supply voltage signal end according to the power supply control signal of the power supply control signal end;
and the boosting module generates an analog voltage signal of an analog voltage signal end according to the power supply voltage signal of the power supply voltage signal end.
The embodiment of the invention has the beneficial effects that:
the embodiment of the invention provides a power-on time sequence control circuit, a driving method thereof, a printed circuit board and a display panel, wherein the power-on time sequence control circuit comprises the following components: the device comprises a first control module, a second control module and a boosting module; the first control module is respectively connected with the first control signal end, the power supply control signal end and the digital voltage signal end and is used for generating a power supply control signal of the power supply control signal end according to a first control signal of the first control signal end and simultaneously generating a digital voltage signal of the digital voltage signal end; the second control module is respectively connected with the power supply control signal end and the power supply voltage signal end and is used for generating a power supply voltage signal of the power supply voltage signal end according to the power supply control signal of the power supply control signal end; the boosting module is respectively connected with the power supply voltage signal end and the analog voltage signal end and is used for generating an analog voltage signal of the analog voltage signal end according to the power supply voltage signal of the power supply voltage signal end. The first control module can simultaneously generate a power supply control signal and a digital voltage signal according to the first control signal, then the second control module generates a power supply voltage signal according to the power supply control signal, and finally the boosting module generates an analog voltage signal according to the power supply voltage signal.
Drawings
Fig. 1 is a schematic structural diagram of a power-on timing control circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a first control module in a power-on timing control circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a second control module in the power-on timing control circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a boost module in a power-on timing control circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a working process of a power-on timing control circuit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a power-on timing control circuit according to a second embodiment of the present invention;
fig. 7 is a schematic structural diagram of a second control module in the power-on timing control circuit according to the second embodiment of the present invention;
fig. 8 is a flowchart of a driving method of a power-on timing control circuit according to an embodiment of the present invention.
Detailed Description
The following describes in detail specific embodiments of a power-on timing control circuit, a driving method thereof, a printed circuit board, and a display panel according to an embodiment of the present invention with reference to the accompanying drawings. It should be noted that the embodiments described in this specification are only a part of the embodiments of the present invention, and not all embodiments; and in case of conflict, the embodiments and features of the embodiments in the present application may be combined with each other; moreover, all other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative effort belong to the protection scope of the present invention.
Example one
A power-on sequence control circuit provided in an embodiment of the present invention, as shown in fig. 1, includes: a first control module 101, a second control module 102 and a boost module 103;
the first control module 101 is connected to the first control signal terminal, the power supply control signal terminal, and the digital voltage signal terminal, and configured to generate a power supply control signal Panel _ VCC _ DVDD at the power supply control signal terminal according to a first control signal Panel _ EN at the first control signal terminal, and generate a digital voltage signal DVDD at the digital voltage signal terminal at the same time;
the second control module 102 is connected to the power control signal terminal and the power voltage signal terminal, respectively, and configured to generate a power voltage signal Panel _ VCC of the power voltage signal terminal according to a power control signal Panel _ VCC _ DVDD of the power control signal terminal;
the boosting module 103 is connected to the power supply voltage signal terminal and the analog voltage signal terminal, respectively, and is configured to generate an analog voltage signal AVDD of the analog voltage signal terminal according to a power supply voltage signal Panel _ VCC of the power supply voltage signal terminal.
In the power-on timing control circuit provided in the first embodiment of the present invention, the first control module 101 may generate the power control signal Panel _ VCC _ DVDD and the digital voltage signal DVDD simultaneously according to the first control signal Panel _ EN; the second control module 102 may generate a power supply voltage signal Panel _ VCC according to the power supply control signal Panel _ VCC _ DVDD; the boost module 103 can generate the analog voltage signal AVDD according to the power supply voltage signal Panel _ VCC, and therefore, in the present invention, the digital voltage signal DVDD is started before the analog voltage signal AVDD, so that a fault of image abnormality caused by the fact that the analog voltage signal AVDD is started before the digital voltage signal DVDD in the prior art is effectively avoided.
In order to better understand the structure and the operation principle of the power-on timing control circuit provided in the first embodiment of the present invention, the specific structure of each module in the first embodiment is described in detail below.
In the power-on timing control circuit provided in the first embodiment of the present invention, as shown in fig. 2, the first control module 101 includes: the circuit comprises a first resistor RL1, a second resistor RL2, a third resistor RL3, a fourth resistor RL4, a fifth resistor RL5, a first triode QL1, a first field-effect transistor MOS1, a first capacitor CL1 and a second capacitor CL 2;
one end of the first resistor RL1 is connected with the first control signal end, and the other end is grounded;
one end of the second resistor RL2 is connected with the first control signal end, the other end of the second resistor RL2 is connected with the base electrode of the first triode QL1, the collector electrode of the first triode QL1 is connected with the first node P1, and the emitter electrode of the first triode QL1 is grounded;
one end of the third resistor RL3 is connected to the first node P1, and the other end is connected to the second node P2;
one end of the fourth resistor RL4 is connected to the first start voltage terminal A3V3, and the other end is connected to the first node P1;
one end of the fifth resistor RL5 is connected to the first starting voltage end A3V3, and the other end is connected to the second node P2;
one end of the first capacitor CL1 is connected to the first starting voltage terminal A3V3, and the other end is connected to the second node P2;
the grid of the first field effect transistor MOS1 is connected with a second node P2, the first pole is connected with a first starting voltage end A3V3, and the second pole is respectively connected with a power supply control signal end, a digital voltage signal end and a second starting voltage end VDD 33;
one end of the second capacitor CL2 is connected to the power control signal terminal, the digital voltage signal terminal, and the second start voltage terminal VDD33, respectively, and the other end is connected to the second node P2.
As shown in fig. 3, in the power-on timing control circuit according to the first embodiment of the present invention, the second control module 102 includes: a sixth resistor RL6, a seventh resistor RL7, an eighth resistor RL8, a ninth resistor RL9, a tenth resistor RL10, an eleventh resistor RL11, a third capacitor CL3, a fourth capacitor CL4, a fifth capacitor CL5, a second triode QL2, a second field effect transistor MOS2 and a first diode D1;
one end of the sixth resistor RL6 is connected with the power supply control signal end, and the other end is connected with the third node P3;
one end of the seventh resistor RL7 is connected to the +12V end of the third start voltage, and the other end is connected to the fourth node P4;
one end of the eighth resistor RL8 is connected to the +5V of the fourth starting voltage end, and the other end is connected to the fourth node P4;
one end of the ninth resistor RL9 is connected to the fourth node P4, and the other end is connected to the fifth node P5;
one end of the tenth resistor RL10 is connected to the fourth node P4, and the other end is connected to the sixth node P6;
one end of the eleventh resistor RL11 is connected to the fifth node P5, and the other end is connected to the sixth node P6;
the base electrode of the second triode QL2 is connected with the third node P3, the collector electrode is connected with the fifth node P5, and the emitter electrode is grounded;
the anode of the first diode D1 is connected to the fifth node P5, and the cathode is connected to the sixth node P6;
the grid electrode of the second field effect transistor MOS2 is connected with a sixth node P6, the first pole is connected with a fourth node P4, and the second pole is connected with a power supply voltage signal end;
one end of the third capacitor CL3 is connected to the third node P3, and the other end is grounded;
one end of the fourth capacitor CL4 is connected to the fourth node P4, and the other end is connected to the sixth node P6;
one end of the fifth capacitor CL5 is connected to the sixth node P6, and the other end is connected to the power supply voltage signal terminal.
As shown in fig. 4, in the power-on timing control circuit according to the first embodiment of the present invention, the boosting module 103 includes: a fourteenth resistor RL14, a fifteenth resistor RL15, a sixteenth resistor RL16, a seventeenth resistor RL17, an eighteenth resistor RL18, a nineteenth resistor RL19, a twentieth resistor RL20, a sixth capacitor CL6, a seventh capacitor CL7, an eighth capacitor CL8, a ninth capacitor CL9, a tenth capacitor CL10, an eleventh capacitor CL11, a twelfth capacitor CL12, a thirteenth capacitor CL13, a fourteenth capacitor CL14, a fifteenth capacitor CL15, a second diode D2, an inductance coil L and a panel signal control chip;
one end of the inductance coil L is connected with a power supply voltage signal end, and the other end of the inductance coil L is connected with a seventh node P7;
the anode of the second diode D2 is connected with the seventh node P7, and the cathode is connected with the analog voltage signal end and the tone modulation signal end respectively;
one end of the sixth capacitor CL6 is connected with the power supply voltage signal end, and the other end is grounded;
one end of the seventh capacitor CL7 is connected to the seventh node P7 through the fourteenth resistor RL14, and the other end is grounded;
one end of the eighth capacitor CL8 is connected to the analog voltage signal end and the tone modulation signal end, respectively, and the other end is grounded;
one end of the ninth capacitor CL9 is connected to the analog voltage signal end and the tone modulation signal end, respectively, and the other end is grounded;
one end of the tenth capacitor CL10 is connected to the analog voltage signal end and the tone modulation signal end, respectively, and the other end is grounded;
one end of the eleventh capacitor CL11 is connected to the eighth node P8, and the other end is grounded;
one end of the fifteenth resistor RL15 is connected to the analog voltage signal end and the tone modulation signal end, respectively, and the other end is connected to the eighth node P8;
one end of a sixteenth resistor RL16 is connected with the eighth node P8, and the other end is grounded;
the first pin POS of the panel signal control chip is grounded through a twelfth capacitor CL12, the second pin PAD is grounded, the third pin DEL is grounded through a thirteenth capacitor CL13, the fourth pin VGH is connected with a ninth node P9, the fifth pin VGHM is connected with a tenth node P10, the sixth pin PE is grounded through an eighteenth resistor RL18, a nineteenth resistor RL19 and a twentieth resistor RL20 which are connected in parallel, the seventh pin LX is connected with a seventh node P7, the eighth pin PGND _2 is grounded, and the ninth pin PGND _1 is grounded;
one end of the fourteenth capacitor CL14 is connected to the ninth node P9, the other end is grounded, and the ninth node P9 is connected to the first signal terminal VGHF;
one end of a fifteenth capacitor CL15 is connected with the tenth node P10, and the other end is grounded;
the seventeenth resistor RL17 has one end connected to the tenth node P10 and the other end connected to the second signal terminal VGHm.
The following is a detailed description of an operation procedure of a power-on timing control circuit according to an embodiment of the present invention, which is composed of the first control module 101 having the structure shown in fig. 2, the second control module 102 having the structure shown in fig. 3, and the voltage boost circuit 103 having the structure shown in fig. 4.
In the first control module 101 shown in fig. 2, the second control module 102 shown in fig. 3, and the boost module 103 shown in fig. 4, each transistor and MOS transistor functions as a switch, a diode functions as a rectifier, and a resistor and a capacitor together function as a filter. The specific working processes of the first control module 101 shown in fig. 2, the second control module 102 shown in fig. 3, and the boost module 103 shown in fig. 4 are shown in fig. 5, where 3.3V and 12V in fig. 5 are both system self-supply voltages for starting the power-on sequence control circuit. Specifically, first, in fig. 2, after the first control signal Panel _ EN controls the first transistor QL1 and the first fet MOS1 to be in an on state in sequence, the power control signal terminal outputs the power control signal Panel _ VDD _ DVDD, and the digital voltage signal terminal outputs the digital voltage signal DVDD. Then, in fig. 3, after the power control signal Panel _ VDD _ DVDD controls the second transistor QL2 and the second fet MOS2 to be in an on state in sequence, the power voltage signal terminal outputs the power voltage signal Panel _ VCC. Finally, in fig. 4, the power supply voltage signal Panel _ VCC at the power supply voltage signal end is boosted by the inductor L and the second diode D2 in sequence to obtain the analog voltage signal AVDD at the analog voltage signal end.
As can be seen from the above description, in the power-on timing control circuit provided in the first embodiment of the present invention, the digital voltage signal DVDD is started before the analog voltage signal AVDD, so that the image abnormality fault caused by the fact that the analog voltage signal AVDD is started before the digital voltage signal DVDD in the prior art is effectively avoided.
Example two
As shown in fig. 6, the power-on timing control circuit provided in the second embodiment of the present invention has a similar structure to the power-on timing control circuit provided in the first embodiment, and the power-on timing control circuit provided in the first embodiment are different only in the specific structure of the second control module 102, so only the differences will be described below, and the repeated points may refer to the first embodiment, and are not described herein again.
As shown in fig. 6, in the power-on timing control circuit according to the second embodiment of the present invention, the second control module 102 is further connected to the first control signal terminal, and is configured to control no signal output at the power voltage signal terminal according to the first control signal Panel _ EN of the first control signal terminal.
Specifically, in the power-on timing control circuit provided in the second embodiment of the present invention, as shown in fig. 7, the second control module 102 includes: a sixth resistor RL6, a seventh resistor RL7, an eighth resistor RL8, a ninth resistor RL9, a tenth resistor RL10, an eleventh resistor RL11, a twelfth resistor RL12, a thirteenth resistor RL13, a third capacitor CL3, a fourth capacitor CL4, a fifth capacitor CL5, a second triode QL2, a second field effect transistor MOS2 and a first diode D1;
one end of the sixth resistor RL6 is connected with the power supply control signal end, and the other end is connected with the third node P3;
one end of the seventh resistor RL7 is connected to the +12V end of the third start voltage, and the other end is connected to the fourth node P4;
one end of the eighth resistor RL8 is connected to the +5V of the fourth starting voltage end, and the other end is connected to the fourth node P4;
one end of the ninth resistor RL9 is connected to the fourth node P4, and the other end is connected to the fifth node P5;
one end of the tenth resistor RL10 is connected to the fourth node P4, and the other end is connected to the sixth node P6;
one end of the eleventh resistor RL11 is connected to the fifth node P5, and the other end is connected to the sixth node P6;
one end of the twelfth resistor RL12 is connected with the first control signal end, and the other end is grounded;
one end of the thirteenth resistor RL13 is connected to the first control signal end, and the other end is connected to the third node P3;
the base electrode of the second triode QL2 is connected with the third node P3, the collector electrode is connected with the fifth node P5, and the emitter electrode is grounded;
the anode of the first diode D1 is connected to the fifth node P5, and the cathode is connected to the sixth node P6;
the grid electrode of the second field effect transistor MOS2 is connected with a sixth node P6, the first pole is connected with a fourth node P4, and the second pole is connected with a power supply voltage signal end;
one end of the third capacitor CL3 is connected to the third node P3, and the other end is grounded;
one end of the fourth capacitor CL4 is connected to the fourth node P4, and the other end is connected to the sixth node P6;
one end of the fifth capacitor CL5 is connected to the sixth node P6, and the other end is connected to the power supply voltage signal terminal.
In an actual application process, compared to the first embodiment of the present invention, the working process of the power-on timing control circuit provided in the second embodiment of the present invention is only different in the specific working manner of the first control signal Panel _ EN, so that only the working condition of the first control signal Panel _ EN in the second embodiment of the present invention is described in detail below, and repeated points can be referred to in the first embodiment, and are not described herein again.
In the power-on timing control circuit including the second control module 102 shown in fig. 7 according to the second embodiment of the present invention, the first control signal Panel _ EN controls the first transistor QL1 and the first fet MOS1 to be sequentially turned on in the first control module 101 shown in fig. 2, so that the power control signal terminal outputs the power control signal Panel _ VDD _ DVDD, and the second transistor QL2 shown in fig. 7 is controlled to be turned off during the process of outputting the digital voltage signal DVDD from the digital voltage signal terminal, so that no signal is output from the power voltage signal terminal. Therefore, the digital voltage signal DVDD can be further ensured to be started before the analog voltage signal AVDD, and the problem of image abnormity caused by the fact that the analog voltage signal AVDD is started before the digital voltage signal DVDD is solved better.
EXAMPLE III
Based on the same inventive concept, a third embodiment of the present invention provides a method for driving a power-on timing control circuit, and because a problem solving principle of the driving method is similar to a problem solving principle of the power-on timing control circuit, implementation of the driving method provided by the third embodiment of the present invention may refer to implementation of the power-on timing control circuit provided by the first embodiment of the present invention and the second embodiment of the present invention, and repeated details are not repeated.
Specifically, as shown in fig. 8, the driving method of the power-on timing control circuit according to the third embodiment of the present invention may specifically include the following steps:
s801, generating a power supply control signal of a power supply control signal end by a first control module according to a first control signal of a first control signal end, and simultaneously generating a digital voltage signal of a digital voltage signal end;
s802, the second control module generates a power supply voltage signal of a power supply voltage signal end according to a power supply control signal of the power supply control signal end;
and S803, the boosting module generates an analog voltage signal of an analog voltage signal end according to the power supply voltage signal of the power supply voltage signal end.
Example four
Based on the same inventive concept, a fourth embodiment of the present invention provides a printed circuit board, including the above power-on timing control circuit. The printed circuit board can be normally used after Surface Mount Technology (SMT). Moreover, because the principle of solving the problem of the printed circuit board is similar to that of solving the problem of the power-on timing control circuit, the implementation of the printed circuit board provided by the fourth embodiment of the present invention may refer to the implementation of the power-on timing control circuit provided by the first embodiment of the present invention and the second embodiment of the present invention, and repeated details are not described again.
Generally, the printed circuit board includes a main chip, and in order to save cost and facilitate driving the power-on timing control circuit, in the printed circuit board provided in the embodiment of the present invention, the main chip may be connected to a first control signal terminal of the power-on timing control circuit, and the first control signal terminal is preferentially provided with the first control signal. That is, after the main chip provides the first control signal to the first control signal terminal, other signals (for example, image signals) that the main chip can output are output, which is well known to those skilled in the art, so that the power-on timing control circuit can work in preference to other circuits. In addition, in the practical application process, the main chip can be supplied with power through the system with the voltage of 3.3V at the end of the main board, and the main chip always exists after the main chip works normally.
EXAMPLE five
Based on the same inventive concept, a fifth embodiment of the present invention further provides a display panel, including the printed circuit board provided in the fifth embodiment of the present invention, where the display panel is a liquid crystal display panel, and may be specifically applied to: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital camera, a navigator, an intelligent watch, a fitness wristband, a personal digital assistant, a self-service deposit/withdrawal machine, and the like. Other essential components of the liquid crystal display panel are understood by those skilled in the art, and are not described herein nor should they be construed as limiting the present invention. The implementation of the display panel can be referred to the embodiment of the printed circuit board, and repeated details are not repeated.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (9)
1. A power-on sequence control circuit, comprising: the device comprises a first control module, a second control module and a boosting module;
the first control module is respectively connected with a first control signal end, a power supply control signal end and a digital voltage signal end and is used for generating a power supply control signal of the power supply control signal end according to a first control signal of the first control signal end and generating a digital voltage signal of the digital voltage signal end at the same time;
the second control module is respectively connected with the power supply control signal end and the power supply voltage signal end and is used for generating a power supply voltage signal of the power supply voltage signal end according to a power supply control signal of the power supply control signal end;
the boosting module is respectively connected with the power supply voltage signal end and the analog voltage signal end and is used for generating an analog voltage signal of the analog voltage signal end according to the power supply voltage signal of the power supply voltage signal end;
the boost module includes: a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a fourteenth capacitor, a fifteenth capacitor, a second diode, an inductance coil and a panel signal control chip;
one end of the inductance coil is connected with the power supply voltage signal end, and the other end of the inductance coil is connected with a seventh node;
the anode of the second diode is connected with the seventh node, and the cathode of the second diode is respectively connected with the analog voltage signal end and the tone modulation signal end;
one end of the sixth capacitor is connected with the power supply voltage signal end, and the other end of the sixth capacitor is grounded;
one end of the seventh capacitor is connected with the seventh node through the fourteenth resistor, and the other end of the seventh capacitor is grounded;
one end of the eighth capacitor is connected with the analog voltage signal end and the tone modulation signal end respectively, and the other end of the eighth capacitor is grounded;
one end of the ninth capacitor is connected with the analog voltage signal end and the tone modulation signal end respectively, and the other end of the ninth capacitor is grounded;
one end of the tenth capacitor is connected with the analog voltage signal end and the tone modulation signal end respectively, and the other end of the tenth capacitor is grounded;
one end of the eleventh capacitor is connected with the eighth node, and the other end of the eleventh capacitor is grounded;
one end of the fifteenth resistor is connected with the analog voltage signal end and the tone modulation signal end respectively, and the other end of the fifteenth resistor is connected with the eighth node;
one end of the sixteenth resistor is connected with the eighth node, and the other end of the sixteenth resistor is grounded;
the first pin of the panel signal control chip is grounded through the twelfth capacitor, the second pin is grounded, the third pin is grounded through the thirteenth capacitor, the fourth pin is connected with the ninth node, the fifth pin is connected with the tenth node, the sixth pin is grounded through the eighteenth resistor, the nineteenth resistor and the twentieth resistor which are connected in parallel, the seventh pin is connected with the seventh node, the eighth pin is grounded, and the ninth pin is grounded;
one end of the fourteenth capacitor is connected with the ninth node, the other end of the fourteenth capacitor is grounded, and the ninth node is connected with the first signal end;
one end of the fifteenth capacitor is connected with the tenth node, and the other end of the fifteenth capacitor is grounded;
one end of the seventeenth resistor is connected with the tenth node, and the other end of the seventeenth resistor is connected with the second signal end.
2. The power-on timing control circuit according to claim 1, wherein the second control module is further connected to the first control signal terminal, and configured to control the power voltage signal terminal to output no signal according to the first control signal of the first control signal terminal.
3. The power-on timing control circuit of claim 1, wherein the first control module comprises: the circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first triode, a first field effect transistor, a first capacitor and a second capacitor;
one end of the first resistor is connected with the first control signal end, and the other end of the first resistor is grounded;
one end of the second resistor is connected with the first control signal end, the other end of the second resistor is connected with the base electrode of the first triode, the collector electrode of the first triode is connected with the first node, and the emitter electrode of the first triode is grounded;
one end of the third resistor is connected with the first node, and the other end of the third resistor is connected with the second node;
one end of the fourth resistor is connected with the first starting voltage end, and the other end of the fourth resistor is connected with the first node;
one end of the fifth resistor is connected with the first starting voltage end, and the other end of the fifth resistor is connected with the second node;
one end of the first capacitor is connected with the first starting voltage end, and the other end of the first capacitor is connected with the second node;
the grid electrode of the first field effect transistor is connected with the second node, the first pole of the first field effect transistor is connected with the first starting voltage end, and the second pole of the first field effect transistor is respectively connected with the power supply control signal end, the digital voltage signal end and the second starting voltage end;
one end of the second capacitor is connected with the power supply control signal end, the digital voltage signal end and the second starting voltage end respectively, and the other end of the second capacitor is connected with the second node.
4. The power-on timing control circuit of claim 1, wherein the second control module comprises: the circuit comprises a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a third capacitor, a fourth capacitor, a fifth capacitor, a second triode, a second field effect transistor and a first diode;
one end of the sixth resistor is connected with the power supply control signal end, and the other end of the sixth resistor is connected with the third node;
one end of the seventh resistor is connected with the third starting voltage end, and the other end of the seventh resistor is connected with the fourth node;
one end of the eighth resistor is connected with a fourth starting voltage end, and the other end of the eighth resistor is connected with the fourth node;
one end of the ninth resistor is connected with the fourth node, and the other end of the ninth resistor is connected with the fifth node;
one end of the tenth resistor is connected with the fourth node, and the other end of the tenth resistor is connected with the sixth node;
one end of the eleventh resistor is connected with the fifth node, and the other end of the eleventh resistor is connected with the sixth node;
the base electrode of the second triode is connected with the third node, the collector electrode of the second triode is connected with the fifth node, and the emitter electrode of the second triode is grounded;
the anode of the first diode is connected with the fifth node, and the cathode of the first diode is connected with the sixth node;
the grid electrode of the second field effect transistor is connected with the sixth node, the first pole of the second field effect transistor is connected with the fourth node, and the second pole of the second field effect transistor is connected with the power supply voltage signal end;
one end of the third capacitor is connected with the third node, and the other end of the third capacitor is grounded;
one end of the fourth capacitor is connected with the fourth node, and the other end of the fourth capacitor is connected with the sixth node;
and one end of the fifth capacitor is connected with the sixth node, and the other end of the fifth capacitor is connected with the power supply voltage signal end.
5. The power-on timing control circuit of claim 2, wherein the second control module comprises: the circuit comprises a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a third capacitor, a fourth capacitor, a fifth capacitor, a second triode, a second field effect transistor and a first diode;
one end of the sixth resistor is connected with the power supply control signal end, and the other end of the sixth resistor is connected with the third node;
one end of the seventh resistor is connected with the third starting voltage end, and the other end of the seventh resistor is connected with the fourth node;
one end of the eighth resistor is connected with a fourth starting voltage end, and the other end of the eighth resistor is connected with the fourth node;
one end of the ninth resistor is connected with the fourth node, and the other end of the ninth resistor is connected with the fifth node;
one end of the tenth resistor is connected with the fourth node, and the other end of the tenth resistor is connected with the sixth node;
one end of the eleventh resistor is connected with the fifth node, and the other end of the eleventh resistor is connected with the sixth node;
one end of the twelfth resistor is connected with the first control signal end, and the other end of the twelfth resistor is grounded;
one end of the thirteenth resistor is connected with the first control signal end, and the other end of the thirteenth resistor is connected with the third node;
the base electrode of the second triode is connected with the third node, the collector electrode of the second triode is connected with the fifth node, and the emitter electrode of the second triode is grounded;
the anode of the first diode is connected with the fifth node, and the cathode of the first diode is connected with the sixth node;
the grid electrode of the second field effect transistor is connected with the sixth node, the first pole of the second field effect transistor is connected with the fourth node, and the second pole of the second field effect transistor is connected with the power supply voltage signal end;
one end of the third capacitor is connected with the third node, and the other end of the third capacitor is grounded;
one end of the fourth capacitor is connected with the fourth node, and the other end of the fourth capacitor is connected with the sixth node;
and one end of the fifth capacitor is connected with the sixth node, and the other end of the fifth capacitor is connected with the power supply voltage signal end.
6. A printed circuit board comprising the power-on timing control circuit according to any one of claims 1 to 5.
7. The printed circuit board of claim 6, further comprising a main chip, wherein the main chip is connected to the first control signal terminal of the power-on timing control circuit for providing a first control signal to the first control signal terminal.
8. A display panel comprising the printed circuit board according to claim 6 or 7.
9. A driving method of a power-on timing control circuit according to any one of claims 1 to 5, comprising:
the first control module generates a power supply control signal of a power supply control signal end according to a first control signal of a first control signal end, and simultaneously generates a digital voltage signal of a digital voltage signal end;
the second control module generates a power supply voltage signal of a power supply voltage signal end according to the power supply control signal of the power supply control signal end;
and the boosting module generates an analog voltage signal of an analog voltage signal end according to the power supply voltage signal of the power supply voltage signal end.
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| CN201810810868.6A CN108986758B (en) | 2018-07-23 | 2018-07-23 | Power-on time sequence control circuit, driving method thereof, printed circuit board and display panel |
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| CN201810810868.6A CN108986758B (en) | 2018-07-23 | 2018-07-23 | Power-on time sequence control circuit, driving method thereof, printed circuit board and display panel |
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| CN109509454B (en) * | 2018-12-24 | 2021-10-01 | 惠科股份有限公司 | Driving device, circuit driving method and display panel |
| CN109782663A (en) * | 2019-01-11 | 2019-05-21 | 合肥惠科金扬科技有限公司 | The electrostatic protection control circuit and master & slave control system of master & slave control system |
| CN110048595B (en) * | 2019-04-25 | 2020-01-17 | 东莞铭普光磁股份有限公司 | Power supply circuit of PAM4 optical module and power supply control method of PAM4 optical module |
| CN114420035A (en) * | 2022-03-30 | 2022-04-29 | 惠科股份有限公司 | Panel driving circuit and display panel |
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| CN2655309Y (en) * | 2003-07-16 | 2004-11-10 | 华为技术有限公司 | Power supply time sequence controlling circuit |
| KR20080019386A (en) * | 2006-08-28 | 2008-03-04 | 삼성전자주식회사 | Power sequence circuit for liquid crystal display and liquid crystal display having this |
| CN101963792B (en) * | 2010-10-29 | 2012-08-22 | 珠海市鑫和电器有限公司 | Time sequence control circuit and control method thereof |
| CN102749856B (en) * | 2012-05-30 | 2016-04-20 | 曙光信息产业(北京)有限公司 | A kind of power-on time sequence control circuit and method |
| TWI464717B (en) * | 2012-09-03 | 2014-12-11 | Hon Hai Prec Ind Co Ltd | Time control circuit and electronic device using the same |
| CN205847412U (en) * | 2016-05-11 | 2016-12-28 | 深圳创维－Rgb电子有限公司 | A kind of liquid crystal display screen power control switch circuit and display device |
| CN206932170U (en) * | 2017-04-12 | 2018-01-26 | 深圳市峰泳科技有限公司 | Power circuit and its liquid crystal display device |
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