CN108984453B - PCIE bus speed measuring system and method based on Shenwei platform - Google Patents
PCIE bus speed measuring system and method based on Shenwei platform Download PDFInfo
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- CN108984453B CN108984453B CN201810764136.8A CN201810764136A CN108984453B CN 108984453 B CN108984453 B CN 108984453B CN 201810764136 A CN201810764136 A CN 201810764136A CN 108984453 B CN108984453 B CN 108984453B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
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- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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Abstract
The invention provides a PCIE bus speed measuring system and method based on a Shenwei platform, which comprises a PCIE bus to be measured, the Shenwei platform, an FPGA speed measuring board card for receiving test data sent by the Shenwei platform and for recording and feeding back the time length t used for transmitting the current test data; a PCIE bus of the Shenwei platform processor is connected with a PCIE expansion module, and the PCIE expansion module is connected with the FPGA speed measurement board card through the PCIE bus to be measured; and a speed measurement software unit which is used for being matched with the FPGA speed measurement board card to be used for detecting the transmission rate of the PCIE bus to be detected is arranged in the Shenwei platform. The PCIE bus speed measurement method and the PCIE bus speed measurement device are used for detecting the transmission speed of the PCIE bus, realize the speed measurement of the PCIE bus based on the Shenwei platform, and make up the blank of realizing the speed measurement of the PCIE bus in the autonomous field of a domestic computer and the like, particularly on the Shenwei platform.
Description
Technical Field
The invention relates to the field of PCIE bus transmission rate test, in particular to a PCIE bus speed measuring system and method based on an Shenwei platform.
Background
The PCIE bus is a general bus specification, and is an indispensable bus transmission interface in the current computer system. The serial interconnection mode is adopted, and data transmission is carried out in a point-to-point mode, so that each device can share an independent bandwidth, and the method is widely applied to the fields of industrial equipment, automation, vehicle-mounted devices, airborne devices and the like.
The Shenwei processor is a processor series with completely independent intellectual property rights developed by the calculation in the south of the Yangtze river, adopts an Alpha architecture and is based on an independent instruction set.
At present, no relevant PCIE bus speed measuring method exists in the autonomous field of a domestic computer and the like, especially on a Shenwei platform.
Disclosure of Invention
The invention aims to solve the technical problem that in order to overcome the defects of the prior art, the PCIE bus speed measurement system and the method based on the Shenwei platform are provided, and are used for realizing the PCIE bus speed measurement based on the Shenwei platform.
In order to solve the technical problem, the invention provides a PCIE bus speed measuring system based on a Shenwei platform, which comprises a PCIE bus to be measured, the Shenwei platform, an FPGA speed measuring board card used for receiving test data sent by the Shenwei platform and recording and feeding back the time length t used for transmitting the current test data; the test data has a specific size;
a PCIE bus of the Shenwei platform processor is connected with a PCIE expansion module, and the PCIE expansion module is connected with the FPGA speed measurement board card through the PCIE bus to be measured;
and a speed measurement software unit which is used for being matched with the FPGA speed measurement board card to be used for detecting the transmission rate of the PCIE bus to be detected is arranged in the Shenwei platform.
The speed measurement software unit comprises a test data generation module, a test data sending module and a test result analysis processing module, wherein:
the test data generation module is used for generating test data;
the test data sending module is used for sending the test data generated by the test data generating module to the FPGA speed measuring board card through the PCIE bus to be tested;
and the test result analysis processing module is respectively connected with the test data generation module and the test data sending module, is used for receiving the time length t used by the current test data transmission fed back by the FPGA speed measurement board card, and is used for calculating and controlling the Shenwei platform to display the transmission rate v of the PCIE bus to be tested based on the currently received time length t and the size of the current transmitted data.
The speed measurement software unit also comprises a test frequency setting module, wherein the test frequency setting module is connected with the test result analysis processing module and is used for setting the detection frequency of the PCIE bus transmission rate test to be tested;
the test result analysis processing module is further configured to, when the number of detection times input by the test time setting module is greater than 1, invoke the test data sending module to execute the test data cycle sending operation of the number of detection times, and is further configured to correspondingly calculate and display, through the shenwei platform, a transmission rate v corresponding to the test data sent each time, and is further configured to calculate and display, through the shenwei platform, an arithmetic average value of all the transmission rates v obtained through the calculation, where the average value is the transmission rate of the PCIE bus to be detected finally.
The FPGA speed measurement board card is integrated with a PCIE bus and supports speed measurement of the PCIE X4, the PCIE X8 and the PCIE X16 bus.
Corresponding to the PCIE bus speed measurement system based on the Shenwei platform, the present invention also provides a PCIE bus speed measurement method based on the Shenwei platform, which includes the steps of:
s1, a PCIE bus of the Shenwei platform processor is connected with a PCIE expansion module, and the PCIE expansion module is connected with the FPGA speed measurement board card through the PCIE bus to be measured; the FPGA speed measurement board card is used for receiving test data sent by the Shenwei platform based on the PCIE expansion module and recording and feeding back the time length t used by the current test data transmission;
s2, a speed measurement software unit used for being matched with the FPGA speed measurement board card for use and used for detecting the transmission rate of the PCIE bus to be detected is arranged in the Shenwei platform;
s3, starting the Shenwei platform system;
and s4, starting the speed measurement software unit, and sending the test data to the FPGA speed measurement board card based on the PCIE expansion module to test the transmission rate of the PCIE bus to be tested.
Wherein, the software starting of the shenwei platform system in the step s3 includes the steps of:
the Shenwei platform is powered on and started, and the BIOS identifies and initializes the FPGA speed measurement board card;
in the process of kernel starting, FIXUP configuration is carried out on a bus of the FPGA speed measurement board card and equipment thereof, and an interrupt number is distributed;
and in the starting process of the operating system, loading the drive of the FPGA speed measurement board card, and realizing the initialization of the FPGA speed measurement board card.
The speed measurement software unit comprises a test data generation module, a test data sending module and a test result analysis processing module, wherein:
the test data generation module is used for generating test data;
the test data sending module is used for sending the test data generated by the test data generating module to the FPGA speed measuring board card through the PCIE bus to be tested;
and the test result analysis processing module is respectively connected with the test data generation module and the test data sending module, is used for receiving the time length t used by the current test data transmission fed back by the FPGA speed measurement board card, and is used for calculating and controlling the Shenwei platform to display the transmission rate v of the PCIE bus to be tested based on the currently received time length t and the size of the current transmitted data.
The speed measurement software unit also comprises a test frequency setting module, wherein the test frequency setting module is connected with the test result analysis processing module and is used for setting the detection frequency of the PCIE bus transmission rate test to be tested;
the test result analysis processing module is further configured to, when the number of detection times input by the test time setting module is greater than 1, invoke the test data sending module to execute the test data cycle sending operation of the number of detection times, and is further configured to correspondingly calculate and display, through the shenwei platform, a transmission rate v corresponding to the test data sent each time, and is further configured to calculate and display, through the shenwei platform, an arithmetic average value of all the transmission rates v obtained through the calculation, where the average value is the transmission rate of the PCIE bus to be detected finally.
The FPGA speed measurement board card is integrated with a PCIE bus and supports speed measurement of the PCIE X4, the PCIE X8 and the PCIE X16 bus.
The method for recording and feeding back the time length t used by the current test data transmission by the FPGA speed measurement board card comprises the following steps:
after the FPGA speed measuring board card receives the data sending notification of the speed measuring software unit in the Shenwei platform, the receiving flag of the board card firmware is set as begin receiving begin, and the time t1 is recorded;
after the data to be tested is received, the receiving flag bit is set as end, and the time t2 is recorded;
then, the time length t = t2-t1 used for transmitting the current test data is internally calculated by the FPGA speed measurement board card;
and finally, the FPGA speed measurement board card is communicated with a driving interface of the FPGA speed measurement board card in the Shenwei platform through internal firmware of the FPGA speed measurement board card, and the calculated time length t = t2-t1 used for transmitting the current test data is fed back to the speed measurement software unit.
Compared with the prior art, the invention has the advantages that:
the PCIE bus speed measuring system and the method based on the Shenwei platform expand the PCIE bus of the Shenwei platform processor through the PCIE expansion module, connect the PCIE expansion module with the FPGA speed measuring board card through the PCIE bus to be measured, and arrange a speed measuring software unit used for being matched with the FPGA speed measuring board card for detecting the transmission speed of the PCIE bus to be measured in the Shenwei platform.
Therefore, compared with the prior art, the invention has prominent substantive features and remarkable progress, and the beneficial effects of the implementation are also obvious.
Drawings
Fig. 1 is a schematic diagram of a schematic structural diagram of a specific embodiment 1 of a PCIE bus speed measurement system based on an applicant platform according to the present invention.
Fig. 2 is a schematic flow chart of a method of an embodiment 1 of a PCIE bus speed measurement method based on a Shenwei platform according to the present invention.
Fig. 3 is a schematic block diagram of a schematic structure of a specific embodiment 1 of a PCIE bus speed measurement system based on an applicant platform according to the present invention.
Wherein: 1. the system comprises a Shenwei platform, 2 a Shenwei platform processor, 3 a PCIE expansion module, 4 an FPGA speed measurement board card, 5 a PCIE bus to be measured, 6 and a speed measurement software unit.
Detailed Description
In order to make the technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings.
Embodiment mode 1:
see fig. 1. Fig. 1 is a specific embodiment of a PCIE bus speed measurement system based on the Shenwei platform according to the present invention. In this embodiment, the PCIE bus speed measurement system based on the add-on-board platform includes a PCIE bus 5 to be measured, an add-on-board platform 1, and an FPGA speed measurement board 4 for receiving test data sent by the add-on-board platform 1 and for recording and feeding back a time length t used for transmitting the current test data; the test data has a specific size; a PCIE bus of the Shenwei platform processor 2 is connected with a PCIE expansion module 3, and the PCIE expansion module 3 is connected with the FPGA speed measurement board card 4 through a PCIE bus 5 to be measured; the Shenwei platform 1 is internally provided with a speed measurement software unit 6 which is used for being matched with the FPGA speed measurement board card 4 to detect the transmission rate of the PCIE bus 5 to be detected.
In this embodiment, the speed measurement software unit 6 includes a test data generation module, a test data transmission module, and a test result analysis processing module, where:
the test data generation module is used for generating test data;
the test data sending module is used for sending the test data generated by the test data generating module to the FPGA speed measuring board card 4 through the PCIE bus 5 to be tested;
and the test result analysis processing module is respectively connected with the test data generation module and the test data sending module, is used for receiving the time length t for current test data transmission fed back by the FPGA speed measurement board 4 (the time length t is the time t consumed from the time when the test data sending module sends the current test data to the time when the data transmission is completed), and is used for calculating and displaying the transmission rate v of the PCIE bus 5 to be tested through the Wei Shen platform 1 based on the currently received time length t and the size of the currently transmitted data.
In this embodiment, the method for calculating the PCIE transmission rate by the test result analysis processing module is as follows: the PCIE transmission rate v is obtained by dividing the size data (such as 1 GB) of the current test data by the currently received time length t. The size data of the current test data can be preset according to the specific size of the test data which can be generated by the test data generation module, and the size of the current generated test data can also be fed back by the test data generation module. In this embodiment, the size (data) of the current test data is fed back by the test data generation module, that is, the test data generation module generates the test data with a specific size and then directly sends the size of the generated test data to the test result analysis processing module.
When the test data generating module is used, the Shenwei platform system is started, the speed measuring software unit 6 is operated, the speed measuring software unit 6 calls the test data generating module to generate test data, the speed measuring software unit 6 calls the test data transmitting module, and the test data generated by the test data generating module is transmitted to the FPGA speed measuring board card 4 through the PCIE expansion module 3 and the PCIE bus 5 to be tested; the FPGA speed measurement board card 4 receives test data sent by the Shenwei platform 1 (through the PCIE bus 5 to be tested) and records and feeds back the time length t used for transmitting the current test data; and a test result analysis processing module of a speed measurement software unit 6 in the Shenwei platform 1 receives the time length t for transmitting the current test data fed back by the FPGA speed measurement board 4, and calculates and displays the transmission rate v of the PCIE bus 5 to be tested through the Shenwei platform 1 based on the currently received time length t and the size of the test data for transmitting the current time.
It should be noted that, in the PCIE expansion module 3 described in this embodiment, a PEX 8632 chip is used to expand multiple PCIE interfaces, and those skilled in the art may also use other PCIE interface expansion chips to expand each corresponding PCIE interface; the FPGA speed measurement board 4 is integrated with a PCIE bus, which supports the PCIE bus speed measurement system based on the Shenwei platform to detect the communication speed of different PCIE buses such as PCIE X4, PCIE X8, PCIE X16, and the like.
See fig. 2. Fig. 2 is a specific embodiment of a PCIE bus speed measurement method based on an Shenwei platform based on the PCIE bus speed measurement system based on the Shenwei platform. In this embodiment, the PCIE bus speed measurement method based on the Shenwei platform includes the following steps s1 to s4, and the detection of the transmission rate of the PCIE bus 5 to be detected is realized based on the steps s1 to s 4.
s1, a PCIE bus of the Shenwei platform processor 2 is connected with a PCIE expansion module 3, and the PCIE expansion module 3 is connected with the FPGA speed measurement board card 4 through a PCIE bus 5 to be measured; the FPGA speed measurement board card 4 is used for receiving test data sent by the Shenwei platform 1 based on the PCIE expansion module 3 and recording and feeding back the time length t used for transmitting the current test data.
s2, a speed measurement software unit 6 is arranged in the shenwei platform 1 and used for being matched with the FPGA speed measurement board card 4 to detect the transmission rate of the PCIE bus 5 to be detected.
s3, Shenwei platform system start.
Specifically, the system boot of the chenwei platform 1 in the step s3 includes three steps of power-on boot of the chenwei platform 1, kernel boot and operating system boot, where:
the Shenwei platform is powered on and started, and the BIOS identifies and initializes the FPGA speed measurement board card 4;
in the process of kernel starting, FIXUP configuration is carried out on a bus and equipment of the FPGA speed measurement board card 4, and an interrupt number is distributed;
and in the starting process of the operating system, loading the drive of the FPGA speed measurement board card 4 and realizing the initialization of the FPGA speed measurement board card 4.
The FPGA speed measurement board 4 is a board using PCIE buses (supporting communications of different interfaces such as PCIE X4, PCIE X8, PCIE X16, and the like), an FPGA chip is integrated in the board, and includes an IP core, and the FPGA chip of the FPGA speed measurement board 4 is connected to the PCIE extension module 3 through the PCIE bus to be measured via the PCIE bus 5.
According to the PCIE bus speed measuring system based on the Shenwei platform, after the FPGA speed measuring board card 4 is powered on, based on the step s3, the speed measuring software unit 6 of the Shenwei platform 1 is started, and the speed measuring software unit 6 calls the drive of the FPGA speed measuring board card 4 to perform data communication with the IP core of the FPGA speed measuring board card 4.
As can be seen, after the shenwei platform system is started, based on the shenwei platform 1, the data communication between the PCIE expansion module 3 in the PCIE bus speed measurement system to be measured and the FPGA speed measurement board 4 is realized.
s4, the speed measurement software unit 6 is started, and the test data is sent to the FPGA speed measurement board 4 based on the PCIE extension module 3 to test the transmission rate of the PCIE bus 5 to be tested.
Specifically, the speed measurement software unit 6 includes a test data generation module, a test data transmission module, and a test result analysis processing module, wherein:
the test data generation module is used for generating test data;
the test data sending module is used for sending the test data generated by the test data generating module to the FPGA speed measuring board card 4 through the PCIE bus 5 to be tested;
and the test result analysis processing module is respectively connected with the test data generation module and the test data sending module, is used for receiving the time length t used by the current test data transmission fed back by the FPGA speed measurement board card 4, and is used for calculating and controlling the Shenwei platform 1 to display the transmission rate v of the PCIE bus 5 to be tested based on the currently received time length t and the size of the current transmitted data.
Corresponding to the PCIE bus speed measurement method based on the shenwei platform, after the shenwei platform system is started, the speed measurement software unit 6 in the shenwei platform 1 is operated, the speed measurement software unit 6 calls the test data generation module to generate test data, the speed measurement software unit 6 calls the test data transmission module, the test data transmission module calls the driving interface of the FPGA speed measurement board 4 in the shenwei platform 1, and the test data generated by the test data generation module is transmitted to the FPGA chip of the FPGA speed measurement board 4 through the PCIE extension module 3 through the PCIE bus 5 to be tested; the FPGA chip of the FPGA speed measurement board card 4 receives test data sent by the Shenwei platform 1 (through the PCIE bus 5 to be tested) and records and feeds back the time length t used for transmitting the current test data; and a test result analysis processing module of a speed measurement software unit 6 in the Shenwei platform 1 receives the time length t for transmitting the current test data fed back by the FPGA speed measurement board 4, and calculates and displays the transmission rate v of the PCIE bus 5 to be tested through the Shenwei platform 1 based on the currently received time length t and the size of the test data for transmitting the current time.
It should be noted that, in this embodiment, the method for recording and feeding back the time length t used for transmitting the current test data by the FPGA speed measurement board includes: after receiving the data transmission notification of the speed measurement software unit 6 in the Shenwei platform 1, the FPGA speed measurement board 4 sets the receiving flag of the board firmware as begin to receive begin, and records the time t 1; after the data to be tested is received, the receiving flag bit is set as end, and the time t2 is recorded; then, the FPGA speed measurement board card 4 internally calculates the time length t = t2-t1 used for the transmission of the current test data; and finally, the FPGA speed measurement board card 4 is communicated with a driving interface of the FPGA speed measurement board card 4 in the Shenwei platform 1 through internal firmware of the FPGA speed measurement board card, and the calculated time length t = t2-t1 used for transmitting the current test data is fed back to the speed measurement software unit 6. In specific implementation, a person skilled in the art can select a corresponding method from the prior art according to actual conditions to record and feed back the time length t used for transmitting the current test data through the FPGA speed measurement board card.
Embodiment mode 2:
see fig. 3. Fig. 3 is another embodiment of a PCIE bus speed measurement system based on the Shenwei platform according to the present invention. Compared with the above specific embodiment 1, the difference of this embodiment 2 is that, in the PCIE bus speed measurement system based on the Shenwei platform, the speed measurement software unit 6 further includes a test frequency setting module, and the test frequency setting module is connected to the test result analysis processing module and is configured to set the detection frequency for the transmission rate test of the PCIE bus 5 to be tested. In addition, in embodiment 2, in the PCIE bus speed measurement system based on the Shenwei platform, the test result analysis processing module of the speed measurement software unit 6 is further configured to, when the detection times input by the test time setting module are greater than 1, invoke the test data sending module to execute the test data cycle sending operation of the detection times, and be configured to correspondingly calculate and display the transmission rate v corresponding to the test data sent each time through the Shenwei platform 1, and also be configured to calculate and display an arithmetic average value of all the transmission rates v obtained through the calculation through the Shenwei platform 1, where the average value is the transmission rate of the PCIE bus 5 to be detected finally.
Wherein, the input interface (i.e. input dialog box) corresponding to the test frequency setting module is displayed by the Shenwei platform 1, when in use, a tester sets the detection frequency for testing the transmission rate of the current PCIE bus 5 to be tested by the input interface of the test frequency setting module, the test result analysis processing module of the speed measurement software unit 6 judges the detection frequency input by the test frequency setting module, and when the detection frequency is judged to be greater than the number 1, the test data sending module is called to carry out the cyclic sending operation for the detection frequency for the test data generated by the test data generating module, and the time length t for transmitting the test data fed back by the FPGA speed measurement board 4 when receiving the test data each time is also based on the size of the test data and the received time length t for transmitting the test data each time, respectively calculating and displaying the transmission rate v of each transmission of test data of the PCIE bus 5 to be tested through the current Shenwei platform 1; finally (a test result analysis processing module of the speed measurement software unit 6) an arithmetic mean value is taken for all the transmission rates v obtained by the calculation, and the mean value is displayed through the power application platform 1, and the mean value is the transmission rate of the PCIE bus 5 to be detected and obtained finally. In the embodiment, a mode of measuring and averaging for multiple times is adopted, so that the accuracy and the reliability of the detection result are improved.
The present embodiment further provides a PCIE bus speed measurement method based on an Shenwei platform based PCIE bus speed measurement system in this embodiment, and compared with the PCIE bus speed measurement method based on the Shenwei platform in the above embodiment 1, the difference is that in the PCIE bus speed measurement method based on the Shenwei platform in this embodiment, the speed measurement software unit 6 further includes a test frequency setting module, which is connected to the test result analysis processing module and is used to set the detection frequency for the transmission rate test of the PCIE bus 5 to be tested; the test result analyzing and processing module of the speed measuring software unit 6 is further configured to, when the number of detection times input by the test number setting module is greater than 1, invoke the test data sending module to execute the test data cycle sending operation of the number of detection times, and is further configured to correspondingly calculate and display, through the charpy platform 1, the transmission rate v corresponding to the test data sent each time, and is further configured to calculate and display, through the charpy platform 1, an arithmetic average of all the transmission rates v obtained by the calculation, where the average is the transmission rate of the PCIE bus 5 to be detected finally.
The details of the using process of the test-frequency-based setting module are described in the PCIE bus speed measurement system part based on the applicant platform in this embodiment, and are not described herein again.
It should be noted that, the FPGA speed measurement board 4 described in the present invention can not only feed back the transmission rate v corresponding to each transmission of the test data of the PCIE bus 5 to be tested to the speed measurement software unit 6 of the Shenwei platform 1, but also can be used to detect and feed back the integrity of each transmission of the test data of the PCIE bus 5 to be tested.
In addition, each of the Shenwei platforms according to the embodiments of the present invention is a Shenwei computer or a Shenwei server.
The above embodiments are only for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may be modified or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (8)
1. A PCIE bus speed measuring system based on an Shenwei platform is characterized by comprising a PCIE bus (5) to be measured, the Shenwei platform (1), an FPGA speed measuring board card (4) for receiving test data sent by the Shenwei platform (1) and recording and feeding back the time length t used by the current test data transmission; the test data has a specific size;
a PCIE bus of the Shenwei platform processor (2) is connected with a PCIE expansion module (3), and the PCIE expansion module (3) is connected with the FPGA speed measurement board card (4) through a PCIE bus (5) to be measured;
a speed measurement software unit (6) which is used for being matched with the FPGA speed measurement board card (4) to be used for detecting the transmission rate of the PCIE bus (5) to be detected is arranged in the Shenwei platform (1);
the speed measurement software unit (6) comprises a test data generation module, a test data sending module and a test result analysis processing module, wherein:
the test data generation module is used for generating test data;
the test data sending module is used for sending the test data generated by the test data generating module to the FPGA speed measuring board card (4) through the PCIE bus (5) to be tested;
and the test result analysis processing module is respectively connected with the test data generation module and the test data sending module, is used for receiving the time length t used by current test data transmission fed back by the FPGA speed measurement board card (4), and is used for calculating and displaying the transmission rate v of the PCIE bus (5) to be tested through the Shenwei platform (1) based on the currently received time length t and the size of the current transmitted data.
2. The PCIE bus speed measurement system based on an Shenwei platform as claimed in claim 1, wherein the speed measurement software unit (6) further comprises a test frequency setting module, and the test frequency setting module is connected to the test result analysis processing module and configured to set a detection frequency for the transmission rate test of the PCIE bus (5) to be tested;
the test result analyzing and processing module is further configured to, when the number of detection times input by the number-of-test setting module is greater than 1, invoke the test data sending module to execute test data cycle sending operation for the number of detection times, and is further configured to correspondingly calculate and display, through the nware platform (1), a transmission rate v corresponding to the test data sent each time, and is further configured to calculate and display, through the nware platform (1), an arithmetic average of all the transmission rates v obtained by the calculation, where the arithmetic average is the transmission rate of the PCIE bus (5) to be detected finally.
3. The PCIE bus speed measurement system based on an Shenwei platform as claimed in any one of claims 1 to 2, wherein the FPGA speed measurement board (4) integrates a PCIE bus to support speed measurement of PCIE X4, PCIE X8 and PCIE X16 buses.
4. A PCIE bus speed measurement method based on the PCIE bus speed measurement system based on the Shenwei platform as recited in claim 1, comprising the steps of:
s1, a PCIE bus of the Shenwei platform processor (2) is connected with a PCIE expansion module (3), and the PCIE expansion module (3) is connected with the FPGA speed measurement board card (4) through a PCIE bus (5) to be measured; the FPGA speed measurement board card (4) is used for receiving test data sent by the Shenwei platform based on the PCIE expansion module (3) and recording and feeding back the time length t used for transmitting the current test data;
s2, a speed measurement software unit (6) which is used for being matched with the FPGA speed measurement board card (4) to be used for detecting the transmission rate of the PCIE bus (5) to be detected is arranged in the Shenwei platform (1);
s3, starting the Shenwei platform system;
s4, starting the speed measurement software unit (6), and sending the test data to the FPGA speed measurement board card (4) through the PCIE expansion module (3) to test the transmission rate of the PCIE bus (5) to be tested;
the speed measurement software unit (6) comprises a test data generation module, a test data sending module and a test result analysis processing module, wherein:
the test data generation module is used for generating test data;
the test data sending module is used for sending the test data generated by the test data generating module to the FPGA speed measuring board card (4) through the PCIE bus (5) to be tested;
and the test result analysis processing module is respectively connected with the test data generation module and the test data sending module, is used for receiving the time length t used by current test data transmission fed back by the FPGA speed measurement board card (4), and is used for calculating and displaying the transmission rate v of the PCIE bus (5) to be tested through the Shenwei platform (1) based on the currently received time length t and the size of the current transmitted data.
5. The PCIE bus speed measuring method based on the Shenwei platform as claimed in claim 4, wherein the step s3 of starting the Shenwei platform system includes the steps of:
the Shenwei platform (1) is powered on and started, and the BIOS identifies and initializes the FPGA speed measurement board card (4);
in the process of kernel starting, FIXUP configuration is carried out on a bus of the FPGA speed measurement board card (4) and equipment thereof, and an interrupt number is distributed;
and in the starting process of the operating system, loading the drive of the FPGA speed measurement board card (4), and realizing the initialization of the FPGA speed measurement board card (4).
6. The PCIE bus speed measurement method based on an Shenwei platform as claimed in claim 4, wherein the speed measurement software unit (6) further comprises a test frequency setting module, and the test frequency setting module is connected to the test result analysis processing module and configured to set a detection frequency for the transmission rate test of the PCIE bus (5) to be tested;
the test result analysis processing module is used for calling the test data sending module to execute test data cycle sending operation for the detection times when the detection times input by the test time setting module are larger than 1, correspondingly calculating and displaying the transmission rate v corresponding to the test data sent each time through the Shenwei platform (1), and calculating and displaying the arithmetic mean value of all the transmission rates v obtained through calculation through the Shenwei platform (1), wherein the arithmetic mean value is the transmission rate of the PCIE bus (5) to be detected finally.
7. The PCIE bus speed measuring method based on the Shenwei platform as claimed in claim 4 or 5, wherein the FPGA speed measuring board card (4) is integrated with a PCIE bus to support the speed measurement of the PCIE X4, PCIE X8 and PCIE X16 buses.
8. The PCIE bus speed measuring method based on the Shenwei platform as claimed in claim 4 or 5, wherein the method for the FPGA speed measuring board card (4) to record and feed back the time length t used by the current test data transmission is as follows:
after the FPGA speed measurement board card (4) receives the data sending notification of the speed measurement software unit (6) in the Shenwei platform (1), setting a receiving flag of the board card firmware as beginning to receive begin, and recording time t 1;
after the data to be tested is received, the receiving flag bit is set as end, and the time t2 is recorded;
then, the time length t used for transmitting the current test data is calculated by the FPGA speed measurement board card (4) as t2-t 1;
and finally, the FPGA speed measurement board card (4) is communicated with a driving interface driven by the FPGA speed measurement board card (4) in the Shenwei platform (1) through internal firmware of the FPGA speed measurement board card, and the calculated time length t used for transmitting the current test data is fed back to the speed measurement software unit (6) when t is t2-t 1.
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