CN108964700B

CN108964700B - Radio frequency circuit

Info

Publication number: CN108964700B
Application number: CN201710392759.2A
Authority: CN
Inventors: 邓喜荣; 张明贵
Original assignee: Nanning Fugui Precision Industrial Co Ltd
Current assignee: Nanning Fulian Fugui Precision Industrial Co Ltd
Priority date: 2017-05-27
Filing date: 2017-05-27
Publication date: 2020-08-28
Anticipated expiration: 2037-05-27
Also published as: CN108964700A

Abstract

A radio frequency circuit for transceiving a radio signal in multiple frequency bands, the radio frequency circuit comprising: the antenna, the transceiver circuit, the adjustable circuit and the processor. Wherein the antenna is used for transmitting wireless signals. The transceiver circuit is used for transmitting and receiving wireless signals. The adjustable circuit is electrically connected between the antenna and the transceiver circuit and used for adjusting the capacitance value of the capacitor so as to filter out a preset frequency band signal in the wireless signal. The processor is connected with the transceiving circuit and the adjustable circuit and is used for controlling the transceiving circuit to carry out transceiving processing on the wireless signals and controlling adjustment of the adjustable circuit. The radio frequency circuit provided by the invention can reduce the reuse of radio frequency elements and can also reduce the interference introduced by the radio frequency switch.

Description

Radio frequency circuit

Technical Field

The invention relates to the field of communication, in particular to a radio frequency circuit.

Background

Currently, most products use multiple frequency bands for communication. Because the conventional radio frequency architecture is commonly used in different communication systems, in application, the different communication systems use a power amplifier, a surface acoustic wave element and a frequency division multiplexer, which are required by the system. Therefore, in the design of the radio frequency architecture, the used devices are inevitably and repeatedly burdensome, and a great deal of waste of resources and space is caused. Meanwhile, in the conventional rf architecture, an rf switch is often used to switch between different transmitting frequency bands and different receiving frequency bands. But current is lost and unnecessary interference is generated due to the operation of the rf switch.

Disclosure of Invention

Therefore, it is desirable to provide a radio frequency circuit to solve the above problems.

An embodiment of the present invention provides a radio frequency circuit for transceiving a wireless signal in multiple frequency bands, the radio frequency circuit including: the antenna, the transceiver circuit, the adjustable circuit and the processor. Wherein the antenna is used for transmitting wireless signals. The transceiver circuit is used for transmitting and receiving wireless signals. The adjustable circuit is electrically connected between the antenna and the transceiver circuit and used for adjusting the capacitance value of the capacitor so as to filter out a preset frequency band signal in the wireless signal. The processor is electrically connected with the transceiver circuit and the adjustable circuit and is used for controlling the transceiver circuit to perform the transceiving processing of the wireless signals and controlling the adjustment of the adjustable circuit.

Preferably, the transceiver circuit comprises: the first amplifier, the first duplexer, the second amplifier and the second duplexer. The transceiver is used for transceiving wireless signals. The first amplifier is electrically connected with the transceiver and used for amplifying a first preset frequency band signal in the preset frequency band signals. The first duplexer is electrically connected between the first amplifier and the adjustable circuit and used for isolating a first receiving signal and a first transmitting signal in the first preset frequency band signal so as to share the antenna. The second amplifier is electrically connected to the transceiver and is used for amplifying a second preset frequency band signal in the preset frequency band signals. The second duplexer is electrically connected between the second amplifier and the adjustable circuit and used for isolating a second receiving signal and a second transmitting signal in the second preset frequency band signal so as to share the antenna.

Preferably, the transceiver circuit further comprises at least one third amplifier and at least one third duplexer. The third amplifier is electrically connected to the transceiver and is configured to amplify a third predetermined frequency band signal of the predetermined frequency band signals. The third duplexer is electrically connected between the third amplifier and the adjustable circuit, and is used for isolating a third receiving signal and a third transmitting signal in a third preset frequency band signal so as to share the antenna.

Preferably, the adjustable circuit comprises: the inductor comprises a first inductor, a second inductor, a third inductor, a first variable capacitor, a second variable capacitor, a third variable capacitor, a first conversion circuit, a second conversion circuit and a third conversion circuit.

The first end of the first inductor is electrically connected with the antenna, and the second end of the first inductor is electrically connected with the ground. The first end of the first variable capacitor is electrically connected with the first end of the first inductor, and the second end of the first variable capacitor is electrically connected with the ground. The first end of the second inductor is electrically connected with the first end of the first inductor. The first end of the second variable capacitor is electrically connected with the second end of the second inductor, and the second end of the second variable capacitor is electrically connected with the transceiver circuit. The first end of the third inductor is electrically connected with the second end of the second variable capacitor, and the second end of the third inductor is electrically connected with the ground. The first end of the third variable capacitor is electrically connected with the first end of the third inductor, and the second end of the third variable capacitor is electrically connected with the ground. The first conversion circuit is electrically connected with the processor and used for converting a first control signal sent by the processor into a first analog signal with a preset voltage and outputting the first analog signal to the first variable capacitor so as to adjust the capacitance value of the first variable capacitor. The second conversion circuit is electrically connected with the processor and is used for converting a second control signal sent by the processor into a second analog signal with a preset voltage and outputting the second analog signal to the second variable capacitor so as to adjust the capacitance value of the second variable capacitor. The third conversion circuit is electrically connected with the processor and is used for converting a third control signal sent by the processor into a third analog signal with a preset voltage and outputting the third analog signal to the third variable capacitor so as to adjust the capacitance value of the third variable capacitor.

Preferably, the first conversion circuit includes: the first digital-to-analog converter, the first integrated operational amplifier, the first resistor and the second resistor. The first digital-to-analog converter is electrically connected with the processor and is used for converting the first control signal into a first analog signal. The input end of the first integrated operational amplifier is electrically connected with the first digital-to-analog converter and used for adjusting and outputting the voltage of the first analog signal. The first end of the first resistor is electrically connected with the input end of the first integrated operational amplifier. The first end of the second resistor is electrically connected with the second end of the first resistor and the output end of the first integrated operational amplifier, and the second end of the second resistor is electrically connected with the ground.

Preferably, the second conversion circuit includes: the second digital-to-analog converter, the second integrated operational amplifier, the third resistor and the fourth resistor. The second digital-to-analog converter is electrically connected with the processor and is used for converting the second control signal into a second analog signal. The input end of the second integrated operational amplifier is electrically connected with the second digital-to-analog converter and used for adjusting and outputting the voltage of the second analog signal. The first end of the third resistor is electrically connected with the input end of the second integrated operational amplifier. The first end of the fourth resistor is electrically connected with the second end of the third resistor and the output end of the second integrated operational amplifier, and the second end of the fourth resistor is electrically connected with the ground.

Preferably, the third conversion circuit includes: the third digital-to-analog converter, the third integrated operational amplifier, the fifth resistor and the sixth resistor. The third digital-to-analog converter is electrically connected with the processor and is used for converting the third control signal into a third analog signal. The input end of the third integrated operational amplifier is electrically connected with the third digital-to-analog converter and used for adjusting and outputting the voltage of the third analog signal. The first end of the fifth resistor is electrically connected with the input end of the third integrated operational amplifier. The first end of the sixth resistor is electrically connected with the second end of the fifth resistor and the output end of the third integrated operational amplifier, and the second end of the sixth resistor is electrically connected with the ground.

Preferably, the processor communicates with the adjustable circuit through a single serial peripheral interface.

The radio frequency circuit provided by the invention can reduce the reuse of radio frequency elements and can also reduce the interference introduced by the radio frequency switch.

Drawings

Fig. 1 is a schematic diagram of an embodiment of a radio frequency circuit according to the invention.

Fig. 2 is a schematic diagram of a tunable circuit according to another embodiment of the rf circuit of the present invention.

Fig. 3 is a return loss measurement diagram of an embodiment of the rf circuit of the present invention.

Fig. 4 is a return loss measurement diagram of an embodiment of the rf circuit of the present invention.

Fig. 5 is a return loss measurement diagram of an embodiment of the rf circuit of the present invention.

Fig. 6 is a return loss measurement diagram of an embodiment of the rf circuit of the present invention.

Description of the main elements

Radio frequency circuit R

Antenna A1

Transceiver circuit RF

Adjustable circuit M1

Processor DSP

First amplifier PA1

Second amplifier PA2

Third amplifier PA3-PA5

First duplexer D1

Second duplexer D2

Third duplexer D3-D5

Transceiver T1

First inductance L1

Second inductance L2

Third inductance L3

First variable capacitor C1

Second variable capacitor C2

Third variable capacitance C3

First conversion circuit Z1

Second switching circuit Z2

Third switching circuit Z3

First digital-to-analog converter DAC1

Second digital to analog converter DAC2

Third digital-to-analog converter DAC3

First integrated operational amplifier G1

Second integrated operational amplifier G2

Third integrated operational amplifier G3

First resistor R1

Second resistor R2

Third resistor R3

Fourth resistor R4

Fifth resistor R5

Sixth resistor R6

Single serial peripheral interface SSBI

First control signal P1

Second control signal P2

Third control signal P3

The following detailed description will further illustrate the invention in conjunction with the above-described figures.

Detailed Description

The invention provides a radio frequency circuit R which is used for receiving and transmitting multi-band wireless signals. In the described embodiment of the present invention, the multiband mainly refers to a signal band commonly used in daily life, such as an operating band of Long Term Evolution (LTE), an operating band of Universal Mobile Telecommunications System (UMTS), and an operating band of Code Division Multiple Access (CDMA). In other embodiments, communication circuits in other system operating frequency bands may also be constructed based on the radio frequency architecture designed by the present invention.

Referring to fig. 1, fig. 1 is a schematic diagram of an embodiment of a radio frequency circuit R according to the invention.

In the present embodiment, the radio frequency circuit R includes: an antenna a1, a transceiver circuit RF, an adjustable circuit M1 and a processor DSP. Antenna a1 is used for transmitting wireless signals. The transceiver circuit RF is used for performing a process of transmitting and receiving a radio signal. The adjustable circuit M1 is electrically connected between the antenna a1 and the transceiver circuit RF, and is configured to adjust a capacitance of the capacitor, so as to filter out a predetermined frequency band signal in the wireless signal. The processor DSP is electrically connected to the transceiver circuit RF and the adjustable circuit M1, and is configured to control the transceiver circuit RF to perform transceiving processing of wireless signals and control adjustment of the adjustable circuit M1.

The transceiver circuit RF includes a transceiver T1, a first amplifier PA1, a first duplexer D1, a second amplifier PA2, and a second duplexer D2. The transceiver T1 is used for transceiving wireless signals. The first amplifier PA1 is electrically connected to the transceiver T1, and is configured to amplify a first predetermined frequency band signal of the predetermined frequency band signals. The first duplexer D1 is electrically connected between the first amplifier PA1 and the adjustable circuit M1, and is configured to isolate a first received signal and a first transmitted signal of the first predetermined frequency band signal, so as to share the antenna a 1. The second amplifier PA2 is electrically connected to the transceiver T1, and is configured to amplify a second predetermined frequency band signal of the predetermined frequency band signals. The second duplexer D2 is electrically connected between the second amplifier PA2 and the adjustable circuit M1, and is configured to isolate a second received signal and a second transmitted signal of the second predetermined frequency band signal, so as to share the antenna a 1.

Specifically, the operating frequency band of the communication circuit in which the first amplifier PA1 and the first duplexer D1 are located is mainly suitable for the LTE B5 operating frequency band, the UMTS B5 operating frequency band, and the CDMA BC0 operating frequency band which have substantially the same operating frequency band. The working frequency band of the communication circuit in which the second amplifier PA2 and the second duplexer D2 are located is mainly suitable for the LTEB8 working frequency band and the UMTS B8 working frequency band which have substantially the same working frequency band.

In this embodiment, more independent communication bands can be applied to the transceiver circuit RF, and as shown in fig. 1, the transceiver circuit RF of this embodiment may further include some communication circuit operating bands other than the operating bands of the first amplifier PA1, the first duplexer D1, the second amplifier PA2, and the second duplexer D2. Specifically, the transceiver circuit RF of the present embodiment further includes: the at least one third amplifier PA3-PA5, the third amplifier PA3-PA5 are electrically connected to the transceiver T1 for amplifying a third predetermined frequency band signal of the predetermined frequency band signals. At least one third duplexer D3-D5, the third duplexer D3-D5 are electrically connected between the third amplifier PA3-PA5 and the adjustable circuit M1, respectively, for isolating a third receiving signal and a third transmitting signal in a third predetermined frequency band signal to share the antenna A1. The working frequency bands of the communication circuits in which the third amplifiers PA3-PA5 and the third duplexers D3-D5 are located are mainly suitable for working frequency bands having substantially the same working frequency band, such as the working frequency bands of LTE B3 and UMTS B3, or the working frequency bands of LTE B2, UMTS B2 and CDMA BC1, or the working frequency bands of LTE B5, UMTS B5 and CDMA BC 0.

Referring to fig. 2, fig. 2 is a schematic diagram of an embodiment of an adjustable circuit M1 of a radio frequency circuit R according to the invention.

In this embodiment, the adjustable circuit M1 includes: the circuit comprises a first inductor L1, a first variable capacitor C1, a second inductor L2, a second variable capacitor C2, a third inductor L3, a third variable capacitor C3, a first conversion circuit Z1, a second conversion circuit Z2 and a third conversion circuit Z3.

The first end of the first inductor L1 is electrically connected to the antenna a1, and the second end of the first inductor L1 is electrically connected to ground. The first end of the first variable capacitor C1 is electrically connected to the first end of the first inductor L1, and the second end of the first variable capacitor C1 is electrically connected to ground. The first end of the second inductor L2 is electrically connected to the first end of the first inductor L1. A first terminal of the second variable capacitor C2 is electrically connected to the second terminal of the second inductor L2, and a second terminal of the second variable capacitor C2 is electrically connected to the transceiver circuit RF. The first terminal of the third inductor L3 is electrically connected to the second terminal of the second variable capacitor C2, and the second terminal of the third inductor L3 is electrically connected to ground. The first terminal of the third variable capacitor C3 is electrically connected to the first terminal of the third inductor L3, and the second terminal of the third variable capacitor C3 is electrically connected to ground. In this embodiment, each tunable capacitor is a voltage-controlled tunable capacitor, and when the signal voltage received by the tunable capacitor changes, the capacitance value of the tunable capacitor changes. In other embodiments, voltage-controlled varactors may be used in place of the adjustable capacitors.

The first conversion circuit Z1 is electrically connected to the processor DSP, and is configured to convert a first control signal P1 sent by the processor DSP into a first analog signal with a preset voltage and output the first analog signal to the first variable capacitor C1, so as to adjust a capacitance value of the first variable capacitor C1. The second converting circuit Z2 is electrically connected to the processor DSP, and is configured to convert the second control signal P2 sent by the processor DSP into a second analog signal with a preset voltage and output the second analog signal to the second variable capacitor C2, so as to adjust a capacitance value of the second variable capacitor C2. The third converting circuit Z3 is electrically connected to the processor DSP, and is configured to convert a third control signal P3 sent by the processor DSP into a third analog signal with a preset voltage and output the third analog signal to the third variable capacitor C3, so as to adjust a capacitance value of the third variable capacitor C3.

Specifically, the first conversion circuit Z1 includes: the digital-to-analog converter comprises a first digital-to-analog converter DAC1, a first integrated operational amplifier G1, a first resistor R1 and a second resistor R2. The first DAC1 is electrically connected to the processor DSP and is configured to convert the first control signal P1 into a first analog signal. The input end of the first integrated operational amplifier G1 is electrically connected to the first DAC1, and is configured to adjust and output a voltage of the first analog signal. The first end of the first resistor R1 is electrically connected to the input terminal of the first integrated operational amplifier G1. The first end of the second resistor R2 is electrically connected to the second end of the first resistor R1 and the output end of the first integrated operational amplifier G1, and the second end of the second resistor R2 is electrically connected to ground.

The second conversion circuit Z2 includes: a second digital-to-analog converter DAC2, a second integrated operational amplifier G2, a third resistor R3, and a fourth resistor R4. The second DAC2 is electrically connected to the processor DSP for converting the second control signal P2 into a second analog signal. The second integrated operational amplifier G2, an input terminal of the second integrated operational amplifier G2 is electrically connected to the second digital-to-analog converter DAC2, and is configured to adjust and output a voltage of the second analog signal. The first end of the third resistor R3 is electrically connected to the input end of the second integrated operational amplifier G2. The first end of the fourth resistor R4 is electrically connected to the second end of the third resistor R3 and the output end of the second integrated operational amplifier G2, and the second end of the fourth resistor R4 is electrically connected to ground.

The third conversion circuit Z3 includes: a third DAC3, a third integrated operational amplifier G3, a fifth resistor R5, and a sixth resistor R6. The third DAC3 is electrically connected to the processor DSP, and is configured to convert the third control signal P3 into a third analog signal. The input end of the third integrated operational amplifier G3 is electrically connected to the third DAC3, and is configured to adjust and output the voltage of the third analog signal. The first end of the fifth resistor R5 is electrically connected to the input terminal of the third integrated operational amplifier G3. The first end of the sixth resistor R6 is electrically connected to the second end of the fifth resistor R5 and the output end of the third integrated operational amplifier G3, and the second end of the sixth resistor R6 is electrically connected to ground.

The first DAC1, the second DAC2 and the third DAC3 may all use 8-bit DACs to improve the accuracy of the DAC conversion. The processor DSP communicates with the adjustable circuit M1 via a Single-Wire Serial Bus Interface (SSBI). The interface outputs corresponding control signals to adjust the capacitance value of each variable capacitor, so that the adjustable circuit M1 can filter out wireless signals of corresponding working frequency bands, and the purpose of sharing the communication circuit by systems in the same working frequency band is achieved. Please refer to the following embodiments for adjusting the capacitance.

Referring to fig. 3, fig. 3 is a return loss measurement diagram of the rf circuit R according to an embodiment of the invention.

As shown in fig. 3, during measurement, the processor DSP sends a control signal to the adjustable circuit M1 through the SSBI interface, the capacitance values of the variable capacitors in the adjustable circuit M1 change correspondingly, and when the capacitance values of the variable capacitors are the first preset values, the curve is as shown in fig. 3. If-9 dB is taken as a limit, the low-frequency resonance frequency band of the radio frequency circuit R is about 780MHz-903MHz, and the high-frequency resonance frequency band thereof is about 1710MHz-2700 MHz. In this embodiment, when the capacitance value of each variable capacitor is the first preset value, the voltage received by the first variable capacitor C1 is 5 volts (V), and the capacitance value is 1.8 picofarads (pf); the voltage received by the second variable capacitor C2 is 1 volt (V), and the capacitance value of the capacitor is 10 picofarads (pf); the third variable capacitor C3 receives a voltage of 5 volts (V) and a capacitance of 1.8 picofarads (pf). In other embodiments, the capacitance value and the received voltage of each variable capacitor may also be determined by observing the curve change in the graph, that is, when the curve shown in fig. 3 appears, the first preset value of each variable capacitor may be recorded, and when the resonance frequency band shown in the diagram needs to appear, each capacitor may be adjusted to the first preset value, so as to construct the required resonance frequency band.

Referring to fig. 4, fig. 4 is a return loss measurement diagram of the rf circuit R according to an embodiment of the invention.

As shown in fig. 4, during measurement, the processor DSP sends a control signal to the adjustable circuit M1 through the SSBI interface, the capacitance values of the variable capacitors in the adjustable circuit M1 change correspondingly, and when the capacitance values of the variable capacitors are the second preset values, the curve is as shown in fig. 4. If the limit is-9 dB, the low frequency resonance frequency band of the radio frequency circuit R is approximately 836MHz-985MHz, and the high frequency resonance frequency band thereof is approximately 1710MHz-2700 MHz. In this embodiment, when the capacitance value of each variable capacitor is the second preset value, the voltage received by the first variable capacitor C1 is 4.2 volts (V), and the capacitance value is 2.2 picofarads (pf); the voltage received by the second variable capacitor C2 is 1.5 volts (V), and the capacitance value of the capacitor is 9 picofarads (pf); the third variable capacitor C3 receives a voltage of 4.2 volts (V) and a capacitance of 2.2 picofarads (pf). In other embodiments, the capacitance value and the received voltage of each variable capacitor may also be determined by observing the curve change in the graph, that is, when the curve shown in fig. 4 appears, the second preset value of each variable capacitor may be recorded, and when the resonance frequency band shown in the diagram needs to appear, each capacitor may be adjusted to the second preset value, so as to construct the required resonance frequency band.

Referring to fig. 5, fig. 5 is a return loss measurement diagram of the rf circuit R according to an embodiment of the invention.

As shown in fig. 5, during measurement, the processor DSP sends a control signal to the adjustable circuit M1 through the SSBI interface, the capacitance values of the variable capacitors in the adjustable circuit M1 change correspondingly, and when the capacitance values of the variable capacitors are the third preset value, the curve is as shown in fig. 5. If the limit is-9 dB, the low-frequency resonance frequency band of the radio frequency circuit R is approximately 725MHz-842MHz, and the high-frequency resonance frequency band thereof is approximately 1710MHz-2700 MHz. In this embodiment, when the capacitance value of each variable capacitor is the third preset value, the voltage received by the first variable capacitor C1 is 3.5 volts (V), and the capacitance value is 2.5 picofarads (pf); the voltage received by the second variable capacitor C2 is 2.5 volts (V), and the capacitance value of the capacitor is 7 picofarads (pf); the third variable capacitor C3 receives a voltage of 3.5 volts (V) and a capacitance of 2.5 picofarads (pf). In other embodiments, the capacitance value and the received voltage of each variable capacitor may also be determined by observing the curve change in the graph, that is, when the curve shown in fig. 5 appears, the third preset value of each variable capacitor may be recorded, and when the resonant frequency band shown in the diagram needs to appear, each capacitor may be adjusted to the third preset value, so as to construct the required resonant frequency band.

Referring to fig. 6, fig. 6 is a return loss measurement diagram of the rf circuit R according to an embodiment of the invention.

As shown in fig. 6, during measurement, the processor DSP sends a control signal to the adjustable circuit M1 through the SSBI interface, the capacitance values of the variable capacitors in the adjustable circuit M1 change correspondingly, and when the capacitance values of the variable capacitors are the fourth preset value, the curve is as shown in fig. 6. If-9 dB is taken as a limit, the low-frequency resonance frequency band of the radio frequency circuit R is about 693MHz-807MHz, and the high-frequency resonance frequency band thereof is about 1710MHz-2700 MHz. In this embodiment, when the capacitance value of each variable capacitor is the fourth preset value, the voltage received by the first variable capacitor C1 is 3.2 volts (V), and the capacitance value is 3 picofarads (pf); the voltage received by the second variable capacitor C2 is 3 volts (V), and the capacitance value of the capacitor is 5 picofarads (pf); the third variable capacitor C3 receives a voltage of 3.2 volts (V) and a capacitance of 3 picofarads (pf). In other embodiments, the capacitance value and the received voltage of each variable capacitor may also be determined by observing the curve change in the graph, that is, when the curve shown in fig. 6 appears, the fourth preset value of each variable capacitor may be recorded, and when the resonance frequency band shown in the diagram needs to appear, each capacitor may be adjusted to the fourth preset value, so as to construct the required resonance frequency band.

The radio frequency circuit R provided by the invention can reduce the reuse of radio frequency elements and can also reduce the interference introduced by a radio frequency switch. .

It is understood that various other changes and modifications may be made by those skilled in the art based on the technical idea of the present invention, and all such changes and modifications should fall within the protective scope of the claims of the present invention.

Claims

1. A radio frequency circuit for transceiving a radio signal in multiple frequency bands, the radio frequency circuit comprising:

an antenna for transmitting the wireless signal;

the receiving and transmitting circuit is used for receiving and transmitting the wireless signals;

the adjustable circuit is electrically connected between the antenna and the transceiver circuit and used for adjusting the capacitance value of the capacitor so as to filter out a preset frequency band signal in the wireless signal; and

a processor electrically connected to the transceiver circuit and the adjustable circuit for controlling the transceiver circuit to perform the transceiving process of the wireless signal and controlling the adjustment of the adjustable circuit,

the adjustable circuit comprises:

a first end of the first inductor is electrically connected with the antenna, and a second end of the first inductor is electrically connected with ground;

a first variable capacitor, a first end of the first variable capacitor being electrically connected to a first end of the first inductor, a second end of the first variable capacitor being electrically connected to ground; and

the first conversion circuit is electrically connected with the processor and used for converting a first control signal sent by the processor into a first analog signal with preset voltage and outputting the first analog signal to the first variable capacitor so as to adjust the capacitance value of the first variable capacitor.

2. The radio frequency circuit of claim 1, wherein the transceiver circuit comprises:

a transceiver for transceiving the wireless signal;

the first amplifier is electrically connected with the transceiver and used for amplifying a first preset frequency band signal in the preset frequency band signals;

a first duplexer electrically connected between the first amplifier and the adjustable circuit, for isolating a first receiving signal and a first transmitting signal in the first preset frequency band signal to share the antenna;

the second amplifier is electrically connected with the transceiver and is used for amplifying a second preset frequency band signal in the preset frequency band signals; and

and the second duplexer is electrically connected between the second amplifier and the adjustable circuit and used for isolating a second receiving signal and a second transmitting signal in the second preset frequency band signal so as to share the antenna.

3. The radio frequency circuit of claim 2, wherein the transceiver circuit further comprises:

the third amplifier is electrically connected with the transceiver and is used for amplifying a third preset frequency band signal in the preset frequency band signals; and

at least one third duplexer, third duplexer electric connection in the third amplifier with between the adjustable circuit, be used for keeping apart third received signal and the third transmitted signal in the third preset frequency channel signal, in order to share the antenna.

4. The radio frequency circuit of claim 1, wherein the adjustable circuit further comprises:

the first end of the second inductor is electrically connected with the first end of the first inductor;

a first end of the second variable capacitor is electrically connected to a second end of the second inductor, and a second end of the second variable capacitor is electrically connected to the transceiver circuit;

a first end of the third inductor is electrically connected with a second end of the second variable capacitor, and a second end of the third inductor is electrically connected with ground;

a first end of the third variable capacitor is electrically connected with a first end of the third inductor, and a second end of the third variable capacitor is electrically connected with the ground;

the second conversion circuit is electrically connected with the processor and is used for converting a second control signal sent by the processor into a second analog signal with preset voltage and outputting the second analog signal to the second variable capacitor so as to adjust the capacitance value of the second variable capacitor; and

and the third conversion circuit is electrically connected with the processor and used for converting a third control signal sent by the processor into a third analog signal with a preset voltage and outputting the third analog signal to the third variable capacitor so as to adjust the capacitance value of the third variable capacitor.

5. The radio frequency circuit of claim 4, wherein the first conversion circuit comprises:

the first digital-to-analog converter is electrically connected with the processor and is used for converting the first control signal into the first analog signal;

the input end of the first integrated operational amplifier is electrically connected with the first digital-to-analog converter and is used for adjusting and outputting the voltage of the first analog signal;

a first end of the first resistor is electrically connected with the input end of the first integrated operational amplifier; and

and the first end of the second resistor is electrically connected with the second end of the first resistor and the output end of the first integrated operational amplifier, and the second end of the second resistor is electrically connected with the ground.

6. The radio frequency circuit of claim 4, wherein the second conversion circuit comprises:

the second digital-to-analog converter is electrically connected with the processor and is used for converting the second control signal into the second analog signal;

the input end of the second integrated operational amplifier is electrically connected with the second digital-to-analog converter and is used for adjusting and outputting the voltage of the second analog signal;

a first end of the third resistor is electrically connected with the input end of the second integrated operational amplifier; and

and a first end of the fourth resistor is electrically connected with the second end of the third resistor and the output end of the second integrated operational amplifier, and a second end of the fourth resistor is electrically connected with the ground.

7. The radio frequency circuit of claim 4, wherein the third conversion circuit comprises:

the third digital-to-analog converter is electrically connected with the processor and is used for converting the third control signal into the third analog signal;

the input end of the third integrated operational amplifier is electrically connected with the third digital-to-analog converter and is used for adjusting and outputting the voltage of the third analog signal;

a first end of the fifth resistor is electrically connected with the input end of the third integrated operational amplifier; and

and a first end of the sixth resistor is electrically connected with the second end of the fifth resistor and the output end of the third integrated operational amplifier, and a second end of the sixth resistor is electrically connected with the ground.

8. The radio frequency circuit of claim 1, wherein the processor communicates with the adjustable circuit through a single serial peripheral interface.