CN108964657A - Double mode for phaselocked loop linearizes charge pump circuit and charge and discharge core circuit - Google Patents
Double mode for phaselocked loop linearizes charge pump circuit and charge and discharge core circuit Download PDFInfo
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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Abstract
Double mode proposed by the present invention for phaselocked loop linearizes charge pump circuit and charge and discharge core circuit；A kind of charge and discharge core circuit constituting double mode linearisation charge pump circuit, including charging current source circuit, discharge current source circuit, offset current source circuit, sampling hold circuit, transmission gate, electric current interchange circuit, the first, second charge control tube, the first, second control of discharge pipe and switching tube；It is characterized by: the complementary signal one of the grid difference reception pattern selection circuit output of the first, second charge control tube；The complementary signal three of the grid difference reception pattern selection circuit output of first, second control of discharge pipe；The source electrode of first, second charge control tube connects charging current source circuit simultaneously；Mode selection circuit of the present invention, charge and discharge core circuit can switch between both of which, and phase-locked loop operation can be supported in built-in loop filter and external loop filter, can be widely applied in RF Phase-Lock Loop system.
Description
Technical field
The present invention relates to phaselocked loops, and in particular to the double mode for phaselocked loop linearizes charge pump circuit and charge and discharge core
Electrocardio road.
Background technique
Phaselocked loop is widely used in simulation, number and radio frequency chip, for providing clock frequency or local frequency.Locking phase
Ring is divided into analog phase-locked look and all-digital phase-locked loop two major classes, and wherein analog phase-locked look presses frequency dividing ratio coverage area, and divides integer
Frequency dividing phase-locked loop and fractional frequency-division phase-locked loop, fractional frequency-division phase-locked loop have the characteristics that high frequency resolution and high phase comparison frequency,
It is the prior development direction of current phaselocked loop product.
Typical decimal frequency divider phaselocked loop component units include: reference buffer, parametric frequency divider, phase frequency detector, electricity
The units such as lotus pump, loop filter, voltage controlled oscillator, feedback divider and Sigma-delta modulator, as shown in Figure 1.It is passing
It unites in fractional frequency-division phase-locked loop, the output signal and reference output signal of feedback divider pass through phase frequency detector and charge pump
Afterwards, charging current and discharge current are converted to, then voltage signal is converted to by loop filter, in the process, due to
Sigma-delta modulator function, in the rising edge time of different cycles, feedback divider phase of output signal compares reference point
Frequency device phase of output signal will appear advanced or hysteresis.
Conventional charge pump circuit has nonlinear characteristic, is easy to fold the high frequency treatment noise of Sigma-delta modulator
Into loop bandwidth, deteriorate phaselocked loop closed loop in-band phase noise, especially under wide loop bandwidth, deteriorates particularly evident.For solution
Certainly this problem, the way of mainstream is to increase constant deviation electric current in charge pump outputs at present, to realize the linear of charge pump
Change characteristic, when phaselocked loop loop filter is external, this linearisation charge pump generates big output voltage fluctuation, can pass through
Loop filter inhibits, if cycle of phase-locked loop filter be it is fully integrated, since loop filter component values can not select
The larger value is selected, the big output voltage fluctuation for causing this linearisation charge pump to generate is difficult to inhibit, this can greatly deteriorate phaselocked loop
The spuious characteristic of output signal has seriously affected its application in fully integrated loop filter.
A kind of double mode applied to phaselocked loop proposed by the present invention linearizes charge pump circuit and charge and discharge core circuit,
The high spuious problem of very good solution conventional linear charge pump bring, and support external loop filter and built-in ring simultaneously
Two kinds of typical cases of path filter.
Summary of the invention
Technical problem to be solved by the present invention lies in provide the double mode for being applied to phaselocked loop to linearize charge pump circuit
And charge and discharge core circuit, to realize the low-voltage fluctuation of charge pump output, and external loop filter and built-in is supported simultaneously
Two kinds of typical cases of loop filter.
First technical solution of the invention is a kind of charge and discharge core electricity for constituting double mode linearisation charge pump circuit
Road, including charging current source circuit, discharge current source circuit, offset current source circuit, sampling hold circuit, transmission gate, electric current
Interchange circuit, the first, second charge control tube, the first, second control of discharge pipe and switching tube；It is characterized by:
The complementary signal one of the grid difference reception pattern selection circuit output of first, second charge control tube；The first,
The complementary signal three of the grid difference reception pattern selection circuit output of two control of discharge pipes；First, second charge control tube
Source electrode connects charging current source circuit simultaneously；The source electrode of first, second control of discharge pipe connects the of electric current interchange circuit simultaneously
One input terminal；The drain electrode of first, second control of discharge pipe is separately connected the drain electrode of the first, second charge control tube；And second
The drain electrode of the input terminal and switching tube for draining while connecting transmission gate of charge control tube and sampling hold circuit；Switching tube
Grid connection signal input terminal, the control signal of reception pattern selection circuit output.
The second input terminal while the source electrode of connection switch pipe and the output end of transmission gate of electric current interchange circuit.
First output end of electric current interchange circuit is connect with discharge current source circuit；The second output terminal of electric current interchange circuit
It is connect with offset current source circuit.
The preferred embodiment of the charge and discharge core circuit according to the present invention for constituting double mode linearisation charge pump circuit,
The sampling hold circuit includes the first, second control pipe, the first, second capacitor and switch；The grid of first, second control pipe
The complementary signal two of reception pattern selection circuit output respectively；The drain electrode of first, second control pipe connects the second charging control simultaneously
The drain electrode of tubulation, and be grounded by first switch and first capacitor；The source electrode of first, second control pipe connects charge and discharge telecommunications simultaneously
Number output end, and pass through second switch and the second capacity earth.
The preferred embodiment of the charge and discharge core circuit according to the present invention for constituting double mode linearisation charge pump circuit,
The electric current interchange circuit includes the first, second, third, fourth transmission gate；The input terminal of first, second transmission gate is connected, and is
The first input end of electric current interchange circuit；Third, the 4th transmission gate input terminal are connected, and are the second input of electric current interchange circuit
End；The first, the output end of third transmission gate is connected, and is the first output end of electric current interchange circuit；The second, the 4th transmission gate is defeated
Outlet is connected, and is the second output terminal of electric current interchange circuit.
The preferred embodiment of the charge and discharge core circuit according to the present invention for constituting double mode linearisation charge pump circuit,
Amplifier is provided between the drain electrode of the one, second charge control tube.
Second technical solution of the invention is a kind of double mode linearisation charge pump circuit for phaselocked loop, including
Mode selection circuit and charge and discharge core circuit, it is characterised in that:
The mode selection circuit is used to keep charge pump to provide control logic, mould to conventional linear charge pump or sampling
When the mode selection terminal of formula selection circuit is logic high, the control logic of conventional linear charge pump is generated；Model selection
When circuit-mode selects end as logic low, the control logic that sampling keeps charge pump is generated.
The charge and discharge core circuit is used to provide charging current and discharge current to loop filter, works as phase lock loop locks
When, charging charge and discharge charge reach balance；Be configured by the scheme control end to charge and discharge core circuit, it can be achieved that
It linearizes charge pump or sampling keeps the switching of two kinds of operating modes of charge pump.
The charge and discharge core circuit includes charging current source circuit, discharge current source circuit, offset current source circuit, adopts
Sample holding circuit, transmission gate, electric current interchange circuit, the first, second charge control tube, the first, second control of discharge pipe and switch
Pipe.
The complementary signal one of the grid difference reception pattern selection circuit output of first, second charge control tube；The first,
The complementary signal three of the grid difference reception pattern selection circuit output of two control of discharge pipes；First, second charge control tube
Source electrode connects charging current source circuit simultaneously；The source electrode of first, second control of discharge pipe connects the of electric current interchange circuit simultaneously
One input terminal；The drain electrode of first, second control of discharge pipe is separately connected the drain electrode of the first, second charge control tube；And second
The drain electrode of the input terminal and switching tube for draining while connecting transmission gate of charge control tube and sampling hold circuit；Switching tube
Grid connection signal input terminal, the control signal of reception pattern selection circuit output.
The second input terminal while the source electrode of connection switch pipe and the output end of transmission gate of electric current interchange circuit.
First output end of electric current interchange circuit is connect with discharge current source circuit；The second output terminal of electric current interchange circuit
It is connect with offset current source circuit.
The preferred embodiment of double mode linearisation charge pump circuit according to the present invention for phaselocked loop, first, the
The complementary signal one of the grid difference reception pattern selection circuit output of two charge control tubes；First, second control of discharge pipe
Grid distinguishes the complementary signal three of reception pattern selection circuit output；The source electrode of first, second charge control tube connects simultaneously to be filled
Electric current source circuit；The source electrode of first, second control of discharge pipe connects the first input end of electric current interchange circuit simultaneously；The first,
The drain electrode of second control of discharge pipe is separately connected the drain electrode of the first, second charge control tube；And the leakage of the second charge control tube
Pole connects drain electrode and the sampling hold circuit of the input terminal and switching tube of transmission gate simultaneously；The grid reception pattern of switching tube is selected
Select the switch control signal of circuit output.
The second input terminal while the source electrode of connection switch pipe and the output end of transmission gate of electric current interchange circuit.
The preferred embodiment of double mode linearisation charge pump circuit according to the present invention for phaselocked loop, the sampling
Holding circuit includes the first, second control pipe, the first, second capacitor and switch；The grid of first, second control pipe receives respectively
The complementary signal two of mode selection circuit output；The drain electrode of first, second control pipe while the leakage for connecting the second charge control tube
Pole, and be grounded by first switch and first capacitor；The source electrode of first, second control pipe connects the output of charge and discharge electric signal simultaneously
End, and pass through second switch and the second capacity earth.
The preferred embodiment of double mode linearisation charge pump circuit according to the present invention for phaselocked loop, the electric current
Interchange circuit includes the first, second, third, fourth transmission gate；The input terminal of first, second transmission gate is connected, and exchanges for electric current
The first input end of circuit；Third, the input terminal of the 4th transmission gate are connected, are the second input terminal of electric current interchange circuit；The first,
The output end of third transmission gate is connected, and is the first output end of electric current interchange circuit；The second, the output end phase of the 4th transmission gate
It even, is the second output terminal of electric current interchange circuit.
The preferred embodiment of double mode linearisation charge pump circuit according to the present invention for phaselocked loop, the mode
D type flip flop, logic processing circuit, mutual supplementary signal generation circuit and output signal generating circuit are provided in selection circuit；
D type flip flop receives the charging control signal and discharge control signal of phase frequency detector output respectively, carries out digital fortune
Output signal generating circuit is output to after calculation；
Logic processing circuit receives mode control signal, reference clock signal, the frequency discrimination mirror of external register output respectively
The charging control signal and discharge control signal of phase device output output a control signal to complementary letter after carrying out logical process respectively
Number generation circuit and output signal generating circuit；
Mutual supplementary signal generation circuit is generated complementary signal one, two, three and is output to charge and discharge by the control of logic processing circuit
Core circuit；
Output signal generating circuit receives the control of discharge letter of the signal of d type flip flop output, phase frequency detector output respectively
Number and logic processing circuit output control signal, generate control signal be output to charge and discharge core circuit；
When mode control signal is logical one level, complementary signal one is believed by the charge control that phase frequency detector exports
It number is controlled, complementary signal two is controlled by the discharge control signal that phase frequency detector exports, and complementary signal three is by logic
Level "0" is controlled；
When the mode control signal that mode selection terminal receives is logical zero level, complementary signal one is by phase frequency detector
The charging control signal of output is controlled；Complementary signal two and complementary signal three are controlled by reference clock signal.
The beneficial effect of double mode linearisation charge pump circuit and charge and discharge core circuit of the present invention is: the present invention
Mode selection circuit, charge and discharge core circuit can switch between both of which, and phase-locked loop operation can be supported in built-in loop filtering
Device and two kinds of external loop filter applications, application mode are flexible；When charge pump circuit of the present invention is applied to phase-locked loop systems, if
Work keeps linearization pattern in sampling, compares conventional linear charge pump circuit, can greatly optimize pll output signal
Phase demodulation leakage is spuious；The present invention has the characteristics that noise is low, spuious low, can be widely applied to the radio-frequency locks such as fully integrated loop filter
In phase loop system, double mode linearisation charge pump circuit of the present invention is had great advantages.
Detailed description of the invention
Fig. 1 is typical decimal frequency divider phaselocked loop block diagram.
Fig. 2 is that the double mode of the present invention for phaselocked loop linearizes charge pump circuit schematic diagram.
Fig. 3 is mode selection circuit schematic diagram.
Fig. 4 is charge and discharge core circuit schematic diagram.
Fig. 5 is mutual supplementary signal generation circuit schematic diagram.
Fig. 6 is charge pump modes switching output voltage wave figure.
Fig. 7 a is the voltage wave cardon that conventional linear charge pump is generated in VCO control terminal.
Fig. 7 b is the voltage wave cardon that sampling keeps linearisation charge pump to generate in VCO control terminal.
Specific embodiment
Embodiment 1: referring to Fig. 1 to Fig. 5, a kind of charge and discharge core circuit constituting double mode linearisation charge pump circuit,
Including charging current source circuit 11, discharge current source circuit 12, offset current source circuit 13, sampling hold circuit 14, transmission gate
15, electric current interchange circuit I_swap, first, second charge control tube MP1, MP2, first, second control of discharge pipe MN1, MN2 and
Switching tube MN3.
The charge and discharge core circuit be provided with complementary signal input terminal cp_up2, cp_upn2, cp_ref2, cp_refn2,
Cp_dnn2, cp_dn2, signal input part cp_don2, scheme control end cp_mod, charge and discharge electrical signal cp_out and control
End processed.
The grid of first, second charge control tube MP1, MP2 is separately connected the second, first complementary signal input terminal cp_
Upn2, cp_up2, the complementary signal one that reception pattern selection circuit 1 exports；The grid of first, second control of discharge pipe MN1, MN2
Pole is separately connected the six, the 5th complementary signal input terminal cp_dnn2, cp_dn2, the complementary letter that reception pattern selection circuit 1 exports
Numbers three；The source electrode of first, second charge control tube MP1, MP2 connects charging current source circuit 11 simultaneously；First, second electric discharge control
The source electrode of tubulation MN1, MN2 connect the first input end Icm of electric current interchange circuit I_swap simultaneously；First, second control of discharge
The drain electrode of pipe MN1, MN2 are separately connected the drain electrode of the first, second charge control tube MP1, MP2；And the second charge control tube MP2
Drain electrode and meanwhile connect transmission gate 15 input terminal and switching tube MN3 drain electrode and sampling hold circuit 14；Switching tube MN3's
Grid connection signal input terminal cp_don2, the switch control signal that reception pattern selection circuit 1 exports.
Sampling hold circuit 14 connects for realizing the charging and discharging of charge pump, while realizing within a reference cycle
Two processes of sampling and holding；Charging current source circuit 11 is for providing charging current source and charge control, when MP1, MP2 grid
When voltage is high level, do not charge；It charges when MP1, MP2 grid voltage are low level；Under conventional linear mode,
By controlling mod_n and mod_p, realize that transmission gate 15 is connected；Sampling keep linearization pattern under, by control mod_n and
15 port of mod_p transmission gate disconnects.
The second input terminal Idn of electric current interchange circuit the I_swap source electrode of connection switch pipe MN3 and transmission gate 15 simultaneously
Output end.
The first output end Inorm of electric current interchange circuit I_swap is connect with discharge current source circuit 12；Electric current exchanges electricity
The second output terminal Ioffset of road I_swap is connect with offset current source circuit 13.
Electric current interchange circuit I_swap is for providing discharge current source and control of discharge, when MN1, MN2 grid voltage are height
It discharges when level；It does not discharge when MP1, MP2 grid voltage are low level.
Electric current interchange circuit I_swap is controlled by port p_ctrl and n_ctrl, is turned off or is connected to internal switch,
Realize that the port Inorm is connected to the port Icm or the port Idn；Or realize that the port Ioffset and the port Icm or the port Idn connect
It is logical.
Switching tube MN3 only in the case where sampling keeps linearization pattern, can just be connected, for realizing lock in phaselocked loop phase locking process
Charge and discharge charge pump during phase is stablized, and after phase lock loop locks, MN3 pipe is disconnected.
When the mode control signal that cp_mod is received when scheme control end is logical one level, transmission gate 15 is in closure
The electric current of state, the second output terminal output of electric current interchange circuit I_swap is equal with the electric current of the second input terminal, and electric current exchanges
The electric current of the first output end of circuit I _ swap output is equal with the electric current of first input end；When scheme control end, cp_mod is received
Mode control signal be logical zero level when, transmission gate 15 is in an off state, and the second of electric current interchange circuit I_swap is defeated
The electric current of outlet output is equal with the electric current of first input end, the electric current of the first output end output of electric current interchange circuit I_swap
It is equal with the electric current of the second input terminal.
The sampling hold circuit 14 includes first, second control pipe MN4, MP4, first, second capacitor CL, CR and opens
It closes；The grid of first, second control pipe MN4, MP4 is separately connected third, the 4th complementary signal input terminal cp_ref2, cp_
Refn2, the complementary signal two that reception pattern selection circuit 1 exports；The drain electrode of first, second control pipe MN4, MP4 connects simultaneously
The drain electrode of second charge control tube MP2, and be grounded by first switch K1 and first capacitor CL；First, second control pipe MN4,
The source electrode of MP4 connects charge and discharge electrical signal cp_out simultaneously, and is grounded by second switch K2 and the second capacitor CR.The
One, second switch is controlled by mode control signal；In the case where sampling keeps linearization pattern, mod_n control signal is high, and two
It is a to close the switch；Under conventional linear mode, it is low, two switches disconnections that mod_n, which controls signal,.
The electric current interchange circuit I_swap includes the first, second, third, fourth transmission gate；First, second transmission gate
Input terminal is connected, and is the first input end Icm of electric current interchange circuit I_swap；Third, the 4th transmission gate input terminal are connected, for electricity
Flow the second input terminal Idn of interchange circuit I_swap；The first, the output end of third transmission gate is connected, and is electric current interchange circuit I_
The first output end Inorm of swap；The second, the output end of the 4th transmission gate is connected, and is the second of electric current interchange circuit I_swap
Output end Ioffset.Control terminal p_ctrl receives mod_n and controls signal, and control terminal n_ctrl receives mod_p and controls signal；
Mod_n is the reverse signal of mode control signal；Mod_p is the reverse signal of mod_n.
Embodiment 2, a kind of double mode for phaselocked loop linearize charge pump circuit, including mode selection circuit 1 and fill
Discharge core circuit 2, in which:
The mode selection circuit 1 is used to keep charge pump to provide control logic to conventional linear charge pump or sampling,
When the mode selection terminal Sel of mode selection circuit is logic high, the control logic of conventional linear charge pump is generated；Mode
When selection circuit mode selection terminal Sel is logic low, the control logic that sampling keeps charge pump is generated.
The charge and discharge core circuit 2 is controlled by external register and mode selection circuit 1, for mentioning to loop filter
For charging current and discharge current, when phase lock loop locks, charging charge and discharge charge reach balance；By to charge and discharge core
The scheme control end on electrocardio road is configured, it can be achieved that linearizing charge pump or sampling cutting for holding two kinds of operating modes of charge pump
It changes.
The mode selection circuit 1 includes mode selection terminal Sel, charge control end UP, discharge control terminal DN, reference signal
Input terminal Fr, complementary signal output end cp_up, cp_upn, cp_ref, cp_refn, cp_dnn, cp_dn and signal output end
cp_don；Charge control end UP and discharge control terminal DN receives charging control signal and the electric discharge of the output of phase frequency detector 1 respectively
Signal is controlled, reference signal input terminal Fr receives reference clock signal.
The charge and discharge core circuit includes charging current source circuit 11, discharge current source circuit 12, offset current source electricity
Road 13, sampling hold circuit 14, transmission gate 15, electric current interchange circuit I_swap, first, second charge control tube MP1, MP2,
One, second control of discharge pipe MN1, MN2 and switching tube MN3.
The charge and discharge core circuit 2 be provided with complementary signal input terminal cp_up2, cp_upn2, cp_ref2, cp_refn2,
Cp_dnn2, cp_dn2, signal input part cp_don2, scheme control end cp_mod, charge and discharge electrical signal cp_out and control
End processed.
The grid of first, second charge control tube MP1, MP2 is separately connected the second, first complementary signal input terminal cp_
Upn2, cp_up2, the complementary signal one that reception pattern selection circuit 1 exports；The grid of first, second control of discharge pipe MN1, MN2
Pole is separately connected the six, the 5th complementary signal input terminal cp_dnn2, cp_dn2, the complementary letter that reception pattern selection circuit 1 exports
Numbers three；The source electrode of first, second charge control tube MP1, MP2 connects charging current source circuit 11 simultaneously；First, second electric discharge control
The source electrode of tubulation MN1, MN2 connect the first input end Icm of electric current interchange circuit I_swap simultaneously；First, second control of discharge
The drain electrode of pipe MN1, MN2 are separately connected the drain electrode of the first, second charge control tube MP1, MP2；And the second charge control tube MP2
Drain electrode and meanwhile connect transmission gate 15 input terminal and switching tube MN3 drain electrode and sampling hold circuit 14；Switching tube MN3's
Grid connection signal input terminal cp_don2, the switch control signal that reception pattern selection circuit 1 exports.
The second input terminal Idn of electric current interchange circuit the I_swap source electrode of connection switch pipe MN3 and transmission gate 15 simultaneously
Output end.
The first output end Inorm of electric current interchange circuit I_swap is connect with discharge current source circuit 12；Electric current exchanges electricity
The second output terminal Ioffset of road I_swap is connect with offset current source circuit 13.
When the mode control signal that cp_mod is received when scheme control end is logical one level, transmission gate 15 is in closure
The electric current of state, the second output terminal output of electric current interchange circuit I_swap is equal with the electric current of the second input terminal, and electric current exchanges
The electric current of the first output end of circuit I _ swap output is equal with the electric current of first input end；When scheme control end, cp_mod is received
Mode control signal be logical zero level when, transmission gate 15 is in an off state, and the second of electric current interchange circuit I_swap is defeated
The electric current of outlet output is equal with the electric current of first input end, the electric current of the first output end output of electric current interchange circuit I_swap
It is equal with the electric current of the second input terminal.
The sampling hold circuit 14 includes first, second control pipe MN4, MP4, first, second capacitor CL, CR and opens
It closes；The grid of first, second control pipe MN4, MP4 is separately connected third, the 4th complementary signal input terminal cp_ref2, cp_
Refn2, the complementary signal two that reception pattern selection circuit 1 exports；The drain electrode of first, second control pipe MN4, MP4 connects simultaneously
The drain electrode of second charge control tube MP2, and be grounded by first switch K1 and first capacitor CL；First, second control pipe MN4,
The source electrode of MP4 connects charge and discharge electrical signal cp_out simultaneously, and is grounded by second switch K2 and the second capacitor CR.The
One, second switch is controlled by mode control signal；In the case where sampling keeps linearization pattern, mod_n control signal is high, and two
It is a to close the switch；Under conventional linear mode, it is low, two switches disconnections that mod_n, which controls signal,.CL and CR is equivalent capacitance.
The electric current interchange circuit I_swap includes the first, second, third, fourth transmission gate；First, second transmission gate
Input terminal is connected, and is the first input end Icm of electric current interchange circuit I_swap；Third, the 4th transmission gate input terminal are connected, for electricity
Flow the second input terminal Idn of interchange circuit I_swap；The first, the output end of third transmission gate is connected, and is electric current interchange circuit I_
The first output end Inorm of swap；The second, the output end of the 4th transmission gate is connected, and is the second of electric current interchange circuit I_swap
Output end Ioffset.Control terminal p_ctrl receives mod_n and controls signal, and control terminal n_ctrl receives mod_p and controls signal；
Mod_n is the reverse signal of mode control signal；Mod_p is the reverse signal of mod_n.
The mode selection circuit 1 includes mode selection terminal Sel, charge control end UP, discharge control terminal DN, reference signal
Input terminal Fr, complementary signal output end cp_up, cp_upn, cp_ref, cp_refn, cp_dnn, cp_dn and signal output end
cp_don；Charge control end UP and discharge control terminal DN receives charging control signal and the electric discharge of the output of phase frequency detector 1 respectively
Signal is controlled, reference signal input terminal Fr receives reference clock signal.
The charge and discharge core circuit is provided with complementary signal input terminal cp_up2, cp_upn2, cp_ref2, cp_
Refn2, cp_dnn2, cp_dn2, signal input part cp_don2, scheme control end cp_mod and charge and discharge electrical signal cp_
out。
First complementary signal output end cp_up and the second complementary signal output end cp_upn output complementary signal one arrives charge and discharge
First complementary signal input terminal cp_up2 of electric core circuit 2 and the second complementary signal input terminal cp_upn2, the 5th complementary signal
Output end cp_dnn and the 6th complementary signal output end cp_dn output complementary signal three to charge and discharge core circuit 2 the 5th mutually
Complement signal input terminal cp_dnn2 and the 6th complementary signal input terminal cp_dn2, third complementary signal output end cp_ref and the 4th
Complementary signal output end cp_refn exports the third complementary signal input terminal cp_ that complementary signal two arrives charge and discharge core circuit 2
Ref2 and the 4th complementary signal input terminal cp_refn2.
D type flip flop, logic processing circuit 5, mutual supplementary signal generation circuit 6 and defeated are provided in the mode selection circuit 1
Signal generating circuit 4 out；
D type flip flop receives the charging control signal and discharge control signal of the output of phase frequency detector 3 respectively, carries out digital fortune
Output signal generating circuit 4 is output to after calculation；
Logic processing circuit 5 receives mode control signal, reference clock signal, the frequency discrimination mirror of external register output respectively
The charging control signal and discharge control signal that phase device 3 exports output a control signal to complementary letter after carrying out logical process respectively
Number generation circuit 6 and output signal generating circuit 4；
Mutual supplementary signal generation circuit 6 is generated complementary signal one, two, three and is output to charge and discharge by the control of logic processing circuit 5
Electric core circuit 2；
The control of discharge that output signal generating circuit 4 receives the signal of d type flip flop output respectively, phase frequency detector 3 exports
The control signal that signal and logic processing circuit 5 export generates control signal and is output to charge and discharge core circuit 2；
When mode control signal is logical one level, complementary signal one is believed by the charge control that phase frequency detector 3 exports
It number is controlled, complementary signal two is controlled by the discharge control signal that phase frequency detector 3 exports, and complementary signal three is by logic
Level "0" is controlled；
When the mode control signal that mode selection terminal Sel is received is logical zero level, complementary signal one is by frequency and phase discrimination
The charging control signal that device 3 exports is controlled；Complementary signal two and complementary signal three are controlled by reference clock signal.
Referring to Fig. 3 and Fig. 5, be provided in the mode selection circuit d type flip flop, the first reverser INV0 and first, second,
Third alternative selector MUX1, MUX2, MUX3, three ends and door AND3, the first delay cell 41, the first digit buffer BUF1
And first, second, third mutual supplementary signal generation circuit 61,62,63；First, second, third mutual supplementary signal generation circuit is by anti-
It is constituted to device INV, delay cell 8 and digit buffer.
The reference signal input terminal Fr of mode selection circuit, which is received, refers to output signal CLKREF, charge control end UP and mirror
Frequency phase detector output UP3 connects；Discharge control terminal DN connects with phase frequency detector output end DN3；Mode selection terminal Sel with fill
Electric discharge core circuit scheme control end cp_mod connection；The of first complementary signal output end cp_up and charge and discharge core circuit
One complementary signal input terminal cp_up2 connects；The second of second complementary signal output end cp_upn and charge and discharge core circuit is complementary
Signal input part cp_upn2 connects；The 6th complementary signal of 6th complementary signal output end cp_dn and charge and discharge core circuit are defeated
Enter cp_dn2 is held to connect；The 5th complementary signal input terminal of 5th complementary signal output end cp_dnn and charge and discharge core circuit
Cp_dnn2 connects；The third complementary signal input terminal cp_ of third complementary signal output end cp_ref and charge and discharge core circuit
Ref2 connects；The 4th complementary signal input terminal cp_ of 4th complementary signal output end cp_refn and charge and discharge core circuit
The port refn2 connects；Signal output end cp_don connects with the signal input part cp_don2 of charge and discharge core circuit.
The control terminal cp_ui<1:0>of charge and discharge core circuit 2 is controlled by register, the entitled CP_UI of control line<1:0>；
The control terminal cp_di<1:0>of charge and discharge core circuit is controlled by register, the entitled CP_DI of control line<1:0>；Charge and discharge core
The control terminal cp_offset<1:0>on electrocardio road is controlled by register, the entitled CP_offset of control line<1:0>；Charge and discharge core
The cp_mod on electrocardio road connects with the end Sel of mode selection circuit, is controlled by register；The charge and discharge telecommunications of charge and discharge core circuit
Number output end cp_out is connected by connecting line CP_OUT with loop filter.
Mode selection terminal Sel by external register control, when the mode control signal that mode selection terminal Sel is received be patrol
When collecting level"1", charge pump of the present invention is in conventional linear mode；It is mandatory by locking phase by the way that offset current source is arranged
The region of charge/discharge operation moves to linear zone charge-discharge region after ring locking, reduces far-end noise under decimal frequency divider mode and rolls over
The noisiness being laminated in band optimizes in-band phase noise；Concrete signal output figure is shown in Fig. 6.
When the mode control signal that mode selection terminal Sel is received is logical zero level, charge pump of the present invention is being adopted
Sample keeps mode.By by the control of time of discharge process about half reference cycle, it is mandatory by charge and discharge after phase lock loop locks
The region of electricity work moves to linear zone charge-discharge region, reduces far-end noise under decimal frequency divider mode and folds into making an uproar in band
Volume optimizes in-band phase noise；Two phase durations of sampling and holding respectively may be about half of reference clock cycle.If preceding
The charging current and discharge current of half period charge pump are opened, then MN4, MP4 pipe are in an off state in sampling hold circuit,
The large impact voltage that charge and discharge moment generates will not be output to loop filter, be stored in sampling hold circuit in the form of a charge
Capacitor CL on, charge according to charge conservation, then is assigned to the capacitor CL and CR of sampling hold circuit by second half of the cycle again
On, the voltage fluctuation that charge pump is output on loop filter route can be reduced in this way, to reduce spuious；Concrete signal output
Figure is shown in Fig. 6.
The electric current of charging current source circuit, discharge current source circuit and offset current source circuit can pass through the disconnection of switch
It is selected with closure, all has programmable configuration feature.
Transmission gate 15 is in an off state in the case where sampling keeps linearization pattern；Under conventional linear mode, in closing
Conjunction state.
The present invention is combined using mode selection circuit 1 and charge and discharge core circuit 2, realizes conventional linear charge pump
The switching of linearisation two kinds of operating modes of charge pump is kept with sampling.
Charge pump circuit functions of the present invention are preceding if phaselocked loop is in the lock state when sampling is kept under linearization pattern
In half of reference clock cycle, charging and discharging process occurs respectively for MP2, MN2, and charging charge and power generation charge can be stored in
Capacitor CL anode；Afterwards in half of reference cycle clock, MP2 and MN2 do not fill power generation process, and capacitor CL anode charge can balance
It is distributed in CL and CR anode.Using this way, the voltge surge of the end charge and discharge moment CPOUT generation can be significantly reduced, greatly
The output phase demodulation leakage for optimizing entire phaselocked loop is spuious, and spuious effect of optimization can pass through the voltage-controlled electricity of VCO after comparison PLL closed loop locking
The voltage fluctuation of pressure side obtains, and the invention patent charge pump compares conventional linear charge in the case where sampling keeps linearization pattern
Pump, spuious effect of optimization comparison is as shown in Fig. 7 a, Fig. 7 b.
Result of implementation above shows: a kind of double mode linearisation charge pump circuit applied to phaselocked loop of the invention can
Two kinds of application models of complete built-in loop filter and complete external loop filter are supported, when work keeps linearization pattern in sampling
When, it is spuious to can effectively reduce phaselocked loop output phase demodulation leakage.The technology of the present invention can be applied to: noise is low, it is spuious it is low, be suitable for it is complete
The RF Phase-Lock Loop system of integrated loop filter.
Claims (8)
1. a kind of charge and discharge core circuit for constituting double mode linearisation charge pump circuit, including charging current source circuit (11),
Discharge current source circuit (12), offset current source circuit (13), sampling hold circuit (14), transmission gate (15), electric current exchange electricity
Road (I_swap), the first, second charge control tube (MP1, MP2), the first, second control of discharge pipe (MN1, MN2) and switching tube
(MN3)；It is characterized by:
The complementary signal of grid difference reception pattern selection circuit (1) output of first, second charge control tube (MP1, MP2)
One；The complementary signal three of grid difference reception pattern selection circuit (1) output of first, second control of discharge pipe (MN1, MN2)；
The source electrode of first, second charge control tube (MP1, MP2) connects charging current source circuit (11) simultaneously；First, second electric discharge control
The source electrode of tubulation (MN1, MN2) connects the first input end (Icm) of electric current interchange circuit (I_swap) simultaneously；First, second puts
The drain electrode of automatically controlled tubulation (MN1, MN2) is separately connected the drain electrode of the first, second charge control tube (MP1, MP2)；And second fills
The drain electrode of automatically controlled tubulation (MP2) connects the drain electrode of the input terminal and switching tube (MN3) of transmission gate (15) simultaneously and sampling is kept
Circuit (14)；The control signal of grid reception pattern selection circuit (1) output of switching tube (MN3)；
The second input terminal (Idn) of electric current interchange circuit (I_swap) while the source electrode and transmission gate of connection switch pipe (MN3)
(15) output end；
The first output end (Inorm) of electric current interchange circuit (I_swap) is connect with discharge current source circuit (12)；Electric current exchanges
The second output terminal (Ioffset) of circuit (I_swap) is connect with offset current source circuit (13).
2. the charge and discharge core circuit according to claim 1 for constituting double mode linearisation charge pump circuit, feature exist
In: the sampling hold circuit (14) includes the first, second control pipe (MN4, MP4), the first, second capacitor (CL, CR) and opens
It closes；The complementary signal two of grid difference reception pattern selection circuit (1) output of first, second control pipe (MN4, MP4)；The
One, the drain electrode of the second control pipe (MN4, MP4) connects the drain electrode of the second charge control tube (MP2) simultaneously, and passes through first switch
(K1) it is grounded with first capacitor (CL)；The source electrode of first, second control pipe (MN4, MP4) connects charge and discharge electrical signal simultaneously
(cp_out), it and by second switch (K2) and the second capacitor (CR) is grounded.
3. the charge and discharge core circuit according to claim 1 for constituting double mode linearisation charge pump circuit, feature exist
In: the electric current interchange circuit (I_swap) includes the first, second, third, fourth transmission gate；First, second transmission gate it is defeated
Enter end to be connected, is the first input end (Icm) of electric current interchange circuit (I_swap)；Third, the 4th transmission gate input terminal are connected, and are
The second input terminal (Idn) of electric current interchange circuit (I_swap)；The first, the output end of third transmission gate is connected, and exchanges for electric current
The first output end (Inorm) of circuit (I_swap)；The second, the output end of the 4th transmission gate is connected, and is electric current interchange circuit (I_
Swap second output terminal (Ioffset)).
4. the charge and discharge core circuit according to claim 1 or 2 or 3 for constituting double mode linearisation charge pump circuit,
It is characterized in that: being provided with amplifier (AMP) between the drain electrode of the one, second charge control tube (MP1, MP2).
5. a kind of double mode for phaselocked loop linearizes charge pump circuit, including mode selection circuit (1) and charge and discharge core
Circuit (2), it is characterised in that:
The mode selection circuit (1) is used to keep charge pump to provide control logic to conventional linear charge pump or sampling；
The charge and discharge core circuit (2) is controlled by external register and mode selection circuit (1), for mentioning to loop filter
For charging current and discharge current；
The charge and discharge core circuit includes charging current source circuit (11), discharge current source circuit (12), offset current source electricity
Road (13), sampling hold circuit (14), transmission gate (15), electric current interchange circuit (I_swap), the first, second charge control tube
(MP1, MP2), the first, second control of discharge pipe (MN1, MN2) and switching tube (MN3)；
The complementary signal of grid difference reception pattern selection circuit (1) output of first, second charge control tube (MP1, MP2)
One；The complementary signal three of grid difference reception pattern selection circuit (1) output of first, second control of discharge pipe (MN1, MN2)；
The source electrode of first, second charge control tube (MP1, MP2) connects charging current source circuit (11) simultaneously；First, second electric discharge control
The source electrode of tubulation (MN1, MN2) connects the first input end (Icm) of electric current interchange circuit (I_swap) simultaneously；First, second puts
The drain electrode of automatically controlled tubulation (MN1, MN2) is separately connected the drain electrode of the first, second charge control tube (MP1, MP2)；And second fills
The drain electrode of automatically controlled tubulation (MP2) connects the drain electrode of the input terminal and switching tube (MN3) of transmission gate (15) simultaneously and sampling is kept
Circuit (14)；The control signal of grid reception pattern selection circuit (1) output of switching tube (MN3)；
The second input terminal (Idn) of electric current interchange circuit (I_swap) while the source electrode and transmission gate of connection switch pipe (MN3)
(15) output end；
The first output end (Inorm) of electric current interchange circuit (I_swap) is connect with discharge current source circuit (12)；Electric current exchanges
The second output terminal (Ioffset) of circuit (I_swap) is connect with offset current source circuit (13).
6. the double mode according to claim 5 for phaselocked loop linearizes charge pump circuit, it is characterised in that:
The sampling hold circuit (14) includes the first, second control pipe (MN4, MP4), the first, second capacitor (CL, CR) and opens
It closes；The complementary signal two of grid difference reception pattern selection circuit (1) output of first, second control pipe (MN4, MP4)；The
One, the drain electrode of the second control pipe (MN4, MP4) connects the drain electrode of the second charge control tube (MP2) simultaneously, and passes through first switch
(K1) it is grounded with first capacitor (CL)；The source electrode of first, second control pipe (MN4, MP4) connects charge and discharge electrical signal simultaneously
(cp_out), it and by second switch (K2) and the second capacitor (CR) is grounded.
7. the double mode according to claim 5 for phaselocked loop linearizes charge pump circuit, it is characterised in that: the electricity
Flowing interchange circuit (I_swap) includes the first, second, third, fourth transmission gate；The input terminal of first, second transmission gate is connected,
For the first input end (Icm) of electric current interchange circuit (I_swap)；Third, the input terminal of the 4th transmission gate are connected, are that electric current is mutual
Change the second input terminal (Idn) of circuit (I_swap)；The first, the output end of third transmission gate is connected, and is electric current interchange circuit (I_
Swap the first output end (Inorm))；The second, the output end of the 4th transmission gate is connected, and is electric current interchange circuit (I_swap)
Second output terminal (Ioffset).
8. linearizing charge pump circuit for the double mode of phaselocked loop according to claim 5 or 6 or 7, it is characterised in that:
Be provided in the mode selection circuit (1) d type flip flop, logic processing circuit (5), mutual supplementary signal generation circuit (6) and
Output signal generating circuit (4)；
D type flip flop receives the charging control signal and discharge control signal of phase frequency detector (3) output respectively, carries out digital operation
After be output to output signal generating circuit (4)；
Logic processing circuit (5) receives the mode control signal of external register output, reference clock signal, frequency and phase discrimination respectively
The charging control signal and discharge control signal of device (3) output output a control signal to complementary letter after carrying out logical process respectively
Number generation circuit (6) and output signal generating circuit (4)；
Mutual supplementary signal generation circuit (6) is generated complementary signal one, two, three and is output to charge and discharge by the control of logic processing circuit (5)
Electric core circuit (2)；
Output signal generating circuit (4) receives the control of discharge of the signal of d type flip flop output, phase frequency detector (3) output respectively
The control signal of signal and logic processing circuit (5) output generates control signal and is output to charge and discharge core circuit (2)；
When mode control signal is logical one level, charging control signal that complementary signal one is exported by phase frequency detector (3)
It is controlled, complementary signal two is controlled by the discharge control signal that phase frequency detector (3) exports, and complementary signal three is by logic
Level "0" is controlled；
When the mode control signal that mode selection terminal (Sel) receives is logical zero level, complementary signal one is by phase frequency detector
(3) charging control signal exported is controlled；Complementary signal two and complementary signal three are controlled by reference clock signal.
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| CN201811010985.0A CN108964657B (en) | 2018-08-31 | 2018-08-31 | Dual-mode linear charge pump circuit for phase-locked loop and charge-discharge core circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112583403A (en) * | 2020-12-11 | 2021-03-30 | 重庆西南集成电路设计有限责任公司 | Circuit and method for indicating single chip microcomputer in wake-up stop state by using phase-locked loop locking |
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