CN107659307A - The charge pump circuit that a kind of current source for frequency synthesizer alternately exchanges - Google Patents
The charge pump circuit that a kind of current source for frequency synthesizer alternately exchanges Download PDFInfo
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- CN107659307A CN107659307A CN201711086536.XA CN201711086536A CN107659307A CN 107659307 A CN107659307 A CN 107659307A CN 201711086536 A CN201711086536 A CN 201711086536A CN 107659307 A CN107659307 A CN 107659307A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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- Engineering & Computer Science (AREA)
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- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses the charge pump circuit that a kind of current source for frequency synthesizer alternately exchanges, including two current sources, two electric currents are heavy, four switches and four data selectors.The current source, electric current are heavy to be connected with data selector, and data selector connects with switch；Data selector is respectively selector M1, selector M2, selector M3, selector M4, switch is respectively switch SW1, switch SW2, switch SW3, switch SW4, wherein selector M1 and selector M3 is by switching SW1, OUTP ends are used as in switch SW3 outputs, and selector M2 and selector M4 is by switching SW2, OUTN ends are used as in switch SW4 outputs；The present invention provides the charge pump circuit that a kind of current source for frequency synthesizer alternately exchanges, and has more preferable noise inhibiting ability, and can reduce the reference spur of introducing.
Description
Technical field
The present invention relates to radio frequency, field of analog integrated circuit, in particular, it is related to a kind of for frequency synthesizer
The charge pump circuit that current source alternately exchanges.
Background technology
The concept for locking phase was proposed in the 1930s earliest, and was obtained quickly in electronics and communication field
Extensive use.Although basic phaselocked loop (PLL) is almost kept intact from occur, using different fabrication techniques and
The realization for meeting the phaselocked loop of different application requirement is always a challenge to designer.
In the radio frequency transceiver of radio communication, phaselocked loop is as frequency synthesizer, there is provided local oscillation signal is used for modulatedemodulate
Adjust, while also provide system clock for digital module.Charge pump phase lock loop is a kind of current more common structure, and phaselocked loop is working
When, the output of voltage controlled oscillator (VCO) differentiates that input reference clock is defeated with dividing after frequency divider by phase frequency detector (PFD)
Go out the phase difference of clock, the output voltage pulse directly proportional to phase difference, charging and discharging currents output is converted to by charge pump (CP)
To loop filter, switch to VCO control voltage input, so as to adjust its output frequency and phase, finally realize that frequency divider is defeated
The signal gone out is equal with reference clock phase alignment, frequency, and now phase-locked loop systems lock.
The performance measure index of phaselocked loop is usually locking time, phase noise and spuious size, in the locked state,
Charge pump is in same and noise current output, because loop has low-pass characteristic to equivalent input phase noise, this portion is had when opening area
Noise current is divided to be presented as the in-band phase noise of VCO outputs；And CP is understood to join due to the Incomplete matching of charging and discharging currents
Examine extra same of rate-adaptive pacemaker and open area's mismatch current, introduce in the spuious of reference frequency (and its harmonic wave) place.
The advantage of fully differential structure is in the common-mode noise that can be introduced in suppression circuit, but due to difference output in CP
The noise source at end is orthogonal, is not belonging to common-mode noise, and output current noise can not be inhibited compared with single-ended structure；Separately
Outside, because laying out pattern wiring can not match completely, and extra mismatch can be introduced in production process, the electricity of difference output
Stream may be introduced fixed direct current mismatch by these process deviations, increase reference spur.
The content of the invention
Instant invention overcomes the deficiencies in the prior art, there is provided the electricity that a kind of current source for frequency synthesizer alternately exchanges
Lotus pump circuit, there is more preferable noise inhibiting ability, and the reference spur of introducing can be reduced.
Technical scheme is as follows：
The charge pump circuit that a kind of current source for frequency synthesizer alternately exchanges, charge pump include the first current source,
Second current source, the first electric current are heavy, the second electric current is heavy, first switch, second switch, third switch, the 4th switch, the first data
Selector, the second data selector, the 3rd data selector and the 4th data selector；First current source, the second electric current
Source is connected with the input of the first data selector, and the first data selector output end is connected with first switch；Described
One electric current is heavy, the second electric current is heavy is connected with the 3rd data selector, and the 3rd data selector and the 3rd switch connect；It is described
First switch is connected with the 3rd switch, and in output end of both junctions as charge pump；First current source, the second electricity
Stream source is connected with the input of the second data selector, and the second data selector output end is connected with second switch；It is described
First electric current is heavy, the second electric current is heavy is connected with the 4th data selector, and the 4th data selector and the 4th switch connect；Institute
Second switch is stated to connect with the 4th switch, and in both junctions as charge pump outputs；First data selector,
Two data selectors, the 3rd data selector and the 4th data selector are all made up of the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, and described
One metal-oxide-semiconductor, the second metal-oxide-semiconductor G poles control signal inversion signal each other.
Further, first metal-oxide-semiconductor, the second metal-oxide-semiconductor are using PMOS composition selector structure, the first MOS
Two inputs of the S poles of pipe, the S poles of the second metal-oxide-semiconductor as data selector, the D poles of first metal-oxide-semiconductor, the second metal-oxide-semiconductor
The connection of D poles, and as the output end of data selector.
Further, first metal-oxide-semiconductor, the second metal-oxide-semiconductor use the selector structure of NMOS tube, first metal-oxide-semiconductor
D poles, the second metal-oxide-semiconductor D poles as data selector two inputs connect, the S poles of first metal-oxide-semiconductor, the 2nd MOS
The S poles connection of pipe, and connected as the output end of data selector.
Further, first data selector, the second data selector, the 3rd data selector and the choosing of the 4th data
The selection signal end for selecting device is connected with reference clock module.
The advantage of the invention is that：The present invention is under phase lock loop locks state, PFD not phase difference outputs, each with reference to frequency
Rate cycle charge pump has a Duan Tongkai areas, and charging and discharging currents are connected to output end simultaneously, and output noise electric current now is due to ring
The low-pass characteristic on road, it is presented as the in-band phase noise of phaselocked loop output.
The present invention is exchanged by the alternating of the output current to differential charge pump, is ensureing the constant situation of output current
Under, realize that the frequency spectrum of output noise is moved to high frequency, using the low-pass characteristic of cycle of phase-locked loop, to reduce charge pump to whole ring
The influence of mutually making an uproar on road.
Alternately interchange structure proposed by the present invention can also reduce what is introduced by laying out pattern mismatch or production technology reason
DC offset, so as to reduce by this part with open area's DC electric current (be different from current source, electric current it is heavy between mismatch current) introduce
Reference spur.
Brief description of the drawings
Fig. 1 is the circuit design drawing of the present invention；
Fig. 2 is the circuit design drawing of the data selector of the present invention；
Fig. 3 is that the data selector of the present invention selects the circuit design drawing of another metal-oxide-semiconductor；
Fig. 4 is a kind of situation schematic diagram when selection signal of the invention is connected as reference clock fractional frequency signal；
Fig. 5 is another situation schematic diagram when selection signal of the invention is connected as reference clock fractional frequency signal；
Fig. 6 is the schematic diagram caused by the input and output of phase frequency detector under loop-locking state of the present invention；
Fig. 7 is the charge pump P output end equivalent noise current figures of the present invention；
Fig. 8 is the charge pump N output end equivalent noise current figures of the present invention；
Fig. 9 is that the phaselocked loop that draws of conventional charge pump configuration is mutually made an uproar curve map；
Figure 10 is that the phaselocked loop that draws of the present invention is mutually made an uproar curve map；
Figure 11 is the schematic diagram of the output current in loop-locking of circuit structure of the present invention and traditional structure；
Figure 12 is the spuious effect of optimization comparison diagram of circuit structure of the present invention and traditional structure；
Figure 13 is the cycle of phase-locked loop structured flowchart of the present invention.
Embodiment
The present invention is further described with reference to the accompanying drawings and detailed description.
The charge pump circuit that a kind of current source for frequency synthesizer alternately exchanges, charge pump include the first current source,
Second current source, the first electric current are heavy, the second electric current is heavy, first switch, second switch, third switch, the 4th switch, the first data
Selector, the second data selector, the 3rd data selector and the 4th data selector；First current source, the second electric current
Source is connected with the input of the first data selector, and the first data selector output end is connected with first switch；Described
One electric current is heavy, the second electric current is heavy is connected with the 3rd data selector, and the 3rd data selector and the 3rd switch connect；It is described
First switch is connected with the 3rd switch, and in output end of both junctions as charge pump；First current source, the second electricity
Stream source is connected with the input of the second data selector, and the second data selector output end is connected with second switch；It is described
First electric current is heavy, the second electric current is heavy is connected with the 4th data selector, and the 4th data selector and the 4th switch connect；Institute
Second switch is stated to connect with the 4th switch, and in both junctions as charge pump outputs；First data selector,
Two data selectors, the 3rd data selector and the 4th data selector are all made up of the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, and described
One metal-oxide-semiconductor, the second metal-oxide-semiconductor G poles control signal inversion signal each other.Specifically as shown in figure 1, charge pump model is equivalent to wrap
Include heavy two current sources, two electric currents, four switches and four data selectors.The current source, electric current are heavy to be selected with data
Device connects, and data selector connects with switch.Data selector is respectively selector M1, selector M2, selector M3, selector
M4, switch respectively switch SW1, switch SW2, switch SW3, switch SW4, wherein selector M1 and selector M3 pass through switch
SW1, switch SW3 outputs are used as OUTP ends, and selector M2 and selector M4 is by switching SW2, OUTN is used as in switch SW4 outputs
End.Wherein current source Ip1Respectively as selector M1, the input signal of selector M2 " 1 " and " 0 ", current source Ip2Make respectively
For selector M1, selector M2 " 0 " and " 1 " input signal, i.e. selector M1 and selector M2 select current source I respectivelyp1With
Current source Ip2In output all the way, its select fractional frequency signal be Sel1.When Sel1 is high level, selector M1, selector M2
Selection one-input terminal leads to output, when Sel1 is low level, then selects zero-input terminal to lead to output.I is sunk for electric currentn1Respectively
Alternatively device M3, selector M4 " 1 " and " 0 " input signal, electric current sink In2Respectively as selector M3, selector M4
" 0 " and " 1 " input signal.That is selector M3 and selector M4 selects electric current to sink I respectivelyn1I is sunk with electric currentn2In output all the way,
It is Sel2 that it, which selects fractional frequency signal,.
Data selector MUX function is that two road signal behaviors of input are output into MUX output all the way.As excellent
Choosing, the first metal-oxide-semiconductor described in data selector M1, data selector M2, the second metal-oxide-semiconductor use the selector structure of PMOS,
Two inputs connection of first metal-oxide-semiconductor, the S poles of the second metal-oxide-semiconductor and data selector, first metal-oxide-semiconductor, second
The D poles of metal-oxide-semiconductor and the output end of data selector connect.Wherein the first metal-oxide-semiconductor, the G poles Sel of the second metal-oxide-semiconductor and Selb letter
Number each other inversion signal, in the selection fractional frequency signal in accessing such as Fig. 1, when only accessing a selection fractional frequency signal, Sel with
Selb is directly accessed a phase inverter, or two selection fractional frequency signals of access are connected with Sel, Selb respectively.
First metal-oxide-semiconductor described in data selector M3, data selector M4, the second metal-oxide-semiconductor use the selector of NMOS tube
Structure, two inputs connection of first metal-oxide-semiconductor, the D poles of the second metal-oxide-semiconductor and data selector, first metal-oxide-semiconductor,
The S poles of second metal-oxide-semiconductor and the output end of data selector connect.
The choosing of first data selector, the second data selector, the 3rd data selector and the 4th data selector
Signal end is selected to be connected with reference clock module.Selection signal Sel1 and Sel2 be reference clock (Ref) fractional frequency signal, its sequential
Relation can have multiple choices.Can be as shown in figure 4, Sel1 and Sel2 be same signal Sel, its rising edge snaps to Ref decline
Edge, frequency are the 1/2 of Ref.Also can as shown in figure 5, Sel1 and Sel2 rising edge alignment to Ref trailing edge, and mutually it
Between stagger 90 ° of phase (or other phase differences), frequency is the 1/4 of Ref.
In example, only needing the 1/2N that Sel1 and Sel2 rising edge alignment to Ref trailing edge and frequency are Ref, (N is whole
Number).
During Sel1 and Sel2 signal saltus steps, the output of selector can be caused to switch between " 0 " and " 1 ", it is final to realize electricity
Stream source and electric current sink is alternately connected to output end OUTP, OUTN with Sel1 and Sel2 frequency respectively.Due to data selector
Actual implementation is MOS switch, and it is in deep triode region or by area during ideal operation, is equivalent to a small resistor or one
Individual great resistance, but non-linear factor can be introduced in handoff procedure, if switching when there is electric current output, output current can be caused
Burr is produced, so being the trailing edge of Ref signals by the selection of Sel1 and Sel2 signals jumping moment, avoids output current generation
Burr.
In phase-locked loop locking, as shown in figure 13, in addition to PFD is phase frequency detector, and the PFD is connected with LPF.Figure
6 be the schematic diagram of input and the output of phase frequency detector under loop-locking state.The phase error that PFD differentiates be typically by
Random phase offset accumulation below precision of phase discrimination causes, and its phase difference is minimum, incomparable with the reference clock signal cycle, therefore
Phase demodulation output pulse alignment Ref signal rising edges now, and the duration is extremely short, subsequent increased same to avoid dead band
Open area's (dash area in figure) also will not undergo Ref trailing edge in this case extremely close to rising edge, Gu Tongkai areas.Will
Sel jumping moments snap to Ref trailing edge, then can avoid producing burr at the time of output current, will according to Fig. 5 modes
Sel1 and Sel2 stagger a phase bit, then current source, electric current can be avoided heavy while switched, more reduce switching instant
Influence to output.
The phaselocked loop that the charge pump can suppress to introduce always mutually is made an uproar, and obtains a kind of noise optimization.I.e. in the locked state,
Phase difference output, each reference frequency cycle charge pump do not have a Duan Tongkai areas to PFD, and charging and discharging currents are connected to output simultaneously
End, output noise electric current now are presented as the in-band phase noise that phaselocked loop exports, by electric current due to the low-pass characteristic of loop
Source Ip1I is sunk with electric currentn1The equivalent noise current to output end is designated as ino1, current source Ip2I is sunk with electric currentn2The equivalent output end of arriving
Noise current is designated as ino2.Difference both ends current source is alternately exchanged under Sel frequencies, seen at output end OUTP, OUTN both ends
Current noise be equivalent to ino1With ino2It is added after being multiplied respectively with two square-wave pulses anti-phase each other.As shown in Figure 7, Figure 8,
Equivalent noise current (the spectrum that the equivalent noise current (spectrum density) and charge pump n output ends that charge pump p output ends obtain obtain
Density) equation below：
Wherein inoutpThe equivalent noise current obtained for charge pump p output ends, inoutnObtained for charge pump n output ends
Equivalent noise current；H1And H (s)2(s) transmission function of the square-wave pulse passed through for both ends；
Wherein, T is the cycle of square wave, as Sel signal periods, and e is the natural logrithm truth of a matter, and s is Laplace transform
Complex frequency variable；
Then final difference output noise current (spectrum density) is the difference of OUTP and OUTN both ends noise current (spectrum density)：
Wherein idiffFor the equivalent noise current of difference output,Its frequency response is in
Existing high pass characteristic, can effectively suppress low-frequency noise.
With MATLAB phaselocked loop is made mutually to make an uproar curve, obtain curve using conventional charge pump configuration as shown in figure 9, and this
Invention proposes that the curve of mutually making an uproar that structure obtains is as shown in Figure 10, wherein, dotted line Total is that the total of phaselocked loop mutually makes an uproar, and dotted line CP is
What charge pump was contributed mutually makes an uproar, and contrasts two figures, it can be seen that the phase noise in band has obtained obvious suppression, for same lock
Xiang Huan, use the low-frequency phase obtained during traditional structure charge pump to make an uproar as -115.8dBc/Hz, propose that structure obtains using the present invention
Low-frequency phase make an uproar as -126.3dBc/Hz, contrast, which obtains structure proposed by the present invention, makes an uproar low-frequency phase and optimizes 8.5dB.
In addition, charge pump can introduce extra DC because laying out pattern mismatches and manufactured reason to difference output both ends
Offset (direct current mismatch), cause to have an extra DC electric current output in Tong Kaiqu, increase reference spur, and the present invention proposes
Alternating interchange structure can then reduce the reference spur that this part DC electric current introduces.The output current of traditional structure is as in Figure 11
Iout1, Iout1The width of positive dash area be each cycle output pulse width dead band length, Iout1Dash area height value is
Imis, because it exports a constant DC component, loop can compensate to this portion of electrical current, be presented as elongate strip in figure
Reverse shade electric current, its area are equal to positive dash area, offset DC component.Circuit proposed by the present invention is due to alternately mutual
Change, the I in the electric current such as Figure 11 of outputout2, Iout2The width of dash area is the dead band length of each cycle output pulse width,
Iout2Dash area height value is Imis, but the sense of current of adjacent periods is on the contrary, now output current is without DC component, loop
This portion of electrical current will not be compensated.
Fourier space is asked to above two output waveform, obtains that spectrum results are as shown in figure 12, prior art construction
Frequency spectrum is black heavy line, and the frequency spectrum of structure proposed by the present invention is dash-dotted gray line, can be proposed by the present invention as seen from the figure
The minimum spectrum line of structure (corresponding 1/2 reference frequency) is close with minimum spectrum line (corresponding reference frequency) size of traditional structure,
But the energy of higher hamonic wave will substantially be less than prior art construction, and for broadband application, spuious gross energy obtains on whole frequency spectrum
Good optimization is arrived.
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, without departing from the inventive concept of the premise, can also make some improvements and modifications, these improvements and modifications also should be regarded as
In the scope of the present invention.
Claims (4)
1. the charge pump circuit that a kind of current source for frequency synthesizer alternately exchanges, it is characterised in that charge pump includes the
One current source, the second current source, the first electric current are heavy, the second electric current is heavy, first switch, second switch, third switch, the 4th open
Pass, the first data selector, the second data selector, the 3rd data selector and the 4th data selector；First electric current
Source, the second current source are connected with the input of the first data selector, the first data selector output end and first switch
Connection；First electric current is heavy, the second electric current is heavy is connected with the 3rd data selector, and the 3rd data selector is opened with the 3rd
Connection connects；The first switch is connected with the 3rd switch, and in output end of both junctions as charge pump；First electricity
Stream source, the second current source are connected with the input of the second data selector, and the second data selector output end is opened with second
Connection connects；First electric current is heavy, the second electric current is heavy is connected with the 4th data selector, the 4th data selector and the 4th
Switch connection；The second switch is connected with the 4th switch, and in both junctions as charge pump outputs；First number
According to selector, the second data selector, the 3rd data selector and the 4th data selector all by the first metal-oxide-semiconductor, the second metal-oxide-semiconductor
Composition, first metal-oxide-semiconductor, the second metal-oxide-semiconductor G poles control signal inversion signal each other.
2. the charge pump circuit that a kind of current source for frequency synthesizer according to claim 1 alternately exchanges, it is special
Sign is, first metal-oxide-semiconductor, the second metal-oxide-semiconductor are using PMOS composition selector structure, the S poles of first metal-oxide-semiconductor, the
Two inputs of the S poles of two metal-oxide-semiconductors as data selector, the D poles of first metal-oxide-semiconductor, the D poles connection of the second metal-oxide-semiconductor,
And as the output end of data selector.
3. the charge pump circuit that a kind of current source for frequency synthesizer according to claim 1 alternately exchanges, it is special
Sign is that first metal-oxide-semiconductor, the second metal-oxide-semiconductor use the selector structure of NMOS tube, the D poles of first metal-oxide-semiconductor, second
The D poles of metal-oxide-semiconductor connect as two inputs of data selector, and the S poles of first metal-oxide-semiconductor, the S poles of the second metal-oxide-semiconductor connect
Connect, and connected as the output end of data selector.
4. the charge pump circuit that a kind of current source for frequency synthesizer according to claim 1 alternately exchanges, it is special
Sign is, the selection of first data selector, the second data selector, the 3rd data selector and the 4th data selector
Signal end is connected with reference clock module.
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| CN201711086536.XA CN107659307B (en) | 2017-11-07 | 2017-11-07 | Charge pump circuit for alternately exchanging current sources of frequency synthesizer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108964657A (en) * | 2018-08-31 | 2018-12-07 | 重庆西南集成电路设计有限责任公司 | Double mode for phaselocked loop linearizes charge pump circuit and charge and discharge core circuit |
| CN109995364A (en) * | 2019-03-06 | 2019-07-09 | 杭州城芯科技有限公司 | A kind of frequency synthesizer based on design circuit |
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| US20040239434A1 (en) * | 2001-10-05 | 2004-12-02 | Arnaud Casagrande | Phase-switched dual-mode counter circuit for a frequency synthesizer |
| US20060119438A1 (en) * | 2004-12-02 | 2006-06-08 | Via Technologies, Inc. | Low noise charge pump for PLL-based frequence synthesis |
| CN101944909A (en) * | 2009-07-10 | 2011-01-12 | 智迈微电子科技(上海)有限公司 | Phase frequency detector and charge pump circuit for phase locked loop |
| CN102710256A (en) * | 2012-07-03 | 2012-10-03 | 复旦大学 | Phase frequency detector capable of reducing loop nonlinearity |
| CN207460133U (en) * | 2017-11-07 | 2018-06-05 | 杭州城芯科技有限公司 | The charge pump circuit that a kind of current source for frequency synthesizer alternately exchanges |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108964657A (en) * | 2018-08-31 | 2018-12-07 | 重庆西南集成电路设计有限责任公司 | Double mode for phaselocked loop linearizes charge pump circuit and charge and discharge core circuit |
| CN109995364A (en) * | 2019-03-06 | 2019-07-09 | 杭州城芯科技有限公司 | A kind of frequency synthesizer based on design circuit |
| CN109995364B (en) * | 2019-03-06 | 2020-08-04 | 杭州城芯科技有限公司 | Frequency synthesizer based on digital temperature compensation circuit |
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