CN108962881A - Stack package structure - Google Patents
Stack package structure Download PDFInfo
- Publication number
- CN108962881A CN108962881A CN201810717620.5A CN201810717620A CN108962881A CN 108962881 A CN108962881 A CN 108962881A CN 201810717620 A CN201810717620 A CN 201810717620A CN 108962881 A CN108962881 A CN 108962881A
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- CN
- China
- Prior art keywords
- solder joint
- stack
- package substrate
- plane
- application
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
The invention discloses stack package structure, one of stack package structure includes: package substrate or applies IC, and surface is provided with the first solder joint；At least two devices, at least two device stack；Plane where it intersects with the first plane where the package substrate or application IC；The side of at least two device surface towards the package substrate or application IC is provided with the second solder joint, and second solder joint is electrically connected with first solder joint.Stack package structure provided by the present invention, even if the number of plies stacked is more, the pad and the distance between pad on package substrate or application IC of each layer device are also shorter, to connect, lead needed for pad is shorter, and the time delay of signal transmission is smaller.Additionally it is possible to avoid TSV technique, production method is simple；Plane where the device of stacking intersects with plane where package substrate or application IC, can reduce package dimension, and increase effective unit in encapsulating structure.
Description
Technical field
The present invention relates to surface mount process technical fields, and in particular to stack package structure.
Background technique
With the continuous development of semiconductor processing technology and three-dimensional encapsulation technology, electronic device and electronic product are to more function
The requirement that can change and be miniaturized is higher and higher.Stacked package technology enables to encapsulation volume smaller, lead Distance Shortened to
Make signal transmission faster.
Prior art discloses a kind of stack package structures, as shown in Figure 1, being mounted on encapsulation using 20 flip-chip of IC
In substrate 10, two formal dress of IC 50 and 52 are stacked on using on IC 20, and the side of two the same sides IC is arranged in a staggered manner to reveal
Pad out.It is provided with pad on one side 54 that IC 50 is staggered, and passes through conducting wire 58 for the weldering of the pad and 10 surface of package substrates
Disk 30 connects；It is provided with pad on one side 56 that IC 52 is staggered, and passes through conducting wire 60 for the pad and 10 surface of package substrates
Pad 30 connects.
However, above-mentioned stack package structure often stacks in the direction perpendicular to package substrates surface, when the number of plies of stacking
When more, the distance between pad is larger on the pad and package substrates of upper device, and lead needed for connecting pad is longer, meeting
The time delay for causing signal to transmit is larger.
Summary of the invention
In view of this, the embodiment of the invention provides stack package structure, to solve to connect pad institute when stacking number is more
The problem that the lead needed is longer, causes signal propagation delay time larger.
First aspect present invention provides a kind of stack package structure, comprising: package substrate applies IC, surface setting
There is the first solder joint；At least two devices, at least two device stack；Plane and the package substrate or application where it
The first plane intersection where IC；The side of at least two device surface towards the package substrate or application IC is provided with
Second solder joint, second solder joint are electrically connected with first solder joint.
Above-mentioned stack package structure, device stack, and flat where the plane where device and package substrate or application IC
The side of face intersection, device surface towards package substrate or application IC is provided with solder joint, with solder joint on package substrate or application IC
Electrical connection, device stack direction is substantially parallel with package substrate or the application surface IC, even if the number of plies stacked is more, each layer device
Pad and the distance between package substrate or the upper pad of application IC it is also shorter, so that it is shorter to connect lead needed for pad, believe
Number transmission time delay it is smaller.Additionally it is possible to avoid TSV technique, production method is simple；Plane where the device of stacking and encapsulation
Substrate or the plane intersection of the place application IC, can reduce package dimension, and increase effective unit in encapsulating structure.
Second aspect of the present invention provides a kind of stack package structure, comprising: package substrate applies IC, surface setting
There is third solder joint；At least one device group, the device group include: the first device and the second device, first device and institute
It states the second device to stack, the position of the two pad is corresponding and is electrically connected；It is flat where first device, second device
Intersect with the first plane where the package substrate or application IC in face；At least one device surface is towards institute in the device group
The side for stating package substrate or application IC is provided with the 4th solder joint；The third solder joint is electrically connected with the 4th solder joint.
Optionally, the part of the second device is overlapped with the first device, stretches out the part of the surface setting described the of the second device
Four solder joints.
Optionally, the one side edge towards the package substrate or application IC of at least one device is opened in the device group
Equipped with gap, the position of at least one the 4th solder joint and the position of the gap are adapted.
Optionally, the stack package structure includes at least two device groups, and at least two devices group is in first party
It stacks upwards；The first direction intersects with the plane where first device, second device.
Optionally, the first direction and the plane where first device, second device are substantially vertical.
Optionally, one of first device and second device are memory device, and another one is logical device；
Or first device and second device are memory device.
Above-mentioned stack package structure, even if the number of plies stacked is more, the pad of each layer device group and package substrate or application
The distance between the upper pad of IC is also shorter, to connect, lead needed for pad is shorter, and the time delay of signal transmission is smaller, specifically asks
With reference to first aspect；Each device group includes the first device and the second device, and the position of the two pad is corresponding and is electrically connected, from
And the number of plies of stacking can be further increased in the case where not increasing wire length.Additionally it is possible to avoid TSV technique, make
It is simple to make method；Plane where the device of stacking intersects with plane where package substrate or application IC, can reduce package dimension,
And increase effective unit in encapsulating structure.
Detailed description of the invention
The features and advantages of the present invention will be more clearly understood by referring to the accompanying drawings, and attached drawing is schematically without that should manage
Solution is carries out any restrictions to the present invention, in the accompanying drawings:
Fig. 1 shows the schematic diagram of existing stack package structure；
Fig. 2 shows a kind of longitudinal profile schematic diagrams of stack package structure according to an embodiment of the present invention；
Fig. 3 shows the longitudinal profile schematic diagram of device group according to an embodiment of the present invention；
Fig. 4 shows the longitudinal profile schematic diagram of another stack package structure according to an embodiment of the present invention；
Fig. 5 shows the longitudinal profile schematic diagram of another stack package structure according to an embodiment of the present invention；
Fig. 6 shows the longitudinal profile schematic diagram of another stack package structure according to an embodiment of the present invention.
Specific embodiment
In order to keep the purpose of the present invention, advantage clearer, below in conjunction with attached drawing to implementation example progress of the invention
Detailed description, examples of the embodiments are shown in the accompanying drawings, and wherein part-structure has directly given preferred structure in attached drawing,
Obviously, described embodiments are some of the embodiments of the present invention, instead of all the embodiments.It should be noted that with reference to
The embodiment of attached drawing description is exemplary, and the structure shown in embodiment is also exemplary, for explaining only the invention, and
Be not construed as limiting the claims, the attached drawing of each embodiment of the present invention merely to signal purpose, therefore must not
Want drawn to scale.Based on the embodiments of the present invention, those skilled in the art institute without creative efforts
The every other embodiment obtained, shall fall within the protection scope of the present invention.
Embodiment one
The embodiment of the invention provides a kind of stack package structures, as shown in Fig. 2, including package substrate or applying IC 10
With at least two devices 21.
The surface of package substrate or application IC 10 are provided with the first solder joint 11.
At least two device 21 stacks, where the plane and package substrate or application IC 10 where these devices 21
First plane intersects (it is alternatively possible to being substantially vertical).
The side of at least two devices, 21 surface towards package substrate or application IC 10 is provided with the second solder joint 22, the
Two solder joints 22 are electrically connected with the first solder joint 11.Second solder joint 22 can be pad；Alternatively, being also possible to salient point, it is arranged in device
21 first surface, position corresponding with salient point is begun with open-minded on the second surface (and first surface is oppositely arranged) of device 21
Mouthful；Or it is also possible to other forms, the application does not limit this.
Stack package structure provided by the embodiment of the present invention, device stack, and the plane where device and encapsulation base
Plate or the plane intersection of the place application IC, the side of device surface towards package substrate or application IC are provided with solder joint, with encapsulation base
Plate is electrically connected using solder joint on IC, and device stack direction is substantially parallel with package substrate or the application surface IC, even if stack
The number of plies is more, and the pad and the distance between pad on package substrate or application IC of each layer device are also shorter, to connect pad
Required lead is shorter, and the time delay of signal transmission is smaller.Additionally it is possible to avoid TSV technique, production method is simple；It stacks
Plane where device intersects with plane where package substrate or application IC, can reduce package dimension, and increase in encapsulating structure
Effective unit.
Device 21 in the embodiment of the present invention can be memory device, or logical device.
Embodiment two
The embodiment of the invention provides a kind of stack package structures, as shown in figure 3, the stack package structure includes encapsulation base
Plate or application IC 10 and at least one device group 20.
The surface of package substrate or application IC 10 are provided with third solder joint 11.As shown in figure 3, device group 20 includes first
Device 23 and the second device 24, the first device 23 and the second device 24 stack, and the position of the two pad is corresponding and is electrically connected.The
Plane where one device 23 and the second device 24 intersects with the first plane where package substrate or application IC 10, such as Fig. 5 institute
Show；Be also possible to it is substantially vertical, such as Fig. 2, Fig. 4 and Fig. 6.At least one device surface towards package substrate or is answered in device group 20
The side of IC 10 is provided with the 4th solder joint 22, third solder joint 11 is electrically connected with the 4th solder joint 22.
Stack package structure provided by the embodiment of the present invention, even if the number of plies stacked is more, the pad of each layer device group
Also shorter with the distance between pad on package substrate or application IC, to connect, lead needed for pad is shorter, and signal transmits
Time delay it is smaller, specifically please refer to embodiment one；Each device group includes the first device and the second device, the position of the two pad
It is corresponding and be electrically connected, so as to further increase the number of plies of stacking in the case where not increasing wire length.Moreover it is possible to
TSV technique is enough avoided, production method is simple；Plane where the device of stacking intersects with plane where package substrate or application IC,
Package dimension can be reduced, and increases effective unit in encapsulating structure.
It can be at least two device groups that the embodiment of the present invention, which provides stack package structure, and at least two devices group is the
It is stacked on one direction.As a kind of optional embodiment, between the plane at 10 place of first direction and package substrate or application IC
Angle be acute angle (being, for example, less than 45 ° of angle, the angle less than 30 °, the angle less than 15 °, the angle less than 5 °), such as scheme
Shown in 5；Alternatively, where a kind of replacement embodiment as the embodiment, first direction and package substrate or application IC 10
Plane it is substantially parallel, as shown in Figure 4 and Figure 6.
One of first device 23 and the second device 24 in the present patent application be memory device (i.e. for storing data
Device), another one is logical device the device of logical process (be used for)；Alternatively, the first device 23 and the second device 24 are
For memory device；It is of course also possible to which the first device 23 and the second device 24 are logical device.
Embodiment three
The embodiment of the invention provides another stack package structure, the difference with embodiment two is, the second device
(24) part is overlapped with the first device (23), and the 4th solder joint 22 is arranged in the part of the surface for stretching out the first device (23).Such as Fig. 4 institute
Show.
Example IV
The embodiment of the invention provides another stack package structure, the difference with embodiment two or embodiment three is,
The one side edge towards package substrate or application IC 10 of at least one device offers gap in device group 20, at least one
The position of 4th solder joint 22 and the position of gap are adapted.As shown in Figure 6.
It should be added that the solder joint in the application can be pad, pad is with salient point, soldered ball, pad by leading
Line connection；Or solder joint is also possible to salient point or soldered ball, contacts and is electrically connected between solder joint.
It should be readily apparent to one skilled in the art that the positional relationship in the application between package substrate or application IC and device is logical
It crosses molding layer or plastic packaging layer (as shown in 40 regions in figure) is fixed.In package substrate or surface, molding layer or the plastic packaging of application IC
Layer is external can also to be arranged soldered ball (as shown in Fig. 2, Fig. 4-6) or pad.
Although being described in detail about example embodiment and its advantage, those skilled in the art can not departed from
Various change, replacement are carried out to these embodiments in the case where spirit of the invention and protection scope defined in the appended claims
And modification, such modifications and variations are each fallen within be defined by the appended claims within the scope of.For other examples, ability
The those of ordinary skill in domain should be readily appreciated that the order of processing step can become while keeping in the scope of the present invention
Change.
Claims (7)
1. a kind of stack package structure characterized by comprising
Package substrate applies IC, and surface is provided with the first solder joint；
At least two devices, at least two device stack；Where plane and the package substrate or application IC where it
The first plane intersection；
The side of at least two device surface towards the package substrate or application IC is provided with the second solder joint, and described second
Solder joint is electrically connected with first solder joint.
2. a kind of stack package structure characterized by comprising
Package substrate applies IC, and surface is provided with third solder joint；
At least one device group, the device group include: the first device and the second device, first device and second device
Part stacks, and the position of the two pad is corresponding and is electrically connected；Plane where first device, second device with it is described
Package substrate intersects using the first plane where IC；
The side of at least one device surface towards the package substrate or application IC is provided with the 4th solder joint in the device group；
The third solder joint is electrically connected with the 4th solder joint.
3. stack package structure according to claim 2, which is characterized in that the part of the second device and the first device weight
It closes, the 4th solder joint is arranged in the part of the surface for stretching out the second device.
4. stack package structure according to claim 2, which is characterized in that the court of at least one device in the device group
Gap is offered to the one side edge of the package substrate or application IC, the position of at least one the 4th solder joint is slitted with described
The position of mouth is adapted.
5. stack package structure according to claim 2, which is characterized in that the stack package structure includes at least two
Device group, at least two devices group stack in a first direction；The first direction and the package substrate apply IC
Angle between the plane at place is acute angle.
6. stack package structure according to claim 2, which is characterized in that the stack package structure includes at least two
Device group, at least two devices group stack in a first direction；The first direction and the package substrate apply IC
The plane at place is substantially parallel.
7. according to the described in any item stack package structures of claim 2 to 6, which is characterized in that first device and described
One of second device is memory device, and another one is logical device；Or first device and second device it is equal
For memory device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810717620.5A CN108962881A (en) | 2018-07-03 | 2018-07-03 | Stack package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810717620.5A CN108962881A (en) | 2018-07-03 | 2018-07-03 | Stack package structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108962881A true CN108962881A (en) | 2018-12-07 |
Family
ID=64485203
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810717620.5A Withdrawn CN108962881A (en) | 2018-07-03 | 2018-07-03 | Stack package structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108962881A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111063664A (en) * | 2019-12-27 | 2020-04-24 | 华天科技（西安）有限公司 | Modularized multi-chip packaging structure and packaging method thereof |
| WO2021103642A1 (en) * | 2019-11-26 | 2021-06-03 | 长鑫存储技术有限公司 | Chip combination and chip |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62260354A (en) * | 1986-05-06 | 1987-11-12 | Mitsubishi Electric Corp | Semiconductor device |
| US20170018529A1 (en) * | 2015-07-17 | 2017-01-19 | Invensas Corporation | Flipped die stack |
| US20170294410A1 (en) * | 2016-04-11 | 2017-10-12 | Invensas Corporation | Microelectronic packages having stacked die and wire bond interconnects |
| CN208298821U (en) * | 2018-07-03 | 2018-12-28 | 华进半导体封装先导技术研发中心有限公司 | Stack package structure |
-
2018
- 2018-07-03 CN CN201810717620.5A patent/CN108962881A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62260354A (en) * | 1986-05-06 | 1987-11-12 | Mitsubishi Electric Corp | Semiconductor device |
| US20170018529A1 (en) * | 2015-07-17 | 2017-01-19 | Invensas Corporation | Flipped die stack |
| US20170294410A1 (en) * | 2016-04-11 | 2017-10-12 | Invensas Corporation | Microelectronic packages having stacked die and wire bond interconnects |
| CN208298821U (en) * | 2018-07-03 | 2018-12-28 | 华进半导体封装先导技术研发中心有限公司 | Stack package structure |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021103642A1 (en) * | 2019-11-26 | 2021-06-03 | 长鑫存储技术有限公司 | Chip combination and chip |
| US11164849B2 (en) | 2019-11-26 | 2021-11-02 | Changxin Memory Technologies, Inc. | Chip assembly and chip |
| CN111063664A (en) * | 2019-12-27 | 2020-04-24 | 华天科技（西安）有限公司 | Modularized multi-chip packaging structure and packaging method thereof |
| CN111063664B (en) * | 2019-12-27 | 2021-06-29 | 华天科技(南京)有限公司 | Modularized multi-chip packaging structure and packaging method thereof |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
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| WW01 | Invention patent application withdrawn after publication | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20181207 |