CN108962865A - A kind of multi-chip PQFN packaging method and structure - Google Patents

A kind of multi-chip PQFN packaging method and structure Download PDF

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Publication number
CN108962865A
CN108962865A CN201810790170.2A CN201810790170A CN108962865A CN 108962865 A CN108962865 A CN 108962865A CN 201810790170 A CN201810790170 A CN 201810790170A CN 108962865 A CN108962865 A CN 108962865A
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China
Prior art keywords
power device
lead frame
chip
pqfn
high side
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Granted
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CN201810790170.2A
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Chinese (zh)
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CN108962865B (en
Inventor
张允武
许欢
胡孔生
陆扬扬
禹阔
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Wuxi Safe Electronics Co Ltd
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Wuxi Safe Electronics Co Ltd
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Priority to CN201810790170.2A priority Critical patent/CN108962865B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A kind of multi-chip PQFN packaging method and structure, the described method comprises the following steps: not being coupled in the principle of the same lead frame with remaining high side power device based at least one high side power device, be distributed lead frame；Multi-chip module is coupled on corresponding lead frame；Connect multi-chip module；Wherein, the multi-chip module includes at least one described high side power device and remaining described high side power device.Of the invention a kind of multi-chip PQFN packaging method and structure, the system connection between multi-chip module is realized using inexpensive single-layer lead frame, it is compared to traditional low-cost single-layer lead frame PQFN encapsulating structure, cabling and wiring difficulty are reduced, the electric interconnection of lead frame is made full use of to improve whole electric property.

Description

A kind of multi-chip PQFN packaging method and structure
Technical field
The present invention relates to the multi-chip package technical fields of semiconductor devices, encapsulate more particularly to a kind of multi-chip PQFN Method and structure.
Background technique
Multi-chip PQFN(Power Quad Flat No-Lead, Power Quad Flat is without pin) encapsulating structure is to be based on Four side flat non-pin (QFN) surface mounting technologies of JEDEC standard, by multiple semiconductor devices and circuit package to together, And the encapsulating structure for encapsulating whole hot property is improved, it is usually used in high voltage and high power application system.By multiple semiconductor devices with Electrical combination not only can simplify circuit design into an encapsulating structure, reduce cost, moreover it is possible to because of the close cloth of relevant component Office and obtain higher efficiency and improve performance.Such multi-chip package technology promotees compared to individual discrete component is used Into application integration, higher electric property and hot property are obtained.And under circuit integration trend, multi-chip is combined The PQFN encapsulation of module is developed rapidly and is widely applied；Multi-chip PQFN package dimension is bigger, and encapsulating structure bottom is naked The bigger pin of product of showing up, has high power density circuit using required high efficiency and heat radiation ability.
The advantages of multi-chip PQFN is encapsulated first is that be that infrastructure cost is low, such as: lead frame therein has used list The multi-layer substrate of layer substrate rather than valuableness.However when using the lead frame of single layer of substrate material, in multi-chip PQFN encapsulation Cabling and wiring become more difficult, and reason is that the top electric interconnection of circuit and device must be realized by bonding line, And bonding line is distributed necessary appropriate design, avoids bonding line short-circuit.And working as by the way of increasing package thickness reduces bonding When line short-circuit risks, encapsulate that whole reliability is usually unsatisfactory, such as: the risk for encapsulating cracking will increase.
Fig. 1 is the circuit diagram of three-phase drive chip and power tube typical case connection type in the prior art, such as Fig. 1 institute Show, it usually needs both three-phase drive chip and power tube are encapsulated in identical carrier, and in certain a pair of of power tube (containing height Side power tube and lowside power pipe) branch road, it will usually increase signal detection branch, for detecting power tube working condition. Fig. 2 is the top schematic diagram of encapsulating structure involved in the patent application document of Publication No. CN201110126379, such as Fig. 2 It is shown, in the patent application document, propose in existing PQFN encapsulating structure scheme, extremely by the first power device of high side Third power device package will lead to the signal that the source electrode in lowside power pipe is connected to ground in same lead frame in this way Sampled signal poor anti jamming capability in detection branch.
Summary of the invention
In order to solve the shortcomings of the prior art, the purpose of the present invention is to provide a kind of multi-chip PQFN packaging methods And structure makes full use of the conductive capability of lead frame itself, the integrated electricity of substitution driving by the multiple lead frames of reasonable layout The long cabling connection in part between road and power device, realizes integrally-built electric interconnection.
To achieve the above object, multi-chip PQFN packaging method provided by the invention, comprising the following steps:
It is not coupled in the principle of the same lead frame with remaining high side power device based at least one high side power device, point Cloth lead frame；
Multi-chip module is coupled on corresponding lead frame；
Connect multi-chip module；
Wherein, the multi-chip module includes at least one described high side power device and remaining described high side power device.
Further, the multi-chip module further includes lowside power device, at least one lowside power device with it is described At least one high side power device is located at same branch at least one high side power device.
Further, company's muscle of at least one lead frame does special pin, at least one multi-chip module Ground Pad is connected by bonding line.
Further, the multi-chip module further includes at least two lowside power devices, at least two lowside power devices Part passes through bonding line respectively and is connected with corresponding pin pad.
To achieve the above object, multi-chip PQFN encapsulating structure provided by the invention, comprising: lead frame and multi-chip mould Block, the multi-chip module include high side power device, wherein
At least one high side power device is not coupled in the same lead frame with remaining high side power device；
The multi-chip module is coupled on corresponding lead frame.
Further, the multi-chip module further include: lowside power device,
At least one lowside power device is located at at least one high side power device at least one described high side power device Same branch.
Further, company's muscle of at least one lead frame does special pin, the ground Pad at least one multi-chip module It is connected by bonding line.
Further, the multi-chip module further includes at least two lowside power devices,
At least two lowside power devices pass through bonding line respectively and are connected with corresponding pin pad.
Further, the multi-chip module further includes lowside power device and driver IC,
The high side power device, the lowside power device and the driver IC constitute full-bridge drive system.
Further, the high side power device and the lowside power device are vertical conduction power device.
Technical solution of the present invention has the advantages that
While not increasing package thickness and size, the multiple lead frames of reasonable layout simultaneously make full use of lead frame itself Conductive capability substitutes the long cabling connection in part between drive integrated circult and power device, reduces low-cost package structure Cabling difficulty improves the reliability and electric property of total system；Company's muscle of lead frame is done into special pin, as The pressure welding point or supporting point of lead frame are conducive to the reliability and stability for improving encapsulating structure；
In addition, the exposed large area lead metal in bottom of multi-chip PQFN encapsulating structure of the invention, is conducive to overall structure height Effect heat dissipation；And multiple high side power devices (the first, second vertical conduction power device) are coupled in a lead frame that (the 6th draws Wire frame), and mutually separated with remaining high side power device (third vertical conduction power device), it can be improved and be connected to remaining High side power device (third vertical conduction power device) where branch lowside power device source electrode and ground between detect The signal anti-interference ability of circuit.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification It obtains it is clear that understand through the implementation of the invention.
Detailed description of the invention
Attached drawing is used to provide further understanding of the present invention, and constitutes part of specification, and with it is of the invention Embodiment together, is used to explain the present invention, and is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is the circuit diagram of three-phase drive chip and power tube typical case connection type in the prior art；
Fig. 2 is the top schematic diagram of encapsulating structure involved in the patent application document of Publication No. CN201110126379；
Fig. 3 is the flow chart of multi-chip PQFN packaging method according to the present invention；
Fig. 4 is according to the schematic diagram that lead frame is distributed in PQFN encapsulating structure top surface in one embodiment of the invention；
Fig. 5 be according in one embodiment of the invention without the top schematic diagram of the PQFN encapsulating structure of bonding line；
Fig. 6 is the top schematic diagram according to the PQFN encapsulating structure for having bonding line in one embodiment of the invention；
Fig. 7 is the schematic bottom view according to PQFN encapsulating structure in one embodiment of the invention；
Fig. 8 is the part according to the lead frame of PQFN encapsulating structure and power device coupling part in one embodiment of the invention Sectional view；
Fig. 9 is the partial cross section according to the lead frame of PQFN encapsulating structure in one embodiment of the invention and pin connection point Figure.
Specific embodiment
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings, it should be understood that preferred reality described herein Apply example only for the purpose of illustrating and explaining the present invention and is not intended to limit the present invention.
Fig. 3 is the flow chart of multi-chip PQFN packaging method according to the present invention, below with reference to Fig. 3, and by specific Multi-chip PQFN packaging method and its structure of the invention is set forth in embodiment.
In step S301, same draw is not coupled in remaining high side power device based at least one high side power device The principle of wire frame is distributed lead frame.
Fig. 4 is according to the top schematic diagram that lead frame is distributed in PQFN encapsulating structure in one embodiment of the invention, such as Encapsulating structure shown in Fig. 4, in the present embodiment, comprising: one group of lead frame comprising: the first, second, third, fourth, Five, the 6th lead frame 001,002,003,004,005,006, and it is distributed in the bottom surface of PQFN encapsulating structure, wherein
Piece company's muscle of first lead frame 001 does Pin foot (also referred to as connecting muscle pin) 010 and is drawn out to the first of encapsulating structure Edge, crimping point/supporting point as encapsulating structure；
Piece company's muscle of the second lead frame 002 does Pin foot 011 and draws in the second edge for arriving encapsulating structure, ties as encapsulation Crimping point/supporting point of structure；
Three Pin feet of the 5th lead frame 005 are drawn out to the third edge of encapsulating structure；
Five Pin feet of the 6th lead frame 006 are drawn out to the third edge of encapsulating structure, and three Pin feet are drawn out to encapsulation knot Second edge of structure；
Second, third, near the 4th lead frame 002,003,004, be equipped with three groups of pin pads: first, second, third group Pin pad 007,008,009, wherein first, second group of pin pad 007,008 is located at the 4th edge of encapsulating structure；The Three groups of pin pads 009 are located at the third edge of encapsulating structure；
The first, second, third, fourth, the surface of the 5th lead frame 001,002,003,004,005 is coated with corresponding plating Layer 104i, 104f, 104e, 104d, 104c；
The surface of 6th lead frame 006 is coated with first, second electroplated layer 104b, 104a；
Also be coated with respectively on second, third lead frame 002,003 for bonding line connection third, the 4th electroplated layer 104h, 104g；
Wherein, 108 be PQFN encapsulating structure mold compound (such as moulding resin).
In step S302, multi-chip module is distributed on corresponding lead frame.
In the step, multi-chip module is distributed to respectively by conductive adhesive layer on the electroplated layer of each lead frame On corresponding lead frame.
Fig. 5 be according in one embodiment of the invention without the top schematic diagram of the PQFN encapsulating structure of bonding line.Such as Fig. 5 It is shown, based on the above embodiment, the encapsulating structure in the present embodiment, further includes: multi-chip module comprising: driver is integrated Circuit 100 and power device, wherein power device includes: first, second, third, fourth, the 5th, the straight conducted power of sextuple Device 101a, 101b, 101c, 101d, 101e, 101f, specifically,
Driver IC 100 is placed on first lead frame 001 by electroconductive binder；
First, second vertical conduction power device 101a, 101b is placed on the 6th lead frame 006 by electroconductive binder；
Third vertical conduction power device 101c is placed on the 5th lead frame 005 by electroconductive binder；
4th vertical conduction power device 101d is placed on the 4th lead frame 004 by electroconductive binder；
5th vertical conduction power device 101e is placed on third lead frame 003 by electroconductive binder；
Sextuple, which direct transfers, leads power device 101f and is placed on the second lead frame 002 by electroconductive binder.
In the present embodiment, power device is MOSFET or insulated gate bipolar transistor IGBT, it is preferable that is also possible to The fast MOSFET or insulated gate bipolar transistor IGBT for restoring function of band.
In step S303, multi-chip module is connected.
In the step, in multi-chip module: driver IC 100 and each power device 101a ~ 101f are adhered to After corresponding lead frame, multi-chip module is connected by bonding line, and draw corresponding pin.
Fig. 6 is the top schematic diagram according to the PQFN encapsulating structure for having bonding line in one embodiment of the invention.Such as Fig. 6 Shown, based on the above embodiment, the driver IC 100 in the encapsulating structure in the present embodiment has 23 general Pad With 1 ground (Ground) Pad, wherein
6 general Pad pass through respectively bonding line be connected to first, second, third, fourth, the 5th, sextuple direct transfers and leads power device Grid 103a, 103b, 103c, 103d, 103e, 103f of part 101a, 101b, 101c, 101d, 101e, 101f；
1 general Pad for being different from above-mentioned 6 general Pad is connected to third vertical conduction power device 101c by bonding line Source electrode 102c；
2 general Pad for being different from above-mentioned 7 general Pad pass through the third that bonding line is connected on the second lead frame 002 respectively 4th electroplated layer 104g on electroplated layer 104h and third lead frame 003；
14 general Pad for being different from above-mentioned 9 general Pad pass through first group of bonding line 107b respectively and are connected to first lead frame On pin pad around frame 001；
Ground (Ground) Pad is connected on the pad of company's muscle pin 010 of first lead frame 001 by bonding line, pin 010 A pin is shared with the ground (Ground) of driver IC 100, space can be saved and wanted to meet basic spacing It asks.
The source electrode 102a of first vertical conduction power device 101a is connected on the second lead frame 002 by bonding line Third electroplated layer 104h；
The source electrode 102b of second vertical conduction power device 101b is connected to third lead frame by second group of bonding line 106 The 4th electroplated layer 104g on 003；
The source electrode 102c of third vertical conduction power device 101c is connected to the plating on the 4th lead frame 004 by bonding line Layer 104d；
The source electrode 102d of 4th vertical conduction power device 101d is connected to the weldering of third group pin by third group bonding line 107a Disk 009；
The source electrode 102e of 5th vertical conduction power device 101e is connected to second group of pin pad 008 by bonding line；
Sextuple, which direct transfers, leads the source electrode 102f of power device 101f and is connected to first group of pin pad 007 by bonding line.
The driver IC 100 and power device (first, second, encapsulated in encapsulating structure in the present embodiment Three, the four, the 5th, sextuple direct transfers and leads power device 101a, 101b, 101c, 101d, 101e, 101f) constitute full-bridge driving system System.
Wherein, first, second, third vertical conduction power device 101a, 101b, 101c is high side power device；4th, 5th, it is lowside power device that sextuple, which direct transfers and leads power device 101d, 101e, 101f,.
Fig. 7 is the schematic bottom view according to PQFN encapsulating structure in one embodiment of the invention, as shown in fig. 7, based on upper Embodiment is stated, after the PQFN encapsulating structure in the present embodiment is via flip horizontal, bottom surface there can be the lead frame of large area And the pin around encapsulating structure, and the profile of the electroplated layer in the top surface of the lead frame profile and encapsulating structure exposed Unanimously, such as: the lead frame 205a exposed correspond to encapsulating structure top surface in the 6th lead frame 006；It exposes Lead frame 205b correspond to encapsulating structure top surface in third lead frame 003.
From in Fig. 7 it can be found that in the bottom surface of the PQFN encapsulating structure in the present embodiment exposure large area lead frame, Be conducive to the high efficiency and heat radiation of encapsulating structure entirety, and can be improved electric property.
Fig. 8 is according to the lead frame of PQFN encapsulating structure in one embodiment of the invention and power device coupling part Partial section view.Below with reference to Fig. 8, based on the above embodiment, clearly describe to draw in the encapsulating structure in the present embodiment Bonding line connection type between wire frame and power device.
As shown in figure 8, the 6th lead frame 006(305a), third lead frame 003(305b) plate one layer first respectively Electroplated layer 104b(304b), be not shown in second electroplated layer 104a(Fig. 8) and the 4th electroplated layer 104g(304g)；
Second vertical conduction power device 101b(301b), the first electroplated layer is fixed on by one layer of conductive adhesive layer 309 On 104b(304b), drain electrode 310b is sticked in conductive adhesive layer 309, source electrode 102b(302b) pass through second group of bonding line 106(306) be connected to third lead frame 003(305b) on the 4th electroplated layer 104g(304g), grid 103b(303b) Positioned at its top surface；
Wherein, remaining other structures are the mold compound 108(308 in encapsulating structure).
In the present embodiment, label X(Y) it indicates, component Y is partial cross section of the component X in figure.
Fig. 9 is the part according to the lead frame of PQFN encapsulating structure in one embodiment of the invention and pin connection point Sectional view based on the above embodiment, clearly describes lead frame in the encapsulating structure in the present embodiment below with reference to Fig. 9 The a variety of connection types having between pin around frame and encapsulating structure.
As shown in figure 9, first lead frame 001(401) a company muscle pin 010(411) draw, and with corresponding pressure Solder joint connection；4th lead frame 004(404) on the 4th vertical conduction power device 101d(401d) source electrode 102d(402d) It is connect between the electroplated layer 409 on third group pin pad 009(410) by third group bonding line 107a (407a).
In Fig. 9,404d is partial cross section of the electroplated layer 104d in figure on the 4th lead frame 004；
414 partial cross section for the electroplated layer 104i on first lead frame 001 in figure；
413 be the conductive adhesive layer on the 4th lead frame 004；
415 be the conductive adhesive layer on first lead frame 001；
412 be partial cross section of the drain electrode of the 4th vertical conduction power device 101d in figure；
403d is partial cross section of the grid 103d of the 4th vertical conduction power device 101d in figure；
400 be partial cross section of the driver IC 100 in figure；
416 partial cross section for the general Pad on driver IC 100 in figure；
408 be partial cross section of the mold compound 108 in figure.
Of the invention a kind of multi-chip PQFN packaging method and structure, realize multi-chip using inexpensive single-layer lead frame System connection between module, is compared to traditional low-cost single-layer lead frame PQFN encapsulating structure, reduces cabling and cloth Line difficulty makes full use of the electric interconnection of lead frame to improve whole electric property；The exposure of large area lead metal is advantageous In the high efficiency and heat radiation of encapsulating structure itself, and the reliability of system also greatly improves therewith；On lead frame there are two couplings Power device is the anti-interference ability for the system that improves, and is conducive to the saving of package area and improves heat-sinking capability；Compared to more Layer lead-frame packages structure, packaging cost are even more to be greatly lowered.
Those of ordinary skill in the art will appreciate that: the foregoing is only a preferred embodiment of the present invention, and does not have to In the limitation present invention, although the present invention is described in detail referring to the foregoing embodiments, for those skilled in the art For, still can to foregoing embodiments record technical solution modify, or to part of technical characteristic into Row equivalent replacement.All within the spirits and principles of the present invention, any modification, equivalent replacement, improvement and so on should all include Within protection scope of the present invention.

Claims (10)

1. a kind of multi-chip PQFN packaging method, which comprises the following steps:
It is not coupled in the principle of the same lead frame with remaining high side power device based at least one high side power device, point Cloth lead frame；
Multi-chip module is coupled on corresponding lead frame；
Connect multi-chip module；
Wherein, the multi-chip module includes at least one described high side power device and remaining described high side power device.
2. a kind of multi-chip PQFN packaging method according to claim 1, which is characterized in that
The multi-chip module further includes lowside power device, at least one lowside power device and at least one described high side At least one high side power device is located at same branch in power device.
3. a kind of multi-chip PQFN packaging method according to claim 1, which is characterized in that
Company's muscle of at least one lead frame does special pin, passes through with the ground Pad of at least one multi-chip module and is bonded Line connection.
4. a kind of multi-chip PQFN packaging method according to claim 1, which is characterized in that
The multi-chip module further includes that at least two lowside power devices, at least two lowside power devices pass through key respectively Zygonema is connected with corresponding pin pad.
5. a kind of multi-chip PQFN encapsulating structure characterized by comprising lead frame and multi-chip module, the multi-chip Module includes high side power device, wherein
At least one high side power device is not coupled in the same lead frame with remaining high side power device；
The multi-chip module is coupled on corresponding lead frame.
6. a kind of multi-chip PQFN encapsulating structure according to claim 5, which is characterized in that the multi-chip module also wraps It includes: lowside power device,
At least one lowside power device is located at at least one high side power device at least one described high side power device Same branch.
7. a kind of multi-chip PQFN encapsulating structure according to claim 5, which is characterized in that
Company's muscle of at least one lead frame does special pin, is connected with the ground Pad of at least one multi-chip module by bonding line It connects.
8. a kind of multi-chip PQFN encapsulating structure according to claim 5, which is characterized in that the multi-chip module also wraps It includes, at least two lowside power devices,
At least two lowside power devices pass through bonding line respectively and are connected with corresponding pin pad.
9. a kind of multi-chip PQFN encapsulating structure according to claim 5, which is characterized in that the multi-chip module also wraps It includes, lowside power device and driver IC,
The high side power device, the lowside power device and the driver IC constitute full-bridge drive system.
10. a kind of multi-chip PQFN encapsulating structure according to claim 9, which is characterized in that the high side power device And the lowside power device is vertical conduction power device.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080252372A1 (en) * 2007-04-13 2008-10-16 Advanced Analogic Technologies, Inc. Power-MOSFETs with Improved Efficiency for Multi-channel Class-D Audio Amplifiers and Packaging Thereof
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CN107658283A (en) * 2017-09-30 2018-02-02 杭州士兰微电子股份有限公司 For motor-driven integrated power module and SPM
CN207354064U (en) * 2017-09-30 2018-05-11 杭州士兰微电子股份有限公司 For motor-driven integrated power module and intelligent power module
US20180182719A1 (en) * 2016-12-28 2018-06-28 Renesas Electronics Corporation Semiconductor device
CN208460754U (en) * 2018-07-18 2019-02-01 无锡安趋电子有限公司 A kind of multi-chip PQFN encapsulating structure

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080252372A1 (en) * 2007-04-13 2008-10-16 Advanced Analogic Technologies, Inc. Power-MOSFETs with Improved Efficiency for Multi-channel Class-D Audio Amplifiers and Packaging Thereof
US20130257524A1 (en) * 2012-04-02 2013-10-03 International Rectifier Corporation (El Segundo, Ca) Monolithic Power Converter Package
US20180182719A1 (en) * 2016-12-28 2018-06-28 Renesas Electronics Corporation Semiconductor device
CN107658283A (en) * 2017-09-30 2018-02-02 杭州士兰微电子股份有限公司 For motor-driven integrated power module and SPM
CN207354064U (en) * 2017-09-30 2018-05-11 杭州士兰微电子股份有限公司 For motor-driven integrated power module and intelligent power module
CN208460754U (en) * 2018-07-18 2019-02-01 无锡安趋电子有限公司 A kind of multi-chip PQFN encapsulating structure

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