CN108962747A - Diode manufacturing method with ladder-type structure - Google Patents
Diode manufacturing method with ladder-type structure Download PDFInfo
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- CN108962747A CN108962747A CN201710373920.1A CN201710373920A CN108962747A CN 108962747 A CN108962747 A CN 108962747A CN 201710373920 A CN201710373920 A CN 201710373920A CN 108962747 A CN108962747 A CN 108962747A
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- semiconductor layer
- type semiconductor
- processing procedure
- chip body
- ladder
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 76
- 239000004065 semiconductor Substances 0.000 claims abstract description 66
- 238000012545 processing Methods 0.000 claims description 50
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 24
- 239000013078 crystal Substances 0.000 claims description 21
- 230000008569 process Effects 0.000 claims description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 18
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims description 13
- 238000001816 cooling Methods 0.000 claims description 10
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 claims description 6
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 6
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 6
- 229960000583 acetic acid Drugs 0.000 claims description 6
- 239000007788 liquid Substances 0.000 claims description 6
- 229910017604 nitric acid Inorganic materials 0.000 claims description 6
- 238000011161 development Methods 0.000 claims description 5
- 239000012362 glacial acetic acid Substances 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- -1 i.e. Substances 0.000 claims 2
- 239000010410 layer Substances 0.000 abstract description 62
- 239000011241 protective layer Substances 0.000 abstract description 12
- 238000005538 encapsulation Methods 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 11
- 239000002245 particle Substances 0.000 description 8
- 230000006872 improvement Effects 0.000 description 6
- 239000011521 glass Substances 0.000 description 5
- 230000004224 protection Effects 0.000 description 5
- 239000002253 acid Substances 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 238000005245 sintering Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000011469 building brick Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
Abstract
A kind of diode manufacturing method with ladder-type structure, the diode grain structure mainly includes a n type semiconductor layer, it is one p type semiconductor layer of storehouse in the one side of the n type semiconductor layer, a N+ type semiconductor layer is attached on the another side of the n type semiconductor layer, it is that there is a groove in the periphery of the p type semiconductor layer, finally the top surface with an insulating protective layer and the insulating protective layer in the groove of the n type semiconductor layer periphery and p type semiconductor layer is not higher than the p type semiconductor layer top surface, the height of the insulating protective layer is reduced by the design of the p type semiconductor layer groove, ensure that the acceptance rate of subsequent encapsulation procedure gets a promotion, and improve the efficiency of diode entirety.
Description
Technical field
The invention relates to a kind of diodes, refer in particular to a kind of diode manufacturing method with ladder-type structure.
Background technique
Rectifier diode is a kind of separate type component in the industry, and rectifier diode is mainly used for as rectification and inhibits
Abnormal signal two acts on greatly, and so-called rectification, which refers to have, to be converted alternating current to as direct current, and inhibit abnormal signal refer to by
Input signal is removed beyond range part is limited, and to maintain the stabilization of input signal, to be used as protection circuit, rectifies two poles
Pipe institute's use scope is indispensable one of electronic building brick on the fields such as semiconductor, communication and consumer electronics.
It is currently known the structure of diode crystal particle, as shown in the known grain structure schematic diagram of Fig. 1, it is known that diode crystal particle
For a PN diode crystal particle 10, which includes a N+ type semiconductor layer 101, in the N+ type semiconductor layer 101
Upper one n type semiconductor layer 102 of storehouse, then in one p type semiconductor layer 103 of upper surface storehouse of n type semiconductor layer 102, and at this
A protective layer 104 is equipped on 10 periphery of crystal grain again, which is an insulating glass.
In diode processing procedure, crystal grain can first pass through the size that etching process defines crystal grain before cutting, and in crystal grain
The peripheral position etched is sintered processing procedure, i.e., is sintered in sintering furnace after the peripheral position is placed in glass powder, with
The protective layer 104 is formed, then carries out the cooling encapsulation processing procedure of crystal grain after crystal grain cutting, is dissipated with forming crystal grain as shown in Figure 2
Seal assembling structure.
However, as shown in the PN diode crystal particle 10 of Fig. 1, as the protective layer of insulation protection in sintering process
104 after sintered, and for the insulating properties of the complete preservation crystal grain, p type semiconductor layer 103 can be higher than by being formed by structure；
Therefore, in subsequent cooling encapsulation processing procedure, in order to cooperate 104 structure of protective layer of its 10 peripheral projection of PN diode crystal particle,
The cooling fin 105 being located on p type semiconductor layer 103 must generate structure convex with complete smooth in p type semiconductor layer
103, as shown in Figure 2；Since the raised structure of protective layer 104 is different, which is packaged
Shi Wufa is completely attached on p type semiconductor layer 103, the problem for causing heat dissipation uneven, and such structure is also be easy to cause
The structure of ambetti excessive height causes acceptance rate to decline, influences diode crystal particle so that easily causing glass impaired when encapsulation
Prouctiveness.
Summary of the invention
For above-mentioned missing, the main purpose of the present invention is to provide a kind of diode fabrications with ladder-type structure
Method forms a stair-stepping groove structure, it is ensured that follow-up process institute shape by etch process for several times on diode crystal particle
At protective layer decline, so as to subsequent encapsulation procedure, and promote the acceptance rate and efficiency of whole diode.
To reach above-mentioned purpose, the present invention provides a kind of diode manufacturing method with ladder-type structure, production
The step of method includes: to provide a chip body；First time Cutting Road oxide etch processing procedure and Cutting Road are carried out to the chip body
Etch process, to define the size of crystal grain；Pre-baked processing procedure is carried out to the chip body, and again in p-type after the chip body is cooling
Photoresist is coated on the top surface surface of semiconductor layer and carries out soft roasting operation；To the p type semiconductor layer top surface surface of the chip body
It is exposed processing procedure, development and fixing processing procedure and hard baking processing procedure, then the N+ type semiconductor layer bottom surface of the chip body is carried out
Coat photoresist and hard baking processing procedure；Second of Cutting Road oxide etch processing procedure is carried out to the chip body and Cutting Road etching is made
Journey；The photoresist on the chip body surface is removed, then is rinsed with water, that is, forms stairstepping groove structure.
As a further improvement of the present invention, wherein the chip body is partly led by a p type semiconductor layer, a N-type in a step
Body layer and a N+ type semiconductor layer are formed.
As further improvement of the invention, wherein Cutting Road oxide etch processing procedure is to utilize titanium dioxide in b step
Silicon etching liquid, i.e. hydrofluoric acid and ammonium fluoride are carried out with the ratio of 1:6, etching period between 15 ~ 20 minutes programs.
As further improvement of the invention, wherein in b step Cutting Road etch process be using nitric acid, hydrofluoric acid and
Glacial acetic acid is carried out with the ratio of 3:1:1, and etching period adjusts its time between 5 ~ 10 minutes, according to the situation that its acid subsides.
As further improvement of the invention, wherein second of Cutting Road oxide etch processing procedure is to utilize in step e
SiO 2 etch liquid, i.e. hydrofluoric acid and ammonium fluoride are carried out with the ratio of 1:6, etching period between 15 ~ 20 minutes programs.
As further improvement of the invention, wherein in step e Cutting Road etch process be using nitric acid, hydrofluoric acid and
Glacial acetic acid is carried out with the ratio of 3:1:1, and etching period adjusts its time between 5 ~ 10 minutes, according to the situation that its acid subsides.
As a further improvement of the present invention, the photoresist on the chip body surface is wherein removed in step e using sulfuric acid.
To enable above and other objects, features and advantages of the invention to be clearer and more comprehensible, preferred embodiment is cited below particularly,
And cooperate institute's accompanying drawings, it is described in detail below.
Detailed description of the invention
Fig. 1 is a schematic diagram of known grain structure.
Fig. 2 is another schematic diagram of known grain structure.
Fig. 3 is the first schematic diagram of production process structure of the invention.
Fig. 4 is the second schematic diagram of production process structure of the invention.
Fig. 5 is the third schematic diagram of production process structure of the invention.
Fig. 6 is the 4th schematic diagram of production process structure of the invention.
Fig. 7 is block flow diagram of the invention.
Symbol indicates in figure:
Symbol mark in known technology:
10 PN diode crystal particles；101 N+ type semiconductor layers；102 n type semiconductor layers；103 p type semiconductor layers；104 protections
Layer；105 cooling fins；
Symbol mark in the present invention:
1 n type semiconductor layer；10 chip bodies；2 p type semiconductor layers；21 grooves；3 N+ type semiconductor layers；4 insulation protections
Layer；S1 ~ S6 step.
Specific embodiment
It is production process structural schematic diagram of the invention refering to shown in Fig. 3 to Fig. 6.As shown in figure 3, two poles of the invention
Pipe grain structure mainly includes a n type semiconductor layer 1, and the n type semiconductor layer 1 is N-type crystal (N-type in the present embodiment
Wafer), one p type semiconductor layer 2 of storehouse in the one side of the n type semiconductor layer 1, is pasted on the another side of the n type semiconductor layer 1
Attached N+ type semiconductor layer 3, the p type semiconductor layer 2 and N+ type semiconductor layer 3 are to attach boron paper and phosphorus paper respectively in processing procedure
In on 1 two sides of n type semiconductor layer, using burn off processing procedure, pre- long-pending processing procedure, separation process, wet oxidation processing procedure and diffusion are impregnated
It is respectively formed the p type semiconductor layer 2 and N+ type semiconductor layer 3 after journey, forms it into a chip body 10.
Later, which enters back into etching and cutting processing procedure；Wherein, which first carries out etch process,
Photoresist (Photo Resist) is coated on the top surface surface of the p type semiconductor layer 2 after cooling down Deng the chip body 10 and is carried out
Soft roasting operation selects various sizes of light shield to be exposed processing procedure, at this after the exposure manufacture process according to product demand later
The processing procedure that the 2 top surface surface of p type semiconductor layer of chip body 10 is developed and is fixed finally carries out the hard baking system of chip body 10
Journey；Photoresist (Photo is coated on 3 bottom surface of N+ type semiconductor layer of chip body 10 after chip body 10 is cooling later
Resist), to form the protective effect for protecting 10 bottom surface of chip body, and hard baking processing procedure is then carried out again；The crystalline substance later
Sheet body 10 carries out first time Cutting Road oxide etch processing procedure, and the Cutting Road oxide etch processing procedure is to utilize in the present embodiment
SiO 2 etch liquid (BOE, Buffered Oxide Etch), i.e., hydrofluoric acid and ammonium fluoride are with the ratio of 1:6, etching period
It is carried out between 15 ~ 20 minutes programs, finally carries out first time Cutting Road etch process again to define the size of the crystal grain, such as
Shown in Fig. 4, the Cutting Road etch process is wet etching processing procedure in the present embodiment, which is to utilize nitric acid, hydrofluoric acid and ice
Acetic acid is carried out with the ratio of 3:1:1, and etching period adjusts its time between 5 ~ 10 minutes, according to the situation that its acid subsides.
Refering to shown in Fig. 5.After terminating first time Cutting Road etch process, which is subjected to stairstepping groove
Structure processing procedure；Wherein the chip body 10 repeats pre-baked processing procedure, and again in the p type semiconductor layer 2 after chip body 10 is cooling
Top surface surface on coat photoresist (Photo Resist) and carry out soft roasting operation, repeat exposure manufacture process, development and fixed
Shadow processing procedure and hard baking processing procedure, behind the top surface surface for completing p type semiconductor layer 2, then to 3 bottom surface of N+ type semiconductor layer of chip body 10
Surface carries out coating photoresist and hard baking processing procedure；Second of Cutting Road oxide etch processing procedure is carried out later, is equally to utilize two
It aoxidizes silicon etching liquid (BOE, Buffered Oxide Etch), i.e., hydrofluoric acid and ammonium fluoride are with the ratio of 1:6, etching period
15 ~ 20 minutes programs carry out, and carry out second of Cutting Road etch process again later, process conditions be in the present embodiment with
Nitric acid, hydrofluoric acid and glacial acetic acid are carried out with the ratio of 3:1:1, and etching period was between 5 ~ 10 minutes, according to the situation tune of its acid recession
Its whole time；After the etching to be done, the photoresist on 10 surface of chip body is first removed using sulfuric acid, is rinsed after completion with water,
Stairstepping groove structure is formed, as shown in figure 5, forming a groove 21 in 2 periphery of p type semiconductor layer.
Refering to shown in Fig. 6.After completing aforementioned secondary Cutting Road oxide etch processing procedure, then carry out glass protection burning
Tie processing procedure；Wherein after the leading pre-baked processing procedure of the chip body 10, protective glue is added in 2 top surface of p type semiconductor layer, which is
It is mixed by glass powder and photoresist, carries out soft roasting, exposure and development again later with after fixing processing procedure, finally entering sintering
Processing procedure so that protective glue formed insulating protective layer 4, as shown in fig. 6, and the insulating protective layer 4 because 2 periphery of p type semiconductor layer ditch
21 space of slot and generate sinking, make its insulating protective layer 4 structural portion can be higher than the p type semiconductor layer 2 top surface, so as to subsequent
Encapsulating structure combination.
It is to illustrate production process above-mentioned with block diagram as shown in fig.7, being block flow diagram of the invention.It provides
One chip body 10 (S1), the chip body 10 are that have a n type semiconductor layer 1, form a p-type in the one side of the n type semiconductor layer 1
Semiconductor layer 2 forms a N+ type semiconductor layer 3 on the another side of the n type semiconductor layer 1；First is carried out to the chip body 10
Secondary Cutting Road oxide etch processing procedure and Cutting Road etch process, to define the size (S2) of crystal grain；Chip body 10 is carried out
Pre-baked processing procedure, and photoresist (Photo is coated on the top surface surface of the p type semiconductor layer 2 again after chip body 10 is cooling
Resist) and soft roasting operation (S3) is carried out；To the 2 top surface surface of p type semiconductor layer of chip body 10 be exposed processing procedure, development with
It is fixed processing procedure and hard baking processing procedure, then 3 bottom surface of N+ type semiconductor layer of chip body 10 is carried out coating photoresist and hard baking system
Journey (S4)；Second of Cutting Road oxide etch processing procedure and Cutting Road etch process (S5) are carried out to chip body 10；Remove chip
The photoresist on 10 surface of body is rinsed again with water, that is, forms stairstepping groove structure (S6).
Embodiments described above, only preferable embodiment, cannot be limit the scope of implementation of the present invention with this,
If all should belong to patent of the invention according to equivalent change or modification made by scope of the present invention patent and description and contain
Lid range.
Claims (7)
1. a kind of diode manufacturing method with ladder-type structure, which is characterized in that step includes:
A., one chip body is provided；
B. first time Cutting Road oxide etch processing procedure and Cutting Road etch process are carried out to the chip body, to define crystal grain
Size；
C. pre-baked processing procedure is carried out to the chip body, and again on the top surface surface of p type semiconductor layer after the chip body is cooling
On coat photoresist and carry out soft roasting operation；
D. processing procedure, development and fixing processing procedure and hard baking are exposed to the p type semiconductor layer top surface surface of the chip body
Processing procedure, then the N+ type semiconductor layer bottom surface of the chip body is carried out coating photoresist and hard baking processing procedure；
E. second of Cutting Road oxide etch processing procedure and Cutting Road etch process are carried out to the chip body；
F. the photoresist for removing the chip body surface is rinsed again with water, forms stairstepping groove structure.
2. as described in claim 1 with the diode manufacturing method of ladder-type structure, which is characterized in that wherein in a step
The chip body is made of a p type semiconductor layer, a n type semiconductor layer and a N+ type semiconductor layer.
3. as described in claim 1 with the diode manufacturing method of ladder-type structure, which is characterized in that wherein in b step
The Cutting Road oxide etch processing procedure is using SiO 2 etch liquid, i.e., hydrofluoric acid and ammonium fluoride are with the ratio of 1:6, etching
Time between 15 ~ 20 minutes program carry out.
4. as described in claim 1 with the diode manufacturing method of ladder-type structure, which is characterized in that wherein in b step
The Cutting Road etch process is to be carried out using nitric acid, hydrofluoric acid and glacial acetic acid with the ratio of 3:1:1, and etching period is between 5 ~ 10
Minute.
5. as described in claim 1 with the diode manufacturing method of ladder-type structure, which is characterized in that wherein in step e
Second of Cutting Road oxide etch processing procedure is using SiO 2 etch liquid, i.e., hydrofluoric acid and ammonium fluoride are with the ratio of 1:6
Example, etching period were carried out between 15 ~ 20 minutes programs.
6. as described in claim 1 with the diode manufacturing method of ladder-type structure, which is characterized in that wherein in step e
The Cutting Road etch process is to be carried out using nitric acid, hydrofluoric acid and glacial acetic acid with the ratio of 3:1:1, and etching period is between 5 ~ 10
Minute.
7. as described in claim 1 with the diode manufacturing method of ladder-type structure, which is characterized in that wherein in step e
The photoresist on the chip body surface is removed using sulfuric acid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710373920.1A CN108962747A (en) | 2017-05-24 | 2017-05-24 | Diode manufacturing method with ladder-type structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710373920.1A CN108962747A (en) | 2017-05-24 | 2017-05-24 | Diode manufacturing method with ladder-type structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108962747A true CN108962747A (en) | 2018-12-07 |
Family
ID=64493831
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710373920.1A Pending CN108962747A (en) | 2017-05-24 | 2017-05-24 | Diode manufacturing method with ladder-type structure |
Country Status (1)
| Country | Link |
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| CN (1) | CN108962747A (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5977605A (en) * | 1995-08-30 | 1999-11-02 | Asea Brown Boveri Ab | SiC Semiconductor device comprising a pn Junction with a voltage absorbing edge |
| CN201383498Y (en) * | 2009-03-03 | 2010-01-13 | 百圳君耀电子（深圳）有限公司 | Semiconductor diode chip |
| CN101982872A (en) * | 2010-10-30 | 2011-03-02 | 强茂电子(无锡)有限公司 | Manufacturing method of grooved diode chip |
| CN102543722A (en) * | 2011-12-26 | 2012-07-04 | 天津中环半导体股份有限公司 | High-voltage transient voltage suppressor chip and production process |
| CN104008970A (en) * | 2014-06-17 | 2014-08-27 | 安徽芯旭半导体有限公司 | Glassivation diode chip and manufacturing method thereof |
| CN104201102A (en) * | 2014-08-28 | 2014-12-10 | 苏州启澜功率电子有限公司 | Fast recovery diode FRD chip and production process for same |
| CN104616978A (en) * | 2014-12-31 | 2015-05-13 | 国家电网公司 | Silicon-carbide power device terminal structure manufacturing method |
| CN104952909A (en) * | 2014-09-03 | 2015-09-30 | 安徽省祁门县黄山电器有限责任公司 | Junction terminal structure of diode chip |
-
2017
- 2017-05-24 CN CN201710373920.1A patent/CN108962747A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5977605A (en) * | 1995-08-30 | 1999-11-02 | Asea Brown Boveri Ab | SiC Semiconductor device comprising a pn Junction with a voltage absorbing edge |
| CN201383498Y (en) * | 2009-03-03 | 2010-01-13 | 百圳君耀电子（深圳）有限公司 | Semiconductor diode chip |
| CN101982872A (en) * | 2010-10-30 | 2011-03-02 | 强茂电子(无锡)有限公司 | Manufacturing method of grooved diode chip |
| CN102543722A (en) * | 2011-12-26 | 2012-07-04 | 天津中环半导体股份有限公司 | High-voltage transient voltage suppressor chip and production process |
| CN104008970A (en) * | 2014-06-17 | 2014-08-27 | 安徽芯旭半导体有限公司 | Glassivation diode chip and manufacturing method thereof |
| CN104201102A (en) * | 2014-08-28 | 2014-12-10 | 苏州启澜功率电子有限公司 | Fast recovery diode FRD chip and production process for same |
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Application publication date: 20181207 |