CN105655450A - Passivation layer deposition method of high-voltage LED chip - Google Patents
Passivation layer deposition method of high-voltage LED chip Download PDFInfo
- Publication number
- CN105655450A CN105655450A CN201410639894.9A CN201410639894A CN105655450A CN 105655450 A CN105655450 A CN 105655450A CN 201410639894 A CN201410639894 A CN 201410639894A CN 105655450 A CN105655450 A CN 105655450A
- Authority
- CN
- China
- Prior art keywords
- passivation layer
- led chip
- layer deposition
- sio
- voltage led
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention provides a passivation layer deposition method of a high-voltage LED chip. The method comprises the following steps: a passivation layer deposition step, i.e., depositing an SiO2 passivation layer on the whole surface of an LED chip obtained after an isolation groove etching process is completed; a passivation layer removing step, i.e., removing the SiO2 passivation layer of other areas apart from a preset non-corrosion area, wherein the non-corrosion area comprises the side wall of an isolation groove and an area, adjacent to the side wall, of the bottom surface of the isolation groove; and alternatively performing the passivation layer deposition step and the passivation layer removing step for multiple times, and enabling the width of the non-corrosion area on a profile to be successively increased as the alternating frequency increases. According to the passivation layer deposition method of the high-voltage LED chip, provided by the invention, the inclination angle of the side wall of the chip can be reduced, bridge disconnection can be prevented during vapor plating of an electrode connection bridge, and accordingly, the yield rate of the high-voltage LED chip can be improved.
Description
Technical field
The present invention relates to semiconductor processing technology field, specifically, it relates to a kind of high-voltage LED core
The passivation layer deposition method of sheet.
Background technology
Photodiode (LightEmittingDiode, LED) just progressively become the main flow lighting source in traditional lighting market owing to having the advantages such as specular removal, low power consuming, long lifetime, nontoxic green, obtain more and more many application in fields such as Landscape Lighting, road lighting, interior lightings. High-voltage LED (High-VoltageLED) becomes the new breakthrough of lighting field gradually with advantages such as its small current driving, succinct design of drive circuit. From in a broad sense, high-voltage LED refers to and the epitaxial film of a large size chip (being generally 45*45mil) is divided into multiple independent core grain by etching the mode of deep trench, and by LED chip that each core grain is connected and formed by the mode of electrode evaporation cross structure in the way of connecting, owing to the voltage of single core grain is 3V under the driving of 20mA electric current, therefore, the operating voltage of the LED chip obtained after series connection can reach 45-51V, therefore is called high voltage LED chip.
Fig. 1 is the section of structure of high voltage LED chip. As shown in Figure 1, the main Making programme of high voltage LED chip is as follows:
Adopt MOCVD technique to make epitaxial layer of gallium nitride on substrate 1, and mix up technique accordingly and from bottom to top obtain N-type GaN layer 2, Multiple Quantum Well district 3 and P type GaN layer 4 successively;
ICP etching technics is adopted to start etching N type GaN layer to produce N electrode platform from P type GaN layer 4; P type GaN layer 4 and N-type GaN layer 2 carry out ITO technique respectively and produces P electrode and N electrode;
ICP technique is adopted often to etch isolation channel between adjacent two chips;
Deposition SiO2Passivation layer 6;
Electrode evaporation cross structure 7, is connected with N electrode with the P electrode by adjacent two chips.
In actual production process, the situation of bridge cut-off often occurs during electrode evaporation cross structure, thus affect the good rate of high voltage LED chip, the reason producing this situation is: after completing the etching technics of above-mentioned isolation channel, the ditch non-intercommunicating cells lateral wall obtained is more steep, this makes in the process of electrode evaporation cross structure 7, and Electrode connection bridge 7 " cannot climb " highly slightly high P electrode.
Summary of the invention
The present invention is intended to one of technical problem at least solving existence in prior art, propose a kind of passivation layer deposition method of high voltage LED chip, it can reduce the angle of inclination of chip sidewall, such that it is able to avoid, during electrode evaporation cross structure, bridge cut-off occurs, and then the good rate of high voltage LED chip can be improved.
For realizing the object of the present invention and provide a kind of passivation layer deposition method of high voltage LED chip, it comprises the following steps:
Passivation layer deposition step, the whole surface deposition one layer of SiO of the LED chip obtained after completing isolation channel etching technics2Passivation layer;
Passivation layer removal step, removes the described SiO in all the other regions except default non-corrosive region2Passivation layer; Described non-corrosive region is the sidewall of described isolation channel, and the region of the contiguous described sidewall in the bottom surface of described isolation channel;
Repeatedly, and the increase with alternate frequency, makes the width of described non-corrosive region on its section successively increase for the described passivation layer deposition step that hockets and described passivation layer removal step.
Preferably, described passivation layer removal step is further comprising the steps:
At described SiO2Passivation layer makes one layer of mask and covers described default non-corrosive region;
The described SiO in all the other regions of corrosion except described default non-corrosive region2Passivation layer, and described SiO2The mask in the non-corrosive region preset on passivation layer.
Preferably, described passivation layer removal step adopts the mode of wet etching.
Preferably, described mask comprises photoresist material.
Preferably, the SiO formed on the sidewall of described isolation channel2When the vertical height of passivation layer exceedes the height of gan N electrode, terminate described passivation layer deposition step and described passivation layer removal step.
The present invention has following useful effect:
The passivation layer deposition method of high voltage LED chip provided by the invention, it carries out passivation layer deposition step and passivation layer removal step by alternate cycles, that is: the whole surface deposition one layer of SiO of the LED chip first obtained after completing isolation channel etching technics2Passivation layer; Then the SiO in all the other regions except default non-corrosive region is removed2Passivation layer. And, by the increase with cycle index, the width of non-corrosive region on its section is successively increased, it is possible to make SiO2Passivation layer successively reduces towards the direction away from sidewall and forms one " step ", finally forms the SiO with certain slope (predetermined inclination angle) on the sidewall of isolation channel2Passivation layer, such that it is able to reduce the angle of inclination of chip sidewall, and then can avoid bridge cut-off occur during electrode evaporation cross structure, it is to increase the good rate of high voltage LED chip.
Accompanying drawing explanation
Fig. 1 is the section of structure of high voltage LED chip;
Fig. 2 is the FB(flow block) of the passivation layer deposition method of high voltage LED chip provided by the invention;
Fig. 3 A has been the sectional view of the LED chip obtained after isolation channel etching technics;
Fig. 3 B has been the sectional view of the LED chip of first time passivation layer deposition step acquisition;
Fig. 3 C has been the sectional view of the LED chip that the mask fabrication in first time passivation layer removal step obtains;
Fig. 3 D has been the sectional view that the passivation layer in first time passivation layer removal step removes the LED chip obtained;
Fig. 3 E has been the sectional view of the LED chip that second time passivation layer deposition step obtains;
Fig. 3 F has been the sectional view of the LED chip that the mask fabrication in second time passivation layer removal step obtains;
Fig. 3 G has been the sectional view that the passivation layer in second time passivation layer removal step removes the LED chip obtained;
Fig. 3 H is the sectional view of the LED chip adopting the passivation layer deposition method of high voltage LED chip provided by the invention finally to obtain; And
Fig. 4 has been the sectional view of the LED chip that electrode evaporation cross structure obtains.
Embodiment
For making the technician of this area understand the technical scheme of the present invention better, below in conjunction with accompanying drawing, the isolation channel lithographic method of galliumnitride base LED chip provided by the invention is described in detail.
The passivation layer deposition method of high voltage LED chip provided by the invention is after the etching technics completing isolation channel, and carries out before carrying out the evaporation process of Electrode connection bridge, in order to the surface deposition SiO at LED chip2Passivation layer. Owing to, after the etching technics completing isolation channel, the ditch non-intercommunicating cells lateral wall of acquisition is more steep, this makes in the process of electrode evaporation cross structure, and Electrode connection bridge " cannot climb " highly slightly high P electrode, thus the situation of bridge cut-off often occurs. The application is to deposition SiO for this problem2The improvement that the step of passivation layer carries out.
Fig. 2 is the FB(flow block) of the passivation layer deposition method of high voltage LED chip provided by the invention. Referring to Fig. 2, this passivation layer deposition method comprises the following steps:
Passivation layer deposition step S1, the whole surface deposition one layer of SiO of the LED chip obtained after completing isolation channel etching technics2Passivation layer;
Passivation layer removal step S2, removes the SiO in all the other regions except default non-corrosive region2Passivation layer; This non-corrosive region is the sidewall of isolation channel and the region of the bottom surface adjacent sidewall of isolation channel;
Repeatedly, and the increase with alternate frequency, makes the width of non-corrosive region on its section successively increase for step S3, the passivation layer deposition that hockets step and passivation layer removal step.
By adopting above-mentioned passivation layer deposition method, it is possible to form one layer of SiO with certain slope on the sidewall of isolation channel2Passivation layer, that is, this SiO2Passivation layer successively reduces towards the direction away from sidewall and forms one " step ", such that it is able to reduce the angle of inclination of chip sidewall, and then can avoid bridge cut-off occur during electrode evaporation cross structure, it is to increase the good rate of high voltage LED chip.
Below in conjunction with Fig. 3 A-Fig. 3 H, the embodiment of passivation layer deposition method provided by the invention is described in detail.
As shown in Figure 3A, for completing the sectional view of LED chip obtained after isolation channel etching technics. LED chip from bottom to top comprises substrate 1, N-type GaN layer 2 and P type GaN layer 3 successively; Further, often between adjacent two chips, there is isolation channel 4. The surface of this isolation channel 4 is made up of sidewall 41 and bottom surface 42, and as seen from the figure, after the etching technics completing isolation channel, sidewall 41 is relatively steep, that is, it is bigger relative to the angle of inclination A of bottom surface 42.
Carrying out first time passivation layer deposition step after completing isolation channel etching technics, as shown in Figure 3 B, after completing first time passivation layer deposition step, the whole surface deposition at LED chip has one layer of SiO2Passivation layer 51.
Carrying out first time passivation layer removal step, this step is further comprising the steps:
As shown in Figure 3 C, first, at SiO2On passivation layer 51, and cover preset non-corrosive region make one layer of mask, in order to protect the SiO in non-corrosive region2Passivation layer 51 is not corroded. This non-corrosive region is sidewall 41 and the region of bottom surface 42 adjacent sidewall 41, thus this mask by the first part 61 covered on sidewall 41 and covers on bottom surface 42 and the second section 62 of adjacent sidewall 41 forms.It should be readily understood that the second section 62 of mask only covers the region, edge of bottom surface 42 adjacent sidewall 41, and do not cover the region intermediate 60 of bottom surface 42, and after the making completing mask, the spacing of this region intermediate 60 is D1.
As shown in Figure 3 D, then, corrode the SiO in all the other regions except default non-corrosive region2Passivation layer, thus after removing mask, obtain the first layer SiO in the region only covering sidewall 41 and bottom surface 42 adjacent sidewall 412Passivation layer 51.
Carry out second time passivation layer deposition step, as shown in FIGURE 3 E, after completing second time passivation layer deposition step, at the first layer SiO2The surface deposition of passivation layer 51 and all the other LED chips has second layer SiO2Passivation layer 52.
Carrying out second time passivation layer removal step, this step comprises the following steps equally:
As illustrated in Figure 3 F, first, at SiO2Passivation layer 52 makes one layer of mask, this mask covers the non-corrosive region preset, this non-corrosive region is sidewall 41 and the region of bottom surface 42 adjacent sidewall 41, thus this mask by the first part 61 covered on sidewall 41 and covers on bottom surface 42 and the second section 62 of adjacent sidewall 41 forms. With above-mentioned first time passivation layer removal step the difference is that: in second time passivation layer removal step, make the width increase of non-corrosive region on its section, thus the width of the second section 62 of mask increases, and the spacing of the region intermediate 60 ' of the bottom surface 42 not covered by mask is D2, and D2 is less than D1.
As shown in Figure 3 G, then, corrode the SiO in all the other regions except default non-corrosive region2Passivation layer, thus removing after mask, has passivation layers on the region of sidewall 41 and bottom surface 42 adjacent sidewall 41, is respectively: the first layer SiO2Passivation layer 51 and second layer SiO2Passivation layer 52, and second layer SiO2Passivation layer 52 is relative to the first layer SiO2Passivation layer 51 reduces towards the direction away from sidewall 41 and forms one " step ".
Analogize with this, as shown in figure 3h, by hocketing above-mentioned passivation layer deposition step and passivation layer removal step repeatedly, and the increase with alternate frequency, the width of non-corrosive region on its section is successively increased, finally can form the SiO with certain slope on sidewall 412Passivation layer 5, this SiO2Passivation layer 5 is B relative to the angle of inclination of bottom surface 42, and B is less than the angle of inclination A of sidewall 41, such that it is able to realize the angle of inclination reducing chip sidewall, and then can avoid bridge cut-off occur during electrode evaporation cross structure, it is to increase the good rate of high voltage LED chip.
Preferably, above-mentioned passivation layer removal step adopts the mode of wet etching.
Preferably, above-mentioned mask comprises photoresist material.
Preferably, the SiO formed on the sidewall of isolation channel2When the vertical height of passivation layer exceedes the height of gan N electrode, terminate above-mentioned passivation layer deposition step and passivation layer removal step, this is because: as shown in Figure 4, for completing the sectional view of the LED chip that electrode evaporation cross structure obtains. P electrode is slightly high relative to the height of N electrode, by making SiO2The vertical height of passivation layer exceedes the height of gan N electrode, it is possible to make SiO2Passivation layer can form slope corresponding on the sidewall of P electrode, such that it is able to ensure that Electrode connection bridge 7 " climbing " is to highly slightly high P electrode.
It should be noted that, in the present embodiment, passivation layer removal step protects the SiO in non-corrosive region by making mask2Passivation layer is not corroded, such that it is able to realize optionally corroding.But the present invention is not limited thereto, in actual applications, it is possible to otherwise carry out selective corrosion or etching, as long as can realize only removing SiO2On passivation layer except preset non-corrosive region except all the other regions.
It should be appreciated that the illustrative embodiments that above enforcement mode is only used to the principle of the present invention is described and adopts, but the present invention is not limited thereto. , it is possible to make various modification and improvement, for those skilled in the art, without departing from the spirit and substance in the present invention these modification and improvement are also considered as protection scope of the present invention.
Claims (5)
1. the passivation layer deposition method of a high voltage LED chip, it is characterised in that, comprise the following steps:
Passivation layer deposition step, the whole surface deposition one layer of SiO of the LED chip obtained after completing isolation channel etching technics2Passivation layer;
Passivation layer removal step, removes the described SiO in all the other regions except default non-corrosive region2Passivation layer; Described non-corrosive region is the sidewall of described isolation channel, and the region of the contiguous described sidewall in the bottom surface of described isolation channel;
Repeatedly, and the increase with alternate frequency, makes the width of described non-corrosive region on its section successively increase for the described passivation layer deposition step that hockets and described passivation layer removal step.
2. the passivation layer deposition method of high voltage LED chip according to claim 1, it is characterised in that, described passivation layer removal step is further comprising the steps:
At described SiO2Passivation layer makes one layer of mask and covers described default non-corrosive region;
The described SiO in all the other regions of corrosion except described default non-corrosive region2Passivation layer, and described SiO2The mask in the non-corrosive region preset on passivation layer.
3. the passivation layer deposition method of high voltage LED chip according to claim 1 and 2, it is characterised in that, described passivation layer removal step adopts the mode of wet etching.
4. the passivation layer deposition method of high voltage LED chip according to claim 2, it is characterised in that, described mask comprises photoresist material.
5. the passivation layer deposition method of high voltage LED chip according to claim 1, it is characterised in that, the SiO formed on the sidewall of described isolation channel2When the vertical height of passivation layer exceedes the height of gan N electrode, terminate described passivation layer deposition step and described passivation layer removal step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410639894.9A CN105655450B (en) | 2014-11-13 | 2014-11-13 | The passivation layer deposition method of high voltage LED chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410639894.9A CN105655450B (en) | 2014-11-13 | 2014-11-13 | The passivation layer deposition method of high voltage LED chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105655450A true CN105655450A (en) | 2016-06-08 |
| CN105655450B CN105655450B (en) | 2019-01-18 |
Family
ID=56478698
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410639894.9A Active CN105655450B (en) | 2014-11-13 | 2014-11-13 | The passivation layer deposition method of high voltage LED chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105655450B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109786419A (en) * | 2018-12-28 | 2019-05-21 | 华灿光电（浙江）有限公司 | A kind of high pressure light-emitting diode chip and preparation method thereof |
| CN109817779A (en) * | 2019-02-02 | 2019-05-28 | 厦门乾照光电股份有限公司 | A kind of high voltage LED chip structure and its manufacturing method |
| US20200251616A1 (en) * | 2019-02-02 | 2020-08-06 | Xiamen Changelight Co. Ltd. | High voltage light-emitting diode and method of producing the same |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009302314A (en) * | 2008-06-13 | 2009-12-24 | Rohm Co Ltd | GaN-BASED SEMICONDUCTOR DEVICE |
| CN102176498A (en) * | 2011-03-22 | 2011-09-07 | 湘能华磊光电股份有限公司 | Manufacturing method of LED chip |
| CN102983147A (en) * | 2012-09-24 | 2013-03-20 | 杭州士兰明芯科技有限公司 | Light emitting diode chip and production method thereof |
| CN103236474A (en) * | 2013-04-09 | 2013-08-07 | 中国科学院半导体研究所 | Method for manufacturing optionally cut high-voltage LED devices |
| CN203134800U (en) * | 2013-03-07 | 2013-08-14 | 南通同方半导体有限公司 | Step type light emitting diode raising high-voltage LED process yield |
| US20130214308A1 (en) * | 2012-02-17 | 2013-08-22 | Samsung Electronics Co., Ltd. | Semiconductor light emitting device, light emitting module, and illumination apparatus |
| WO2013131449A1 (en) * | 2012-03-05 | 2013-09-12 | 映瑞光电科技(上海)有限公司 | Methods for manufacturing isolated deep trench and high-voltage led chip |
| TW201347141A (en) * | 2012-05-04 | 2013-11-16 | Chi Mei Lighting Tech Corp | Light-emitting diode structure and method for manufacturing the same |
| CN103762288A (en) * | 2014-01-23 | 2014-04-30 | 同辉电子科技股份有限公司 | Reflective arc type isolation groove for high-voltage LED |
-
2014
- 2014-11-13 CN CN201410639894.9A patent/CN105655450B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009302314A (en) * | 2008-06-13 | 2009-12-24 | Rohm Co Ltd | GaN-BASED SEMICONDUCTOR DEVICE |
| CN102176498A (en) * | 2011-03-22 | 2011-09-07 | 湘能华磊光电股份有限公司 | Manufacturing method of LED chip |
| US20130214308A1 (en) * | 2012-02-17 | 2013-08-22 | Samsung Electronics Co., Ltd. | Semiconductor light emitting device, light emitting module, and illumination apparatus |
| WO2013131449A1 (en) * | 2012-03-05 | 2013-09-12 | 映瑞光电科技(上海)有限公司 | Methods for manufacturing isolated deep trench and high-voltage led chip |
| TW201347141A (en) * | 2012-05-04 | 2013-11-16 | Chi Mei Lighting Tech Corp | Light-emitting diode structure and method for manufacturing the same |
| CN102983147A (en) * | 2012-09-24 | 2013-03-20 | 杭州士兰明芯科技有限公司 | Light emitting diode chip and production method thereof |
| CN203134800U (en) * | 2013-03-07 | 2013-08-14 | 南通同方半导体有限公司 | Step type light emitting diode raising high-voltage LED process yield |
| CN103236474A (en) * | 2013-04-09 | 2013-08-07 | 中国科学院半导体研究所 | Method for manufacturing optionally cut high-voltage LED devices |
| CN103762288A (en) * | 2014-01-23 | 2014-04-30 | 同辉电子科技股份有限公司 | Reflective arc type isolation groove for high-voltage LED |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109786419A (en) * | 2018-12-28 | 2019-05-21 | 华灿光电（浙江）有限公司 | A kind of high pressure light-emitting diode chip and preparation method thereof |
| CN109817779A (en) * | 2019-02-02 | 2019-05-28 | 厦门乾照光电股份有限公司 | A kind of high voltage LED chip structure and its manufacturing method |
| US20200251616A1 (en) * | 2019-02-02 | 2020-08-06 | Xiamen Changelight Co. Ltd. | High voltage light-emitting diode and method of producing the same |
| CN109817779B (en) * | 2019-02-02 | 2020-08-14 | 厦门乾照光电股份有限公司 | Manufacturing method of high-voltage LED chip structure |
| US11695098B2 (en) * | 2019-02-02 | 2023-07-04 | Xiamen Changelight Co., Ltd. | High voltage light-emitting diode and method of producing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105655450B (en) | 2019-01-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9082891B2 (en) | Methods for manufacturing isolated deep trench and high-voltage LED chip | |
| CN104779293B (en) | The manufacturing method of groove-shaped super-junction device | |
| US9059012B2 (en) | Epitaxial layer wafer having void for separating growth substrate therefrom and semiconductor device fabricated using the same | |
| US20070042520A1 (en) | Method of manufacturing vertical GaN-based light emitting diode | |
| TWI398022B (en) | Separation method of epitaxial substrate of photovoltaic element | |
| CN104681674A (en) | GaN-based high-voltage direct-current LED insulation isolating process | |
| KR101186684B1 (en) | Light emitting diode and method of fabricating the same | |
| JP2006253172A (en) | Semiconductor light emitting element, semiconductor light emitting apparatus and method of manufacturing semiconductor light emitting element | |
| CN105655450A (en) | Passivation layer deposition method of high-voltage LED chip | |
| KR102522529B1 (en) | Light emitting diode display device | |
| CN103199053B (en) | The formation method of groove and semiconductor structure | |
| CN107611235A (en) | A kind of method for lifting high voltage LED chip luminous efficiency | |
| CN103681315A (en) | Method for forming buried layer | |
| KR20130107537A (en) | Light emitting device and method of manufacturing the same | |
| CN106098544A (en) | The method improving groove type double-layer grid MOS dielectric layer pattern | |
| CN107946175B (en) | Filling method for groove epitaxy | |
| CN102938436B (en) | Isolation filling manufacture method in GaN-based high voltage light-emitting diode (LED) manufacture process | |
| CN103413875A (en) | PN step of LED (Light Emitting Diode) chip, LED chip and manufacturing method of PN step | |
| CN107731733B (en) | Filling method for groove epitaxy | |
| TWI497756B (en) | Led chip manufacturing method | |
| KR101843154B1 (en) | Method for separating epitaxial growth layer from growth substrate | |
| CN102683533B (en) | Light emitting diode and manufacturing method thereof | |
| CN102969412B (en) | Integrated LED chip and preparation method thereof | |
| TWI455255B (en) | Patterned substrate structure, manufacturing method thereof and light-emitting device having the same | |
| CN112635399A (en) | Preparation method of gallium nitride power device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 100176 No. 8 Wenchang Avenue, Beijing economic and Technological Development Zone Applicant after: Beijing North China microelectronics equipment Co Ltd Address before: 100176 Beijing economic and Technological Development Zone, Wenchang Road, No. 8, No. Applicant before: Beifang Microelectronic Base Equipment Proces Research Center Co., Ltd., Beijing |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |