CN108959140A - TTP and AFDX adapter based on MPC555 and AN8202 - Google Patents
TTP and AFDX adapter based on MPC555 and AN8202 Download PDFInfo
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- CN108959140A CN108959140A CN201710389148.2A CN201710389148A CN108959140A CN 108959140 A CN108959140 A CN 108959140A CN 201710389148 A CN201710389148 A CN 201710389148A CN 108959140 A CN108959140 A CN 108959140A
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- Prior art keywords
- mpc555
- ttp
- afdx
- fault
- tolerant
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/08—Protocols for interworking; Protocol conversion
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40267—Bus for use in transportation systems
- H04L2012/4028—Bus for use in transportation systems the transportation system being an aircraft
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Hardware Redundancy (AREA)
Abstract
The present invention relates to a kind of TTP based on MPC555 and AN8202 and AFDX adapter, on the basis of analyzing typical event/time trigger data/address bus and existing airborne equipment interface requirements, the data transformation interface of design studies airborne-bus TTP and backbone network AFDX.Microcontroller MPC555 execution speed with higher, perfect system protection function, stronger I/O function and data-handling capacity, suitable for the higher occasion of reliability requirement, the present invention proposes that a kind of TTP based on MPC555 and AS8202 is designed with AFDX conversion interface circuit, study the TTP protocol controller General layout Plan based on MPC555, analyse in depth the clock synchronous fault-tolerant of time trigger, the crucial fault tolerant mechanism such as malfunctioning node detection and malfunctioning node recovery and principle, study fault-tolerant strategy group membership's agreement GMP based on time trigger, for the excessive continuous fault of appearance, the irreclaimable problem of failure, the present invention proposes a kind of improved fault-tolerant strategy, the node for transient fault occur is set to return to system in finite time, improve the appearance of system Wrong ability.
Description
One, technical field
This patent is related to a kind of TTP based on MPC555 and AS8202 and AFDX adapter, belongs to electronic circuit field.
Two, background technique
Airborne equipment is distributed in full machine different zones, and each region has one or more remote signal collector, if
Standby signal accesses backbone network by it, and regional signal collector is completed airborne system/device signal and acquired and itself and backbone network
Adaptation and interaction.The essence of signal picker is one or more view adaptable interface circuit, airborne is set one or more kinds of
Standby communication bus protocol mode, is converted into backbone protocol mode, accesses backbone network.The design of interface circuit must consider to be adapted to energy
Power independently uses and works ability i.e. independently of other functions of airborne equipment, can be used for a variety of future predictable machines
Carry the ability of equipment, it is also desirable to consider integration capability, i.e., the adaptable interface is used for system on all kinds of machines convenient for system integrator,
Such as: power-supply system, fuel system, flight control system.
Three, summary of the invention
1, goal of the invention: the Hughes Aircraft Company of foreign well-known, Texas instrument company, Smith's space flight company etc. are more
Manufacturer of family produces the various Airborne Terminal interfaces of aviation electronics, but its interface kernel technology blocks China, and the country is being ground
When making big aircraft, the Airborne Terminal interface of use passes through outsourcing mostly, by Hansen company if the communication gate of TTP and AFDX
It provides, so developing TTP with independent intellectual property rights and AFDX adapter seems particularly necessary.
2, technical solution: in order to achieve the above object of the invention, the invention proposes a kind of based on MPC555's and AN8202
The design of TTP and AFDX adapter, the adapter mainly include AFDX telecommunication circuit, MPC555 operating circuit and TTP/C communication
Circuit three parts are constituted.Wherein MPC555 is the master controller of circuit, is mainly used for realizing the control of TTP fault-tolerant strategy and TTP
With the conversion of AFDX protocol data.
TTP and AFDX adapter proposed by the invention designs the MPC555 based on Freescale company, the processing unit
It has been internally integrated Power PC core, system interface unit and the Communications Processor Module of insertion, the exploitation suitable for communication products.
TTP/C communication circuit portion uses dedicated TTP controller chip AS8202NF, and protocol processes core passes through host C NI interface and master
Controller MPC555 is connected.
Time trigger data of this patent analysis and research based on MPC555 are transmitted, distributed clock is synchronous and fault-tolerant, member
The software design approach of the key function module of the TTP/C protocol controller such as relationship consistency, and propose a kind of improved composition
Member's agreement tolerant fail algorithm, when solving node continuous fault number greater than certain amount, clock cannot be synchronized, and malfunctioning node can not be again
The problem of incorporating TTP network；
To work normally safety adapter of the invention, usually also need to design some control circuits, clock circuit, guarantor
The auxiliary circuits such as protection circuit.
3, the utility model has the advantages that synthesis is described above, the TTP of the invention based on MPC555 and AN8202 has with AFDX adapter
Following features: the circuit realizes the conversion between TTP agreement and AFDX agreement；The adapter software proposes one kind when designing
Improve fault-tolerant strategy, solve node continuous fault number it is excessive when, the irreclaimable problem of failure,
Four, Detailed description of the invention
Attached drawing 1 is TTP and AFDX adapter block diagram based on MPC555 and AN8202
Attached drawing 2 is AS8202NF and MPC555 connection schematic diagram
Attached drawing 3 is DM9000 and MPC555 connection schematic diagram
Attached drawing 4 is TTP and AFDX protocol conversion module flow chart
Attached drawing 5 is integrity detection flow chart
Attached drawing 6 is Redundancy Management flow chart
Attached drawing 7 is the fault-tolerant flow chart of group membership's agreement
Attached drawing 8 is to improve the fault-tolerant flow chart of group membership's agreement
Five, specific embodiment
This patent designs a kind of TTP based on MPC555 and AN8202 and AFDX adapter, during designing and developing,
Deeply understand bus protocol content, it is most important to grasp processing unit, protocol controller development approach.Wherein, processing unit selects
The MPC555 of Freescale company is selected, which has been internally integrated Power PC core, system interface unit and the communication of insertion
Processing module, the exploitation suitable for communication products.TTP/C protocol controller is based on special chip AS8202NF, AFDX interface
End then uses ethernet mac controller DM9000, the port drivers under any system of portable.Fig. 1, which gives, to be based on
MPC555 designs the interface circuit of TTP/C bus and AFDX bus, including AFDX telecommunication circuit, MPC555 operating circuit and TTP/
C telecommunication circuit three parts are constituted.Wherein MPC555 is the master controller of circuit, is mainly used for realizing the transmitting-receiving control of AFDX signal
What system, TTP/C protocol core logic, this patent proposed improves fault-tolerant strategy and the conversion of TTP and AFDX protocol data.
The interface circuit of AS8202NF and MPC555, which is mainly responsible for, changes the circulation of TTP formatted data into electric signal and by double
Twisted wire transmission.MPC555 operating circuit mainly completes the self-starting of MPC555, and AFDX network protocol handles and to TTP agreement control
The control of device processed.MPC555 and DM9000 chip interface circuit is completed data of the data between MPC555 and AFDX bus and is passed
Data in MPC555 are converted to AFDX data format by defeated, and are sent to bus and are communicated with avionics system.
The connection of AS8202NF and MPC555 is as shown in Fig. 2, host interface CNI for connect master controller with
AS8202NF, the main signal of the interface have: 12 bit address signal A [11:0], 16 data-signal D [15:0], controller pieces
Enabled CEB, the enabled OEB of controller output, controller is selected to write enabled WEB, controller ready signal READYB, interrupt signal
INTB, host clock input RAM_CLK_TESTSE and host clock enable USE_RAM_CLK, and these signals asynchronous can read/
The two-port RAM of write access AS8202NF, master clock (CLK0) does not establish the influence with the duration.Since MPC555 is used
Be big end data format, i.e. high byte is located at low address, and AS8202NF using small end data format and uses double word
The mode of section executes access, therefore the A0-A11 of AS8202NF is connected with the ADDR11-ADDR0 of MPC555 respectively, equally,
The D0-D15 of AS8202NF is connected with the DATA15-DATA0 of MPC555 respectively；Controller piece selects enabled CEB, writes enabled WEB, is defeated
Out enable OEB respectively with the chip selection signal of MPC555Read/write control signalsExport enable signalConnect；
The interrupt signal pin INTB of AS8202NF is connected to the external interrupt pin of MPC555On, but due to the output mould of INTB
Formula is open-drain output, and low level is effective, it is therefore desirable to external pull-up resistor；Controller ready signal READYB is used for CNI
A low level confirmation signal is sent to MPC555 after being transmitted, also due to READYB is open-drain output mode,
Need external pull-up resistor.In addition, READYB signal has asynchronous and synchronous two kinds of producing methods, by pin USE_RAM_CLK and
RAM_CLK_TESTSE control: when USE_RAM_CLK ground connection, asynchronous READYB signal will be generated, this mode allows most
Short bus cycles but finally still needing to carry out signal in application layer it is synchronous；When USE_RAM_CLK meets high level, RAM_CLK_
When TESTSE is connected with host bus clock, synchronous READYB signal will be generated, but since there may be some meta-stables
Situation, the operating mode are not suitable for being applied to the higher system of reliability requirement.This system is to simplify subsequent software design, selection
Synchronous mode generates READYB signal, USE_RAM_CLK ground connection, and RAM_CLK_TESTSE is connected with the CLKOUT of MPC555.
The connection of DM9000 and MPC555 is as shown in Fig. 3, MPC555 and DM9000 with full-duplex data transmission mode into
The transmission of row data, realizes the network transmission of AFDX protocol data, and processor MPC555 utilizes piece choosing/CS3 and address wire ADDR31
It is separately connected the AEN pin and CMD pin of DM9000 chip；Since MPC555 is using big end data format, i.e. high byte
Positioned at low address, and DM9000 is using small end data format, so the data line DATA [31:16] and DM9000 of MPC555
Data line SD [0:15] connection, for realize the data between DM9000 and MPC555 transmit；The enabled letter of the output of MPC555
Number/the reading pin IOR# of OE connection DM9000, read/write control signalsPin connection DM9000's writes pin IOW#；Together
When, DM9000 occupies interrupt pin/IRQ0 of MPC555, so that MPC555 is able to respond the interruption of DM9000.
MPC555 in house software and workflow are as shown in figure 4, protocol conversion module is the main portion of entire software design
Point, module call signal conversion process first, two priority of design are identical in the process, in polling dispatching mode
Thread, respectively AFDX turn TTP thread and TTP turns AFDX thread.TTP formatted data is exported when input is AFDX data；When
When input is TTP data, AFDX formatted data is exported.Below by taking AFDX turns TTP program circuit as an example, to signal conversion module
Some piths are described.
It is sequential bits inspection module first, AFDX turns in TTP program, needs to complete sequential bits checking function, process such as Fig. 5
It is shown, the sequential bits and the frame of the frame are had to check for for each AFDX frame for being transmitted to sequential bits checking function module
The serial number of serial number, frame designs in software, adds 1 automatically after being properly received each time, and sequential bits can be in AFDX frame format
Middle extraction.After initialization, the sequential bits of first frame are 0, after normal work, if the sequential bits of a frame are not the frames
Serial number either serial number add 1 (data that sequential bits are 8 recycle value from 0 to 255, under normal circumstances should be identical, when from
It needs to add 1) when 255 to 0, it will report an error and abandon the frame.
When there are following two special circumstances, the data received also can by integrity detection,
1) sequential bits=0；
2) the first frame data for receiving after terminal is restarted are received, at this time sequential bits it is same=0.
Next layer of Redundancy Management System is subsequently entered by the valid frame of sequence bit trial.
Redundancy Management System reads AFDX frame to be checked from the FIFO that upper level sequential bits check module, and obtaining should
The sequential bits and frame number of frame, if the two is identical or a upper frame is received afterwards in maximum delay time (SKEWmax)
It arrives, is then judged as first valid frame, can be by Redundancy Management System, and more new database.Then frame number is added
1, continue to obtain AFDX frame, if the frame received again is less than frame number at this time, is judged as duplicate frame, will be lost
It abandons, as shown in Figure 6.
The fault tolerant mechanism of TTP agreement, can be effective by the combination of factions' failure algorithm and implicit confirmation algorithm
Determine the fault condition of sending node and receiving node, and passes through bus network at the first time to other node updates member relations
List keeps the consistency of all node memberships in whole system, and Fig. 7 is the fault-tolerant process of group membership's agreement, passes through analysis
It is found that in the TTP network of m node, when appearance | (m-2)/2 | when secondary continuous fault, it will lead to group membership's agreement fault-tolerant strategy
In vain.This patent proposes that a kind of improved group membership's agreement fault-tolerant strategy is not examined temporarily when receiving data to inactive node
Membership table is surveyed, enables it to come back in system in finite time, improves system survivability.Fig. 8, which gives, to be changed
Into its fault-tolerant process of group membership's agreement.Node niOnly meet this condition of A > B, just allows to send message, otherwise node niTemporarily
When be not allowed to send message, and empty its membership table, niAs inactive node, when inactive node receives message, no
It needs to compare membership table, within next TDMA period, if inactive node can receive message, and inactive node is at it
The message sent in next sending time slots can be confirmed by other nodes, then can come back in system.
Claims (3)
1. a kind of TTP based on MPC555 and AS8202 and AFDX conversion interface circuit, including TTP/C telecommunication circuit, MPC555
Operating circuit and AFDX telecommunication circuit three parts are constituted.Wherein TTP telecommunication circuit be based on AS8202 chip, by MOIS mode with
The connection of MPC555 inter-process core.
2. interface convertor as described in claim 1, complete the copy of the TTP/C bus message based on MPC555, decoding and
The conversion of coding and TTP and AFDX protocol data.
3. this patent proposes that a kind of improved fault-tolerant strategy when receiving data to inactive node does not detect membership table temporarily,
It enables it to come back in system in finite time, improves system survivability, solve based on time trigger
Fault-tolerant strategy group membership's agreement GMP, which is directed to, there is failure irreclaimable problem when excessive continuous fault.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710389148.2A CN108959140A (en) | 2017-05-25 | 2017-05-25 | TTP and AFDX adapter based on MPC555 and AN8202 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710389148.2A CN108959140A (en) | 2017-05-25 | 2017-05-25 | TTP and AFDX adapter based on MPC555 and AN8202 |
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| Publication Number | Publication Date |
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| CN108959140A true CN108959140A (en) | 2018-12-07 |
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| CN201710389148.2A Pending CN108959140A (en) | 2017-05-25 | 2017-05-25 | TTP and AFDX adapter based on MPC555 and AN8202 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102135762A (en) * | 2010-12-31 | 2011-07-27 | 上海派芬自动控制技术有限公司 | Time trigger type real-time simulation control system |
| CN104483828A (en) * | 2014-12-04 | 2015-04-01 | 中国航空工业集团公司第六三一研究所 | Distributed fault tolerance computer member consistency ensuring method |
-
2017
- 2017-05-25 CN CN201710389148.2A patent/CN108959140A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102135762A (en) * | 2010-12-31 | 2011-07-27 | 上海派芬自动控制技术有限公司 | Time trigger type real-time simulation control system |
| CN104483828A (en) * | 2014-12-04 | 2015-04-01 | 中国航空工业集团公司第六三一研究所 | Distributed fault tolerance computer member consistency ensuring method |
Non-Patent Citations (1)
| Title |
|---|
| 杨景中 等: "结合短帧优先的权重轮询AFDX端系统发送策略", 《北京航空航天大学学报》 * |
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