CN108958996A - A kind of test memory RankMargin optimization method and system - Google Patents
A kind of test memory RankMargin optimization method and system Download PDFInfo
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- CN108958996A CN108958996A CN201810495493.9A CN201810495493A CN108958996A CN 108958996 A CN108958996 A CN 108958996A CN 201810495493 A CN201810495493 A CN 201810495493A CN 108958996 A CN108958996 A CN 108958996A
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- 238000012360 testing method Methods 0.000 title claims abstract description 73
- 230000015654 memory Effects 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000005457 optimization Methods 0.000 title claims abstract description 30
- 238000012790 confirmation Methods 0.000 claims abstract description 13
- 230000004913 activation Effects 0.000 claims description 12
- 238000012544 monitoring process Methods 0.000 claims description 11
- 230000004048 modification Effects 0.000 claims description 8
- 238000012986 modification Methods 0.000 claims description 8
- 238000003825 pressing Methods 0.000 claims description 6
- 238000003860 storage Methods 0.000 claims description 6
- 230000008676 import Effects 0.000 claims description 4
- 238000010200 validation analysis Methods 0.000 claims 1
- 238000009434 installation Methods 0.000 abstract description 4
- 230000008569 process Effects 0.000 abstract description 3
- 230000008901 benefit Effects 0.000 abstract description 2
- 238000001816 cooling Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- General Engineering & Computer Science (AREA)
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- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
The problem of the invention discloses a kind of test memory Rank Margin optimization method and systems, are related to hardware optimization the field of test technology, solve test in the prior art and need to tear open the equipment such as machine installation Serial Port Line, and process is cumbersome, influence testing efficiency.The technical solution of use are as follows: method is the following steps are included: modify the BIOS setting options of board to be measured；By the sol log of the BMC Remote Open board to be measured of an other test machine, and by sol log information recording to file；Board to be measured is shut down, then is switched on, sol log will be automatically recorded；Sol log is downloaded and is exported, confirmation message；The present invention connects any hardware external equipment without tearing machine open, has the advantages that easy to use, convenient test is flexible, high reliablity, test speed are fast and high-efficient.
Description
Technical field
The present invention relates to hardware optimization the field of test technology, specifically a kind of test memory Rank Margin optimization
Method and system.
Background technique
Memory is one of the ost important components in computer, it is the bridge linked up with CPU.All programs in computer
Operation all carry out in memory, therefore influence of the performance of memory to computer is very big.Memory is also referred to as memory
Reservoir, effect is for temporarily storing the operational data in CPU, and the data exchanged with external memories such as hard disks.Only
Want computer in operation, CPU will be transferred to the data for needing operation in memory and carry out operation, and CPU is again after the completion of operation
Result is sent out, the operation of memory also determines the stable operation of computer.
The compatibility of memory and mainboard directly affects the normal work of server, and common Rank Margin is limited to
Dependence of test complexity and Serial Port Line etc. can only carry out testing one by one, and testing efficiency is extremely low, and coverage is not
Enough, there are risk hidden danger；In response to this problem, such as patent 201710294823.3, entitled " one kind can be carried out by network in batches
The method of server memory Rank Margin test ", the technical solution which uses are as follows: be used for test phase or production
Stage internally deposits into the test in terms of row Rank Margin in batches, while result is printed to and is saved on the hard disk of the machine,
And be compared automatically with SPEC, output test passes through or the result of failure；Though the technical solution of the patent can be real simultaneously
Existing multiple servers carry out Rank Margin test, improve the compatibility of memory and server.
But the RMT performance of current development phase test memory, the main interface BMC_ passed through on Serial Port Line connection mainboard
UART finally grabs log log comparing result to control computer end test, and such test needs to tear open machine installation Serial Port Line etc. and sets
Standby, process is cumbersome, influences testing efficiency, and the technical solution that above-mentioned patent uses can not solve the above problems.
Summary of the invention
Technical assignment of the invention is to provide a kind of test memory Rank Margin optimization method and system, existing to solve
There is in technology test need to tear open the equipment such as machine installation Serial Port Line, process is cumbersome, the problem of influencing testing efficiency.
Technical assignment of the invention realizes in the following manner,
A kind of test memory Rank Margin optimization method, the described method comprises the following steps:
(1), the BIOS setting options of board to be measured are modified；
(2), by the sol log of the BMC Remote Open board to be measured of an other test machine, and by sol log information recording
To file；
(3), board to be measured is shut down, then be switched on, sol log will be automatically recorded；
(4), sol log is downloaded and is exported, confirmation message.
In the step (1), prepare board to be measured, and modify BIOS setting options, reenters BIOS setup, and
Three kinds of operating statuses are respectively set in the storage configuration of processor；
State 1: state of activation is enabled by being set as enabled in Rank Margin tool；
State 2: disabled disabled state is set as in attempting quick start；
State 3: disabled disabled state is set as in attempting quickly cold start-up.
In the step (2), by being arranged and running the one of ipmi platform management tool on another test machine host
The long-range monitoring instruction of group, is capable of the sol log of Remote Open board to be measured, and record information to file.
In the step (3), comprising the following steps:
A, by pressing the power switch of board to be measured, board host to be measured is closed；
B, after closing board host to be measured, it is arranged on a testing machine and run ipmi platform management tool another group remotely monitors
Instruction, and activate sol log；
C, by pressing the power switch of board to be measured, opening board host to be measured will survey when board to be measured shows starting-up interface
The remote monitoring end mouth of test-run a machine is disconnected with the board connectivity port to be measured being connected, and is accessed simultaneously by opening web interface
Download sol log.
In the step (4), the sol log that downloading is completed is imported in intel tool and checks RMT performance, and saves sol
Log comparing result.
A kind of test memory Rank Margin optimization system, use any test memory Rank Margin among the above
Optimization method, system include:
, modification unit, for modifying the BIOS setting options of board to be measured；
, remote control unit, for the sol log of the BMC Remote Open board to be measured by an other test machine, and
By sol log information recording to file；
, equipment manipulate unit, shut down, then be switched on, and automatically record sol log for board to be measured；
, information confirmation unit, for by sol log download export, confirmation message.
Unit setting modification BIOS option is modified, reenters BIOS setup, and divide in the storage configuration of processor
It She Zhi not three kinds of operating statuses；
State 1: it is set as enabled in Rank Margin tool and enables state of activation；
State 2: disabled disabled state is set as in attempting quick start；
State 3: disabled disabled state is set as in attempting quickly cold start-up.
Remote control unit tested on machine host at another be arranged and run one group of ipmi platform management tool it is long-range
Monitoring instruction, the sol log of Remote Open board to be measured, and record information to file.
The stepIn, equipment manipulation unit further includes that equipment closing unit, long-range activation unit and equipment starting are visited
Ask unit,
Equipment closing unit, for closing board host to be measured；
Long-range activation unit, for be arranged on a testing machine and run another group of ipmi platform management tool remotely monitoring refer to
It enables, and activates sol log；
Equipment starts access unit, and for opening board host to be measured, board to be measured shows starting-up interface, the remote of test machine is arranged
Range monitoring port is off-state with the board connectivity port to be measured being connected, and accesses by opening web interface and download sol
Log.
Information confirmation unit, which is used to import the sol log that downloading is completed in intel tool, checks RMT performance, and saves
Sol log comparing result.
A kind of test memory Rank Margin optimization method of the invention and system have the advantage that compared with the prior art
1, a kind of test memory Rank Margin optimization method provided by the invention and system by modification BIOS option, pass through
The method that board to be measured is remotely controlled using test machine can replace test memory Rank Margin in prior art to need
Tear the machine installation equipment such as Serial Port Line open, the present invention connects the external equipments such as any hardware without tearing machine open, with easy to use excellent
Point；
2, the present invention is more convenient flexible on test memory Rank Margin；
3, the present invention has the characteristics that fast and high-efficient using simplicity, high reliablity, test speed, therefore, has and pushes away well
Wide use value.
Detailed description of the invention
The following further describes the present invention with reference to the drawings.
Attached drawing 1 is a kind of flow diagram of test memory Rank Margin optimization method.
Specific embodiment
A kind of method of web access Docker container of the invention is made referring to Figure of description and specific embodiment following
It explains in detail.
Embodiment 1:
A kind of test memory Rank Margin optimization method of the invention, the described method comprises the following steps:
(1), the BIOS setting options of board to be measured are modified；
(2), by the sol log of the BMC Remote Open board to be measured of an other test machine, and by sol log information recording
To file；
(3), board to be measured is shut down, then be switched on, sol log will be automatically recorded；
(4), sol log is downloaded and is exported, confirmation message.
Embodiment 2:
A kind of test memory Rank Margin optimization method of the invention, the described method comprises the following steps:
(1), prepare board to be measured first, and modify the BIOS setting options of board to be measured, reenter BIOS setup, and
Three kinds of operating statuses are respectively set in the storage configuration of processor；Three kinds of operating statuses are respectively in Rank Margin tool
It is set as enabled and enables state of activation；Disabled disabled state is set as in attempting quick start；Attempting fast quickly cooling
Disabled disabled state is set as in starting；
(2), by the sol log of the BMC Remote Open board to be measured of an other test machine, it is arranged on the test machine host
And one group for running ipmi platform management tool remotely monitors instruction, is capable of the sol log of Remote Open board to be measured, and will letter
File is recorded in breath；
(3), board host to be measured is closed by pressing the power switch of board to be measured first；After closing board host to be measured,
It is arranged on a testing machine and run ipmi platform management tool another group remotely monitors instruction, and activates sol log；Then lead to
The power switch for pressing board to be measured is crossed, board host to be measured is opened, when board to be measured shows starting-up interface, by the remote of test machine
Range monitoring port is disconnected with the board connectivity port to be measured being connected, and is accessed and downloaded sol days by opening web interface
Will.
(4), sol log is downloaded and is exported, the sol log that downloading is completed imports intel tool Xeon_E5_RMTRE_
2p8.exe checks RMT performance, and saves sol log comparing result.
Embodiment 3:
A kind of test memory Rank Margin optimization system of the invention, uses any survey in embodiment 1 or embodiment 2
Memory Rank Margin optimization method is tried, system includes:
, modification unit, for modifying the BIOS setting options of board to be measured；
, remote control unit, for the sol log of the BMC Remote Open board to be measured by an other test machine, and
By sol log information recording to file；
, equipment manipulate unit, shut down, then be switched on, and automatically record sol log for board to be measured；
, information confirmation unit, for by sol log download export, confirmation message.
Embodiment 4:
A kind of test memory Rank Margin optimization system of the invention, uses any survey in embodiment 1 or embodiment 2
Memory Rank Margin optimization method is tried, system includes:
, modification unit for modifying the BIOS setting options of board to be measured reenter BIOS setup, and in processor
Storage configuration in three kinds of operating statuses are respectively set；Three kinds of operating statuses are respectively to be set as in Rank Margin tool
Enabled enables state of activation；Disabled disabled state is set as in attempting quick start；In attempting quickly cold start-up
It is set as disabled disabled state；
, remote control unit, for the sol log of the BMC Remote Open board to be measured by an other test machine,
It is arranged on the test machine host and run ipmi platform management tool one group remotely monitors instruction, Remote Open board to be measured
Sol log, and record information to file；
, equipment manipulate unit, equipment manipulation unit further includes that equipment closing unit, long-range activation unit and equipment starting are visited
Ask unit,
Equipment closing unit, for closing board host to be measured；
Long-range activation unit, for be arranged on a testing machine and run another group of ipmi platform management tool remotely monitoring refer to
It enables, and activates sol log；
Equipment starts access unit, and for opening board host to be measured, board to be measured shows starting-up interface, the remote of test machine is arranged
Range monitoring port is off-state with the board connectivity port to be measured being connected, and accesses by opening web interface and download sol
Log；
, information confirmation unit, for by sol log download export, information confirmation unit simultaneously will downloading complete sol log
It imports intel tool Xeon_E5_RMTRE_2p8.exe and checks RMT performance, and save sol log comparing result.
The technical personnel in the technical field can readily realize the present invention with the above specific embodiments,.But it answers
Work as understanding, the present invention is not limited to 4 kinds of above-mentioned specific embodiments.On the basis of the disclosed embodiments, the technology
The technical staff in field can arbitrarily combine different technical features, to realize different technical solutions.
Except for the technical features described in the specification, it all is technically known to those skilled in the art.
Claims (10)
1. a kind of test memory Rank Margin optimization method, it is characterised in that the described method comprises the following steps:
(1), the BIOS setting options of board to be measured are modified；
(2), by the sol log of the BMC Remote Open board to be measured of an other test machine, and by sol log information recording
To file；
(3), board to be measured is shut down, then be switched on, sol log will be automatically recorded；
(4), sol log is downloaded and is exported, confirmation message.
2. a kind of test memory Rank Margin optimization method according to claim 1, it is characterised in that the step
(1) in, prepare board to be measured, and modify BIOS setting options, reenter BIOS setup, and in the storage configuration of processor
In three kinds of operating statuses are respectively set；
State 1: state of activation is enabled by being set as enabled in Rank Margin tool；
State 2: disabled disabled state is set as in attempting quick start；
State 3: disabled disabled state is set as in attempting quickly cold start-up.
3. a kind of test memory Rank Margin optimization method according to claim 1, it is characterised in that the step
(2) in, instruction, energy are remotely monitored by one group being arranged and running ipmi platform management tool on another test machine host
The sol log of enough Remote Open boards to be measured, and record information to file.
4. a kind of test memory Rank Margin optimization method according to claim 1, it is characterised in that the step
(3) in, comprising the following steps:
A, by pressing the power switch of board to be measured, board host to be measured is closed；
B, after closing board host to be measured, it is arranged on a testing machine and run ipmi platform management tool another group remotely monitors
Instruction, and activate sol log；
C, by pressing the power switch of board to be measured, opening board host to be measured will survey when board to be measured shows starting-up interface
The remote monitoring end mouth of test-run a machine is disconnected with the board connectivity port to be measured being connected, and is accessed simultaneously by opening web interface
Download sol log.
5. a kind of test memory Rank Margin optimization method according to claim 1, it is characterised in that the step
(4) in, the sol log that downloading is completed is imported in intel tool and checks RMT performance, and saves sol log comparing result.
6. a kind of test memory Rank Margin optimization system, it is characterised in that use any test in claim 1-5
Memory Rank Margin optimization method, system include:
, modification unit, for modifying the BIOS setting options of board to be measured；
, remote control unit, for the sol log of the BMC Remote Open board to be measured by an other test machine, and will
Sol log information recording is to file；
, equipment manipulate unit, shut down, then be switched on, and automatically record sol log for board to be measured；
, information confirmation unit, for by sol log download export, confirmation message.
7. a kind of test memory Rank Margin optimization system according to claim 6, it is characterised in that modification unit is set
Modification BIOS option is set, BIOS setup is reentered, and three kinds of operating statuses are respectively set in the storage configuration of processor；
State 1: it is set as enabled in Rank Margin tool and enables state of activation；
State 2: disabled disabled state is set as in attempting quick start；
State 3: disabled disabled state is set as in attempting quickly cold start-up.
8. a kind of test memory Rank Margin optimization system according to claim 6, it is characterised in that long-range control is single
Member is tested on machine host at another to be arranged and runs one group of ipmi platform management tool and remotely monitor instruction, and Remote Open waits for
The sol log of board is surveyed, and records information to file.
9. a kind of test memory Rank Margin optimization system according to claim 6, it is characterised in that the step
In, equipment manipulation unit further includes that equipment closing unit, long-range activation unit and equipment start access unit,
Equipment closing unit, for closing board host to be measured；
Long-range activation unit, for be arranged on a testing machine and run another group of ipmi platform management tool remotely monitoring refer to
It enables, and activates sol log；
Equipment starts access unit, and for opening board host to be measured, board to be measured shows starting-up interface, the remote of test machine is arranged
Range monitoring port is off-state with the board connectivity port to be measured being connected, and accesses by opening web interface and download sol
Log.
10. a kind of test memory Rank Margin optimization system according to claim 6, it is characterised in that validation of information
Unit, which is used to import the sol log that downloading is completed in intel tool, checks RMT performance, and saves sol log comparing result.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810495493.9A CN108958996A (en) | 2018-05-22 | 2018-05-22 | A kind of test memory RankMargin optimization method and system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810495493.9A CN108958996A (en) | 2018-05-22 | 2018-05-22 | A kind of test memory RankMargin optimization method and system |
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| CN108958996A true CN108958996A (en) | 2018-12-07 |
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| CN201810495493.9A Pending CN108958996A (en) | 2018-05-22 | 2018-05-22 | A kind of test memory RankMargin optimization method and system |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112463517A (en) * | 2020-10-30 | 2021-03-09 | 苏州浪潮智能科技有限公司 | SOL-based signal screen capture information acquisition method and device |
| WO2023206957A1 (en) * | 2022-04-29 | 2023-11-02 | 苏州元脑智能科技有限公司 | Memory test method, apparatus and system, device, and readable storage medium |
| WO2023245779A1 (en) * | 2022-06-24 | 2023-12-28 | 长鑫存储技术有限公司 | Memory judgment method and apparatus, storage medium, and electronic device |
-
2018
- 2018-05-22 CN CN201810495493.9A patent/CN108958996A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112463517A (en) * | 2020-10-30 | 2021-03-09 | 苏州浪潮智能科技有限公司 | SOL-based signal screen capture information acquisition method and device |
| WO2023206957A1 (en) * | 2022-04-29 | 2023-11-02 | 苏州元脑智能科技有限公司 | Memory test method, apparatus and system, device, and readable storage medium |
| WO2023245779A1 (en) * | 2022-06-24 | 2023-12-28 | 长鑫存储技术有限公司 | Memory judgment method and apparatus, storage medium, and electronic device |
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Application publication date: 20181207 |
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