CN108922925A - A kind of power device protection chip and preparation method thereof - Google Patents
A kind of power device protection chip and preparation method thereof Download PDFInfo
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- CN108922925A CN108922925A CN201810746985.0A CN201810746985A CN108922925A CN 108922925 A CN108922925 A CN 108922925A CN 201810746985 A CN201810746985 A CN 201810746985A CN 108922925 A CN108922925 A CN 108922925A
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- 229920005591 polysilicon Polymers 0.000 claims abstract description 54
- 238000002347 injection Methods 0.000 claims abstract description 43
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- 238000004519 manufacturing process Methods 0.000 claims description 19
- 230000015572 biosynthetic process Effects 0.000 claims description 11
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
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Abstract
The present invention provides a kind of power device protection chips and preparation method thereof, including：The substrate of first conduction type；First epitaxial layer of the first conduction type, is grown on the upper surface of substrate；The buried layer of first conduction type is formed in first epitaxial layer；Second epitaxial layer of the second conduction type is formed in first epitaxial layer upper surface；The third epitaxial layer of second conduction type is connect through second epitaxial layer and with the buried layer；First injection region of the first conduction type is formed in second epitaxial layer and is connected with the buried layer and the third epitaxial layer；Dielectric layer, the dielectric layer include that the first part positioned at second epitaxial layer upper surface connect with the first part and run through the second part that second epitaxial layer extends to first epitaxial layer；Polysilicon layer extends in the third epitaxial layer through the first part.Device performance, which can be improved, in the present invention reduces device cost.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of power device protection chip and preparation method thereof.
Background technique
Power device protection chip is a kind of for protecting sensitive semiconductor device, destroys it from transient voltage surge
And specially designed solid-state semiconductor device, it has, and clamp coefficient is small, small in size, response is fast, leakage current is small and high reliablity
The advantages that, thus be widely used on voltage transient and carrying out surge protection.Low Capacitance Power device protection chip is applicable in
In the protection device of high-frequency circuit, because it can reduce interference of the parasitic capacitance to circuit, declining for high-frequency circuit signal is reduced
Subtract.
The transient voltage that static discharge and some other voltage surge form occur at random, is typically found in various electronics
In device.As semiconductor devices increasingly tends to miniaturization, high density and multi-functional, electronic device becomes increasingly susceptible to voltage
The influence of surge, even results in fatal harm.Various voltage surges can induce transient current from static discharge to lightning etc.
Peak power device protects impact of the chip commonly used to protection sensitive circuit by surge.Based on different applications, power device
Part protection chip can play the role of circuit protection by changing the clamping voltag of surge discharge path and itself.
Currently used power device protects chip, further decreases parasitic capacitance if necessary then for multiple power devices
Part protection chip is connected in parallel, and increases device area and manufacturing cost in this way.
Summary of the invention
The present invention is based on the above problems, proposes a kind of power device protection chip and preparation method thereof, is improving
Power device reduces the manufacturing cost of power device protection chip while protecting chip performance.
In view of this, on the one hand the embodiment of the present invention proposes a kind of power device protection chip, power device protection
Chip includes：
The substrate of first conduction type；
First epitaxial layer of the first conduction type, is grown on the upper surface of substrate, and the doping concentration of the substrate is higher than
The doping concentration of first epitaxial layer；
The buried layer of first conduction type is formed in first epitaxial layer, and at least partly surface of the buried layer is naked
It is exposed to first epitaxial layer upper surface, the doping concentration of the buried layer is higher than the doping concentration of first epitaxial layer；
Second epitaxial layer of the second conduction type is formed in first epitaxial layer upper surface；
The third epitaxial layer of second conduction type is connect through second epitaxial layer and with the buried layer；
Dielectric layer, the first part including extending to first epitaxial layer through second epitaxial layer；
Polysilicon layer is formed in the third epitaxial layer and extends to third epitaxial layer upper surface；
First electrode is connect with second epitaxial layer and the polysilicon layer respectively；
Second electrode is formed in the lower surface of the substrate and connect with the substrate.
Further, power device protection chip further includes the first injection region of the first conduction type, and described first
Injection region is formed in second epitaxial layer and is connected with the buried layer and the third epitaxial layer.
Further, the dielectric layer further includes the second part positioned at second epitaxial layer upper surface.
Further, the first electrode is formed in the dielectric layer upper surface, and the polysilicon layer runs through described second
Part is to connect the first electrode.
Further, the first electrode is connect through the second part and with second epitaxial layer.
On the other hand the embodiment of the present invention provides a kind of production method of power device protection chip, this method includes：
In the first epitaxial layer of one conduction type of upper surface of substrate growth regulation of the first conduction type, the doping of the substrate
Concentration is higher than the doping concentration of first epitaxial layer；
Form the buried layer of the first conduction type in first epitaxial layer, at least partly surface exposure of the buried layer in
The upper surface of first epitaxial layer, the doping concentration of the buried layer are higher than the doping concentration of first epitaxial layer；
The second epitaxial layer of the second conduction type is formed in first epitaxial layer upper surface；
The first groove of the buried layer is formed through second epitaxial layer and extended in second epitaxial layer；
The third epitaxial layer of the second conduction type is formed in the first groove side wall and bottom surface, makes the third epitaxial layer
It is connect with the buried layer, and forms second groove in the third epitaxial layer；
Form the third groove for running through second epitaxial layer and connecting with first epitaxial layer；
The first part of dielectric layer is formed in the third groove；
Polysilicon layer is formed in the second groove, the polysilicon layer is extended to out of described second groove described
The upper surface of third epitaxial layer；
Form the first electrode connecting respectively with second epitaxial layer and the polysilicon layer；
The second electrode connecting with the substrate is formed in the lower surface of the substrate.
Further, it after the second epitaxial layer that first epitaxial layer upper surface forms the second conduction type, also wraps
It includes：
The first injection region of the first conduction type is formed in second epitaxial layer, first injection region is buried with described
Layer and the third epitaxial layer are connected.
Further, it is formed in the third groove after the first part of dielectric layer, further includes：
The second part of the dielectric layer is formed in second epitaxial layer upper surface.
Further, the first electrode that the formation is connect with second epitaxial layer and the polysilicon layer respectively is specific
Including：
The first electrode is formed in the dielectric layer upper surface, the polysilicon layer is run through into the second part and company
Connect the first electrode.
Further, the first electrode that the formation is connect with second epitaxial layer and the polysilicon layer respectively is specific
Including：
The first electrode is connected through the second part and with second epitaxial layer.
The technical solution of the embodiment of the present invention passes through one conduction type of upper surface of substrate growth regulation in the first conduction type
The first epitaxial layer, the doping concentration of the substrate is higher than the doping concentration of first epitaxial layer；In first epitaxial layer
The interior buried layer for forming the first conduction type, at least partly surface exposure of the buried layer in the upper surface of first epitaxial layer,
The doping concentration of the buried layer is higher than the doping concentration of first epitaxial layer；Second is formed in first epitaxial layer upper surface
Second epitaxial layer of conduction type；It is formed in second epitaxial layer through second epitaxial layer and extends to the buried layer
First groove；The third epitaxial layer of the second conduction type is formed in the first groove side wall and bottom surface, is made outside the third
Prolong layer to connect with the buried layer, and forms second groove in the third epitaxial layer；It is formed through second epitaxial layer simultaneously
The third groove being connect with first epitaxial layer；The first part of dielectric layer is formed in the third groove；Described
Polysilicon layer is formed in two grooves, and the polysilicon layer is extended to the upper table of the third epitaxial layer out of described second groove
Face；Form the first electrode connecting respectively with second epitaxial layer and the polysilicon layer；In the lower surface shape of the substrate
At the second electrode being connect with the substrate.To reduce parasitic capacitance, so that the protection feature and reliability of device all obtain
Promotion is arrived.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below to needed in embodiment description
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, general for this field
For logical technical staff, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is the flow diagram of the production method for the power device protection chip that one embodiment of the present of invention provides；
Fig. 2 to Figure 11 is the knot of the production method step for the power device protection chip that one embodiment of the present of invention provides
Structure schematic diagram；
Figure 12 is the equivalent circuit diagram for the power device protection chip structure that one embodiment of the present of invention provides；
In figure：1, substrate；2, the first epitaxial layer；3, buried layer；4, the second epitaxial layer；5, first groove；6, third epitaxial layer；
7, second groove；8, the first injection region；9, third groove；10, dielectric layer；101, first part；102, second part；103,
One contact hole；104, the second contact hole；11, polysilicon layer；12, the first metal layer；13, second metal layer；14, first electrode；
15, second electrode；A, first diode；B, the second diode b.
Specific implementation method
It below will the present invention will be described in more detail refering to attached drawing.In various figures, identical element uses similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use that " A is directly on B herein to describe located immediately at another layer, another region above scenario
The expression method of face " or " A on B and therewith abut ".In this application, " A is in B " indicates that A is located in B, and
And A and B is abutted directly against, rather than A is located in the doped region formed in B.
In this application, term " semiconductor structure " refers to entire half formed in each step of manufacturing semiconductor devices
The general designation of conductor structure, including all layers formed or region.
Many specific details of the invention, such as structure, material, the size, processing side of device are described hereinafter
Method and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
Below in conjunction with Fig. 1 to Figure 12 to a kind of power device protection chip provided in an embodiment of the present invention and preparation method thereof
It is described in detail.
The embodiment of the present invention provides a kind of production method of power device protection chip, one embodiment as shown in Figure 1
The flow diagram of the production method of the power device protection chip of offer, the power device protect the production method packet of chip
It includes：
Step S1：It is described in the first epitaxial layer 2 of 1 upper surface growth regulation of substrate, one conduction type of the first conduction type
The doping concentration of substrate 1 is higher than the doping concentration of first epitaxial layer 2.
Step S2：The buried layer 3 of the first conduction type is formed in first epitaxial layer 2, the buried layer 3 is at least partly
Surface exposure is higher than mixing for first epitaxial layer 2 in the upper surface of first epitaxial layer 2, the doping concentration of the buried layer 3
Miscellaneous concentration.
Step S3：The second epitaxial layer 4 of the second conduction type is formed in 2 upper surface of the first epitaxial layer.
Step S4：It is formed in second epitaxial layer 4 through second epitaxial layer 4 and extends to the buried layer 3
First groove 5.
Step S5：The third epitaxial layer 6 of the second conduction type is formed in 5 side wall of first groove and bottom surface, is made described
Third epitaxial layer 6 is connect with the buried layer 3, and second groove 7 is formed in the third epitaxial layer 6.
Step S6：Form the third groove 9 for running through second epitaxial layer 4 and connecting with first epitaxial layer 2.
Step S7：The first part 101 of dielectric layer 10 is formed in the third groove 9.
Step S8：Polysilicon layer 11 is formed in the second groove 7, by the polysilicon layer 11 from the second groove
The upper surface of the third epitaxial layer 6 is extended in 7.
Step S9：Form the first electrode 14 connecting respectively with second epitaxial layer 4 and the polysilicon layer 11；Institute
The lower surface for stating substrate 1 forms the second electrode 15 connecting with the substrate 1.
It is understood that the first groove 5 is deep trench, by being formed in 5 side wall of first groove and bottom surface
The third epitaxial layer 6 of second conduction type, and the polysilicon layer 11, the polycrystalline are formed in the second groove 7
For silicon layer 11 for discharging, the third epitaxial layer 6 and the buried layer 3 form PN junction, specifically, the bottom surface of the groove with it is described
Buried layer 3 is reacted, so as to form a conductive path.Dielectric layer 10 is formed in the third groove 9 simultaneously, it is described
The dielectric layer 10 formed in third groove 9 plays the role of isolation, reduces parasitic capacitance.
Specifically, the substrate 1 is the carrier in integrated circuit, and the substrate 1 plays the role of support, the substrate 1
Also assist in the work of the integrated circuit.The substrate 1 can be silicon substrate, or Sapphire Substrate can also be carbon
Silicon substrate, it might even be possible to be silicon Chu substrate, it is preferred that the substrate 1 is silicon substrate, this is because silicon substrate material is with low
Cost, large scale, conductive feature, avoid edge effect, can increase substantially yield.
Specifically, first conduction type is one of p-type doping and n-type doping, and second conduction type is P
Type doping and the another kind in n-type doping.
Referring next to attached drawing, the production method of power device described above protection chip is elaborated.
For convenience of description, spy illustrates herein：First conduction type can be n-type doping, so that described second is conductive
Type is p-type doping；First conduction type can also adulterate for p-type, so that second conduction type is n-type doping.
It is understood that when first conduction type is n-type doping, when second conduction type is that p-type is adulterated, the substrate
1, first epitaxial layer 2, the buried layer 3 and first injection region 8 are p-type doping, second epitaxial layer 4 and described
Third epitaxial layer 6 is N-type epitaxy layer.When first conduction type is p-type doping, second conduction type is mixed for N-type
When miscellaneous, the substrate 1, first epitaxial layer 2, the buried layer 3 and first injection region 8 are n-type doping, and described second
Epitaxial layer 4 and the third epitaxial layer 6 are p-type epitaxial layer.Preferably, first conduction type is p-type doping, described the
Two conduction types are n-type doping, because the effective mass in hole is small, mobility is small, thus more difficult conduction, opposite N-type material
For material, resistivity wants high, and as P type substrate, typically grounded current potential forms reverse biased pn junction with epitaxial layer.In next reality
Apply in example, using first conduction type as p-type adulterate, second conduction type be n-type doping for be described, but
It is defined not to this.
Specifically, P type substrate and p-type extension belong to P-type semiconductor, and N-type substrate and N-type extension belong to N-type and partly lead
Body.The P-type semiconductor is the silicon wafer for adulterating triad, such as any group of boron element or phosphide element or aluminium element or three
It closes.The N-type semiconductor is any combination of the silicon wafer for adulterating pentad, such as P elements or arsenic element or both.
Attached drawing 2 is please referred to, executes step S1, specially：It is conductive in the 1 upper surface growth regulation of substrate one of the first conduction type
First epitaxial layer 2 of type.It can wherein be epitaxially-formed, can also be infused by ion in the 1 upper surface use of substrate
The method for entering and/or spreading forms first epitaxial layer 2 in 1 upper surface of substrate.It is possible to further in the substrate
1 upper surface use is epitaxially-formed, and can also pass through ion implanting and/or diffusion boron element or phosphide element or aluminium element or three
The method of any combination of person forms first epitaxial layer 2 in 1 upper surface of substrate.Specifically, the extension or diffusion
Method include depositing operation.In some embodiments of the invention, depositing operation can be used in the 1 upper surface shape of substrate
At first epitaxial layer 2, for example, depositing operation can be selected from electron beam evaporation, chemical vapor deposition, atomic layer deposition,
One of sputtering.Preferably, the first epitaxial layer 2, chemical vapor deposition are formed using chemical vapor deposition on the substrate 1
Including process for vapor phase epitaxy.In production, chemical vapor deposition uses process for vapor phase epitaxy mostly, in 1 upper surface of substrate
The first epitaxial layer 2 is formed using process for vapor phase epitaxy, process for vapor phase epitaxy can be improved the perfection of silicon materials, improve device
Integrated level reaches raising minority carrier life time, reduces the leakage current of storage element.Further, the doping concentration of the substrate 1 and institute
The doping concentration for stating the first epitaxial layer 2 is different.Preferably, the doping concentration of the substrate 1 is higher than mixing for first epitaxial layer 2
Miscellaneous concentration, the resistivity of substrate 1 described in the resistivity ratio of first epitaxial layer 2 is high at this time, reduces dead resistance, to be promoted
The breakdown reverse voltage of device.
Attached drawing 3 is please referred to, executes step S2, specially：Burying for the first conduction type is formed in first epitaxial layer 2
Layer 3, at least partly surface exposure of the buried layer 3 is in the upper surface of first epitaxial layer 2.The buried layer 3 can be by outer
Prolong growth to be formed, can also be formed by ion implanting and/or the method for diffusion.Further, the buried layer 3 can be by outer
Prolong growth to be formed, ion implanting and/or diffusion boron element or phosphide element or aluminium element or any combination of three can also be passed through
Method formed.Preferably, the method that ion implanting can be used forms the buried layer 3, forms described bury by ion implanting
Layer 3 can accurately control the accumulated dose, depth distribution and surface uniformity of impurity, can prevent spreading again for original impurity, while can
Self-aligned technology is realized, to reduce capacity effect.
Attached drawing 4 is please referred to, executes step S3, specially：The second conduction type is formed in 2 upper surface of the first epitaxial layer
The second epitaxial layer 4.Extension, diffusion and/or the method for injection wherein can be used and form second epitaxial layer 4, specifically,
The extension or the method for diffusion include depositing operation.It is possible to further use extension, diffusion and/or injection P elements or
The method of any combination of arsenic element or both forms second epitaxial layer 4.In some embodiments of the invention, using heavy
Product technique forms the second epitaxial layer 4 in 2 upper surface of the first epitaxial layer, steams for example, depositing operation can be selected from electron beam
One of hair, chemical vapor deposition, atomic layer deposition, sputtering.Wherein, chemical vapor deposition includes process for vapor phase epitaxy, excellent
Choosing, the second epitaxial layer 4 is formed using process for vapor phase epitaxy in 2 upper surface of the first epitaxial layer, process for vapor phase epitaxy can be with
The perfection for improving silicon materials, improves the integrated level of device, reaches raising minority carrier life time, reduce the leakage current of storage element.Institute
It states the second epitaxial layer 4 to cover the upper surface of first epitaxial layer 2, and is equipped with certain thickness.
Attached drawing 5 is please referred to, executes step S4, specially：It is formed in second epitaxial layer 4 and runs through second extension
Layer 4 and the first groove 5 for extending to the buried layer 3.In some embodiments of the invention, in the upper of second epitaxial layer 4
Surface prepares mask material, and the mask material is specially the first photoresist, passes through etching shape on first photoresist layer
The first groove 5 of the buried layer 3 is extended at through second epitaxial layer 4, then removes first photoresist.Wherein, it carves
The method of erosion includes dry etching and wet etching, it is preferred that the method for the etching used is dry etching, and dry etching includes
Photoablation, gaseous corrosion, plasma etching etc., and dry etching easily realizes that automation, treatment process are not introduced into pollution, cleaning
Degree is high.In some embodiments of the invention, the bottom surface of the first groove 5 is connected with the buried layer 3, for example, described
The bottom surface of one groove 5 extends in the buried layer 3, and the bottom surface of the first groove 5 can also be with the upper table of the buried layer 3
Face connection, guarantees that the bottom surface of the first groove 5 is contacted with the buried layer 3.
Attached drawing 6 is please referred to, executes step S5, specially：The second conductive-type is formed in 5 side wall of first groove and bottom surface
The third epitaxial layer 6 of type connect the third epitaxial layer 6 with the buried layer 3, and is formed in the third epitaxial layer 6
Two grooves 7.In some embodiments of the invention, extension or the side of diffusion are used in the side wall of the first groove 5 and bottom surface
Method forms the third epitaxial layer 6, further, in the side wall and underrun extension or diffusion phosphorus member of the first groove 5
Any combination of plain or arsenic element or both is to form the third epitaxial layer 6.Specifically, the third epitaxial layer 6 is the
The heavy doping of two conduction types, the doping concentration of the third epitaxial layer 6 are higher than the doping concentration of second epitaxial layer 4.
Further, referring to Fig. 7, being based on above-mentioned steps S5, step 51 is executed, specially：In first epitaxial layer 2
Upper surface is formed after the second epitaxial layer 4 of the second conduction type, further includes：First is formed in second epitaxial layer 4 to lead
First injection region 8 of electric type, first injection region 8 are connected with the buried layer 3 and the third epitaxial layer 6.In addition,
5 side wall of first groove and bottom surface form the third epitaxial layer 6 of the second conduction type, make the third epitaxial layer 6 with it is described
Buried layer 3 connects, and is formed after second groove 7 in the third epitaxial layer 6, and the is also formed in second epitaxial layer 4
First injection region 8 of one conduction type, first injection region 8 are connected with the buried layer 3 and the third epitaxial layer 6.?
In some embodiments of the present invention, mask material is prepared in the upper surface of second epitaxial layer 4, the mask material is specially
Second photoresist forms first in second epitaxial layer 4 respectively by the method for photoetching on second photoresist layer
Injection region 8, first injection region 8 are connected with the buried layer 3 and the third epitaxial layer 6.In second photoresist layer
Upper surface the first injection region 8 of the first conduction type is formed using the method for ion implanting and/or diffusion, then remove conductive the
Two photoresist layers.Further, ion implanting and/or diffusion boron element or indium are used in the upper surface of second photoresist layer
The method of any combination of element or aluminium element or three forms the first injection region 8 of the first conduction type, then removes conductive the
Two photoresist layers.Preferably, the doping concentration of the buried layer 3 is greater than or equal to the doping concentration of first injection region 8, at this time
The resistivity of the buried layer 3 is less than or equal to first injection region 8, so that electric current arrives outside described first along the buried layer 3
Prolong 2 downside of layer.In addition, first injection region 8 and the buried layer 3 are heavy doping, the third epitaxial layer 6 is also heavily doped
It is miscellaneous, therefore first injection region 8 is reacted with the buried layer 3 and the third epitaxial layer 6, forms the PN of high-dopant concentration
Knot.
Attached drawing 8 is please referred to, executes step S6, specially：Formed through second epitaxial layer 4 and with first extension
The third groove 9 of 2 connection of layer.In some embodiments of the invention, exposure mask material is prepared in the upper surface of second epitaxial layer 4
Material, the mask material is specially third photoresist, is formed on first photoresist layer by etching and runs through described second
Epitaxial layer 4 and the third groove 9 connecting with first epitaxial layer 2, remove the third photoresist layer.Wherein, the side of etching
Method includes dry etching and wet etching, it is preferred that the method for the etching used is dry etching, and dry etching includes that light is waved
Hair, gaseous corrosion, plasma etching etc., and dry etching easily realizes that automation, treatment process are not introduced into pollution, cleannes
It is high.Further, the quantity of the third groove 9 is at least two, and the third groove 9 is adjacent to first injection region
8 and it is away from the third epitaxial layer 6.In some embodiments of the invention, the third groove 9 runs through second extension
Layer 4 is simultaneously connect with first epitaxial layer 2, for example, the third groove 9 is through second epitaxial layer 4 and extends to described
First epitaxial layer 2 or the third groove 9 connect through second epitaxial layer 4 and with the upper surface of first epitaxial layer 2
It connects, guarantees that the third groove 9 is contacted with first epitaxial layer 2.
Attached drawing 9 is please referred to, executes step S7, specially：The first part of dielectric layer 10 is formed in the third groove 9
101.The dielectric layer 10 is insulating layer, and sputtering can be used for the dielectric layer 10 or thermal oxide is formed.Of the invention some
In embodiment, the dielectric layer 10 is the silicon oxide layer that thermal oxide is formed, and in subsequent doping step, the silicon oxide layer is made
For protective layer, and by the interlayer insulating film as resulting devices.Specifically, the first part 101 is to be filled in described the
Dielectric layer in three grooves 9, the first part 101 extend to the upper table of second epitaxial layer 4 out of described third groove 9
Face.
Further, it is formed in the third groove 9 after the first part 101 of dielectric layer 10, further includes：Described
The second part 102 of second epitaxial layer, 4 upper surface formation dielectric layer 10.The second part 102 covers second epitaxial layer 4
Lid, and it is equipped with certain thickness, and the first part 101 and 102 connection of second part.Institute in the dielectric layer 10
It states first part 101 and the second part 102 plays the role of that electric current and insulation is isolated.Furthermore it is also possible in the third
The of dielectric layer 10 is formed in 4 upper surface of the second epitaxial layer while forming first part 101 of dielectric layer 10 in groove 9
Two parts 102.
Attached drawing 10 is please referred to, executes step S8, specially：Polysilicon layer 11 is formed in the second groove 7, it will be described
Polysilicon layer 11 extends to the upper surface of the third epitaxial layer 6 out of described second groove 7.Based on above-mentioned steps S7, in shape
During at the dielectric layer 10, thermal oxide has also been carried out in the second groove 7, has formed the third of the dielectric layer 10
Part, the Part III include the upper surface that the third epitaxial layer 6 is extended to out of described second groove 7, i.e., will be described
The all filled media layer of second groove 7.It is formed by the method for etching and removes the Part III, the method for etching includes dry method
Etching and wet etching, it is preferred that the method for the etching used is wet etching, and wet etching is easy to operate, to equipment requirement
Selectivity that is low, being easily achieved mass production, and etch might as well.Wet etching removes the Part III, reaches
Self aligned effect.The polysilicon layer 11, the polycrystalline are formed by the method for extension or diffusion in the second groove 7
P-type doping is generally in silicon layer 11.Specifically, the extension or the method for diffusion include depositing operation.Of the invention some
In embodiment, depositing operation can be used in 1 upper surface of substrate and form first epitaxial layer 2, for example, depositing operation can
To be selected from one of electron beam evaporation, chemical vapor deposition, atomic layer deposition, sputtering.Preferably, on the substrate 1
Use low-pressure chemical vapor deposition (abbreviation LPCVD, i.e. Low Pressure Chemical Vapor Deposition) shape
At the polysilicon layer 11, the purity is high of the polysilicon layer 11 of formation, uniformity is good.
Attached drawing 11 is please referred to, executes step S09, specially：Formed respectively with second epitaxial layer 4 and the polysilicon
The first electrode 14 of 11 connection of layer；The second electrode 15 connecting with the substrate 1 is formed in the lower surface of the substrate 1.It is described
First electrode 14 is electrically connected with second epitaxial layer 4, so that circuit flows to second epitaxial layer 4 and first epitaxial layer
2 access, to form PN junction.The first electrode 14 is also connected with the polysilicon layer 11, by third described in conduct current
In epitaxial layer 6 and buried layer 3.1 lower surface of substrate is metallized, second metal layer 13 is formed, thus formation and institute
State the second electrode 15 of the electrical connection of substrate 1.The electric current flows to external electrical along the second electrode 15 by the substrate 1
Road.
Further, the first electrode 14 connecting with second epitaxial layer 4 and the polysilicon layer 11 respectively is formed to have
Body includes：The first electrode 14 is formed in 10 upper surface of dielectric layer, the polysilicon layer 11 is run through described second
Divide 102 and is filled into the second groove 7.Based on above-mentioned steps S8, during forming the dielectric layer 10, described
Thermal oxide has also been carried out in two grooves 7, has formed the Part III of the dielectric layer 10, the Part III includes from described second
102 upper surface of second part that the dielectric layer 10 is extended in groove 7, i.e., be filled into described second for the polysilicon layer 11
In groove 7.It being formed by the method for etching and removes the Part III, the method for etching includes dry etching and wet etching,
Preferably, the method for the etching used is wet etching, wet etching is easy to operate, it is low for equipment requirements, be easily achieved it is large quantities of
Amount production, and the selectivity etched might as well.Wet etching removes the Part III, has reached self aligned effect.?
The polysilicon layer 11, generally P in the polysilicon layer 11 are formed by the method for extension or diffusion in the second groove 7
Type doping.Likewise, forming the polysilicon layer 11, the institute of formation using low-pressure chemical vapor deposition on the substrate 1
The purity is high of polysilicon layer 11 is stated, uniformity is good.
Further, the first electrode 14 connecting with second epitaxial layer 4 and the polysilicon layer 11 respectively is formed to have
Body includes：The first electrode 14 is connected through the second part 102 and with second epitaxial layer 4.By described
A part 101 is used as mask material, specifically, will be located at the silicon oxide layer of 4 upper surface of the second epitaxial layer as exposure mask material
Material, etching form the first contact hole 103 and the second contact hole 104.Preferably, lithographic method includes dry etching, dry etching
Including photoablation, gaseous corrosion, plasma etching etc., and dry etching easily realize automation, treatment process be not introduced into pollution,
Cleannes are high.Preferably, first contact hole 103 and second contact hole 104 respectively with 4 surface of the second epitaxial layer
Connection specifically forms the first metal layer 12 in 102 upper surface of second part, the first metal layer 12 further includes filling out
The part in first contact hole 103 and second contact hole 104 is filled, the first metal layer 12 forms described first
Electrode 14, the first electrode 14 pass through first contact hole 103, second contact hole 104 and second epitaxial layer 4
Realize electrical connection in surface.The quantity of first contact hole 103 and second contact hole 104 is at least one.
Below in conjunction with Fig. 1 to Figure 12 to a kind of power device protection chip provided in an embodiment of the present invention and its equivalent circuit
It is described in detail.
Shown in equivalent circuit diagram as shown in figure 12, present invention implementation provides a kind of power device protection chip, shown function
Rate device protection chip include：
The substrate 1 of first conduction type；
First epitaxial layer 2 of the first conduction type, is grown on 1 upper surface of substrate, and the doping concentration of the substrate 1 is high
In the doping concentration of first epitaxial layer 2；
The buried layer 3 of first conduction type is formed in first epitaxial layer 2, and at least partly surface of the buried layer 3
It is exposed to 2 upper surface of the first epitaxial layer, the doping concentration of the buried layer 3 is higher than the doping concentration of first epitaxial layer 2；
Second epitaxial layer 4 of the second conduction type is formed in 2 upper surface of the first epitaxial layer；
The third epitaxial layer 6 of second conduction type is connect through second epitaxial layer 4 and with the buried layer 3；
Dielectric layer 10, the first part 101 including extending to first epitaxial layer 2 through second epitaxial layer 4；
Polysilicon layer 11 is formed in the third epitaxial layer 6 and extends to 6 upper surface of third epitaxial layer；
First electrode 14 is connect with second epitaxial layer 4 and the polysilicon layer 11 respectively；
Second electrode 15 is formed in the lower surface of the substrate 1 and connect with the substrate 1.
It is understood that the first groove 5 is deep trench, by being formed in 5 side wall of first groove and bottom surface
The third epitaxial layer 6 of second conduction type, and the polysilicon layer 11, the polycrystalline are formed in the second groove 7
For silicon layer 11 for discharging, the third epitaxial layer 6 and the buried layer 3 form PN junction, specifically, the bottom surface of the groove with it is described
Buried layer 3 is reacted, so as to form a conductive path.Dielectric layer 10 is formed in the third groove 9 simultaneously, it is described
The dielectric layer 10 formed in third groove 9 plays the role of isolation, reduces parasitic capacitance.
Specifically, the substrate 1 is the carrier in integrated circuit, and the substrate 1 plays the role of support, the substrate 1
Also assist in the work of the integrated circuit.The substrate 1 can be silicon substrate, or Sapphire Substrate can also be carbon
Silicon substrate, it might even be possible to be silicon Chu substrate, it is preferred that the substrate 1 is silicon substrate, this is because silicon substrate material is with low
Cost, large scale, conductive feature, avoid edge effect, can increase substantially yield.
Specifically, first conduction type is one of p-type doping and n-type doping, and second conduction type is P
Type doping and the another kind in n-type doping.
Referring next to attached drawing, the structure and its equivalent circuit of power device described above protection chip are explained in detail
It states.
For convenience of description, spy illustrates herein：First conduction type can be n-type doping, so that described second is conductive
Type is p-type doping；First conduction type can also adulterate for p-type, so that second conduction type is n-type doping.
It is understood that when first conduction type is n-type doping, when second conduction type is that p-type is adulterated, the substrate
1, first epitaxial layer 2, the buried layer 3 and first injection region 8 are p-type doping, second epitaxial layer 4 and described
Third epitaxial layer 6 is N-type epitaxy layer.When first conduction type is p-type doping, second conduction type is mixed for N-type
When miscellaneous, the substrate 1, first epitaxial layer 2, the buried layer 3 and first injection region 8 are n-type doping, and described second
Epitaxial layer 4 and the third epitaxial layer 6 are p-type epitaxial layer.Preferably, first conduction type is p-type doping, described the
Two conduction types are n-type doping, because the effective mass in hole is small, mobility is small, thus more difficult conduction, opposite N-type material
For material, resistivity wants high, and as P type substrate, typically grounded current potential forms reverse biased pn junction with epitaxial layer.In next reality
Apply in example, using first conduction type as p-type adulterate, second conduction type be n-type doping for be described, but
It is defined not to this.
Specifically, P type substrate and p-type extension belong to P-type semiconductor, and N-type substrate and N-type extension belong to N-type and partly lead
Body.The P-type semiconductor is the silicon wafer for adulterating triad, such as any group of boron element or phosphide element or aluminium element or three
It closes.The N-type semiconductor is any combination of the silicon wafer for adulterating pentad, such as P elements or arsenic element or both.
In some embodiments of the invention, as shown in Figures 2 and 3, the power device protection chip is led including first
The substrate 1 of electric type and the first epitaxial layer 2 of the first conduction type, first epitaxial layer 2 are grown on table on the substrate 1
Face.Preferably, the doping concentration of the substrate 1 is higher than the doping concentration of first epitaxial layer 2, at this time first epitaxial layer
The resistivity of substrate 1 described in 2 resistivity ratio is high, reduces dead resistance, to improve the breakdown reverse voltage of device.
In some embodiments of the invention, as shown in figure 3, power device protection chip further includes the first conductive-type
The buried layer 3 of type, the buried layer 3 are formed in first epitaxial layer 2, and at least partly surface exposure of the buried layer 3 is in institute
State 2 upper surface of the first epitaxial layer.Preferably, the doping concentration of the buried layer 3 is higher than the doping concentration of first epitaxial layer 2,
And buried layer 3 is heavy doping, to further promote the breakdown reverse voltage of device.Further, mixing due to the substrate 1
Miscellaneous concentration is higher than the doping concentration of first epitaxial layer 2, so that the resistivity of the epitaxial layer is higher than the resistance of the substrate 1
Rate increases the buried layer 3 of heavy doping, so that the doping concentration of the substrate 1 between the substrate 1 and first epitaxial layer 2
Higher than the doping concentration of the buried layer 3.The resistivity of the buried layer 3 is lower than the resistivity of first epitaxial layer 2, and electric current can edge
The low buried layer 3 of resistivity to first epitaxial layer, 2 downside, to change current path, be equivalent to and reduce series electrical
Resistance.
In some embodiments of the invention, as shown in figure 4, power device protection chip further includes the second conductive-type
Second epitaxial layer 4 of type, second epitaxial layer 4 are formed in 2 upper surface of the first epitaxial layer.Second epitaxial layer 4 with
The conduction type of first epitaxial layer 2 is different, and second epitaxial layer 4 is used to form PN junction with first epitaxial layer 2.More
Specifically, second epitaxial layer 4 is located at the side point that at least two third grooves 9 are away from first injection region 8
At least two PN junctions are not formed with first epitaxial layer 2.
In some embodiments of the invention, as shown in Figure 5 and Figure 6, the power device protection chip further includes second
The third epitaxial layer 6 of conduction type, the third epitaxial layer 6 are connect through second epitaxial layer 4 and with the buried layer 3.Institute
The outside that third groove 9 is located at the third epitaxial layer 6 is stated, the third groove 9 is for filling the third epitaxial layer 6.Institute
The quantity for stating third groove 9 is at least two, due to the first part 101 in the third groove 9 by first injection region 8 with
Second epitaxial layer 4 is isolated, so second epitaxial layer 4 is separate with described first in at least two third grooves 9
The side of injection region 8 is contacted with first epitaxial layer 2.Specifically, the bottom surface of the third epitaxial layer 6 and 3 phase of buried layer
Connection, for example, the bottom surface of the third epitaxial layer 6 is located in the buried layer 3, the bottom surface of the third epitaxial layer 6 can also be with
The surface of the buried layer 3 connects, and guarantees the bottom surface of the third epitaxial layer 6 and the contact of the buried layer 3, makes electric current from described the
Three epitaxial layers 6 flow to the buried layer 3, so that the bottom surface of the third epitaxial layer 6 is reacted with the buried layer 3, form PN junction.
6 concrete shape of third epitaxial layer is groove, and those skilled in the art can select not similar shape according to the electric property of device
The shape of the groove of shape, the groove can be rectangle groove, can also can also be U-shaped groove with square trench, it might even be possible to
For ball cunette slot, etc..
Further, as shown in fig. 7, power device protection chip further includes the first injection region of the first conduction type
8, first injection region 8 is formed in second epitaxial layer 4 and is connected with the buried layer 3 and the third epitaxial layer 6.
Specifically, first injection region 8 through second epitaxial layer 4 and extends to the upper surface of second epitaxial layer 4 under
Surface.More specifically, the quantity at least two of first injection region 8, first injection region 8 is located at the third
The two sides of epitaxial layer 6 are simultaneously contacted with the third epitaxial layer 6.In addition, first injection region 8 of the first conduction type and described
Buried layer 3 is heavy doping, and the third epitaxial layer 6 of the second conduction type is also heavy doping, thus first injection region 8 with
The buried layer 3 and the third epitaxial layer 6 are reacted, and the PN junction of high-dopant concentration is formed, wherein the third epitaxial layer 6
It is at least one with the quantity of the buried layer 3, therefore the quantity of the PN junction of the high-dopant concentration is at least one.It needs to illustrate
, what the breakdown voltage of the PN junction of the high-concentration dopant was formed lower than second epitaxial layer 4 with first epitaxial layer 2
What the breakdown voltage of PN junction, the PN junction of the high-dopant concentration and second epitaxial layer 4 and first epitaxial layer 2 were formed
The quantitative proportion of PN junction is 1:2, the diode for being now placed in intermediate high-dopant concentration can be prior to second epitaxial layer 4 and institute
The diode for stating the formation of the first epitaxial layer 2 is opened.The diode that first epitaxial layer 2 is formed is for reducing capacitor.
In some embodiments of the invention, as shown in figure 8, power device protection chip further includes dielectric layer 10,
The dielectric layer 10 includes the first part 101 that first epitaxial layer 2 is extended to through second epitaxial layer 4.Specifically,
The first part 101 is adjacent to first injection region 8 and is away from the third epitaxial layer 6.The of the dielectric layer 10
A part 101 is for second epitaxial layer 4 and first injection region 8 to be individually insulated, so that improved power device
Part protects chip to reduce capacitor, guarantees that the PN junction of 101 two sides of first part is in parallel.In some embodiments of the invention,
The first part 101 can not contact with the buried layer 3, and the first part 101 can also contact with buried layer 3, not influence
The normal work of the device.101 concrete shape of first part is groove, and those skilled in the art can be according to device
Electric property selects groove of different shapes, and the shape of the groove can be rectangle groove, can also be with square trench, can be with
For U-shaped groove, it might even be possible to for ball cunette slot, etc..
Further, the dielectric layer 10 further includes the second part 102 positioned at 4 upper surface of the second epitaxial layer.Institute
The second part 102 of dielectric layer 10 is stated for second epitaxial layer 4 to be isolated with the first electrode 14.
In some embodiments of the invention, as shown in figure 9, power device protection chip further includes polysilicon layer
11, the polysilicon layer 11 is formed in the third epitaxial layer 6 and extends to 6 upper surface of third epitaxial layer.The device
Part monocrystalline silicon multi-purpose greatly is made, and the polysilicon layer 11 is connect with 6 surface of third epitaxial layer, so that discharging efficiency is higher.
Specifically, the polysilicon layer 11 has very high compatibility in monocrystalline silicon.
Further, the first electrode 14 is formed in 102 upper surface of second part, and the polysilicon layer 11 runs through
The second part 102, so that the upper surface of the polysilicon layer 11 is directly contacted with the first electrode 14, formation is electrically connected
It connects, so that electric current is conductive rapidly by polysilicon layer 11.
In some embodiments of the invention, as shown in Figure 10, the power device protection chip further includes first electrode
14 and second electrode 15, the first electrode 14 connect respectively with second epitaxial layer 4 and the polysilicon layer 11, described
Two electrodes 15 are formed in the lower surface of the substrate 1 and connect with the substrate 1.Specifically, the first electrode 14 is specially
The first metal layer 12, the first metal layer 12 include the layer gold for being covered in 102 upper surface of second part of the dielectric layer 10
The block metal for belonging to and being connect with 4 upper surface of the second epitaxial layer.The layer metal and described block of metal are interconnected, in order to
The quick transmitting of electronics.The second electrode 15 is specially the second metal layer 13, and the second metal layer 13 covers described
The lower surface of substrate 1, and it is equipped with certain thickness.The second electrode 15 also forms the relationship being electrically connected with the substrate 1.
Specifically, the first contact hole 103 and the second contact hole 104 are offered in the first part 101, described first connects
Contact hole 103 is connect with 4 surface of the second epitaxial layer respectively with second contact hole 104, and the first electrode 14 is specially
The first metal layer 12, the first metal layer 12 include and first contact hole 103 and 104 connection of the second contact hole
Part, the first electrode 14 pass through first contact hole 103 and second contact hole 104 and second epitaxial layer 4
Surface electrical connection.First contact hole 103 and second contact hole 104 ensure that PN junction and the institute of the high-dopant concentration
It states the second epitaxial layer 4 and forms parallel circuit with the PN junction that first epitaxial layer 2 is formed, reduce parasitic capacitance, while can also
It is conductive.
Further, the first electrode 14 is connect through the second part 102 and with second epitaxial layer 4.Institute
The quantity for stating block metal is at least two, and described block of metal is specifically the first contact hole 103 offered in the second part 102
With metal layer formation is filled in the second contact hole 104 respectively, therefore form the first electrode 14 through described second
The relationship dividing 102 and being connect with second epitaxial layer 4.More specifically, the first electrode 14 and second extension
Layer 4 is connected, and mode can not be unique, for example, the first electrode 14 is contacted from first contact hole 103 and described second
Hole 104 extends respectively to 4 surface of the second epitaxial layer, and the first electrode 14 can also be from 103 He of the first contact hole
Second contact hole 104 extends respectively in second epitaxial layer 4, guarantees the first electrode 14 and second extension
Layer 4 contacts.
Please refer to the equivalent circuit diagram of the protection chip structure of power device shown in Figure 12.When to 14 He of first electrode
When the second electrode 15 is powered, the electric current flows to the second electrode 15 from the first electrode 14.It should be noted that
The forward and reverse of PN junction formed below is set as p-type with the first conduction type, and second conduction type is set as N-type as this
One embodiment of invention does not limit this to be judged.The third epitaxial layer 6 passes through described the of two sides respectively
One injection region 8 and the buried layer 3 contacted with the third epitaxial layer 6 form the PN junction of a high-dopant concentration, and the electric current once leads to
Cross first electrode 14, the polysilicon layer 11, the third epitaxial layer 6, the buried layer 3, first epitaxial layer 2, the lining
Bottom 1 and the second electrode 15, to form the equivalent circuit of reversed first diode a.Second epitaxial layer 4 is located at
The side that the third groove 9 is away from first injection region 8 forms two PN junctions, institute with first epitaxial layer 2 respectively
Electric current is stated once by first contact hole 103 and second contact hole 104, described second in the first electrode 14
Epitaxial layer 4, first epitaxial layer 2, the substrate 1 and the second electrode 15, so that formation is with the first diode a
The equivalent circuit of the symmetrical second diode b of axis.The first diode a and the second diode b is in parallel.Described first
The quantitative proportion of diode a and the second diode b are 1:2, the first diode a can be prior to the described 2nd 2 at this time
Pole pipe b is opened, and the second diode b is for reducing capacitor.On the whole, three groups of diodes are formd in the present embodiment simultaneously
The equivalent circuit of connection.
The technical scheme of the present invention has been explained in detail above with reference to the attached drawings, and improve makes 3 groups according to the technical solution of the present invention
Power device protects integrated chip to together, reduces device area by introducing 3 technique of buried layer, reduces technology difficulty, subtract
Small device manufacturing cost.Three groups of diodes in parallel, reduce parasitic capacitance, so that improved power device protection chip
Protection feature and reliability are all improved.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of power device protects chip, which is characterized in that including：
The substrate of first conduction type；
First epitaxial layer of the first conduction type, is grown on the upper surface of substrate, and the doping concentration of the substrate is higher than described
The doping concentration of first epitaxial layer；
The buried layer of first conduction type is formed in first epitaxial layer, and at least partly surface exposure of the buried layer in
First epitaxial layer upper surface, the doping concentration of the buried layer are higher than the doping concentration of first epitaxial layer；
Second epitaxial layer of the second conduction type is formed in first epitaxial layer upper surface；
The third epitaxial layer of second conduction type is connect through second epitaxial layer and with the buried layer；
Dielectric layer, the first part including extending to first epitaxial layer through second epitaxial layer；
Polysilicon layer is formed in the third epitaxial layer and extends to third epitaxial layer upper surface；
First electrode is connect with second epitaxial layer and the polysilicon layer respectively；
Second electrode is formed in the lower surface of the substrate and connect with the substrate.
2. power device according to claim 1 protects chip, which is characterized in that the power device protection chip also wraps
Include the first injection region of the first conduction type, first injection region be formed in second epitaxial layer and with the buried layer and
The third epitaxial layer is connected.
3. power device according to claim 1 protects chip, which is characterized in that the dielectric layer further includes positioned at described
The second part of second epitaxial layer upper surface.
4. power device according to claim 3 protects chip, which is characterized in that the first electrode, which is formed in, to be given an account of
Matter layer upper surface, the polysilicon layer is through the second part to connect the first electrode.
5. power device according to claim 4 protects chip, which is characterized in that the first electrode runs through described second
Part is simultaneously connect with second epitaxial layer.
6. a kind of production method of power device protection chip comprising：
In the first epitaxial layer of one conduction type of upper surface of substrate growth regulation of the first conduction type, the doping concentration of the substrate
Higher than the doping concentration of first epitaxial layer；
The buried layer of the first conduction type is formed in first epitaxial layer, at least partly surface exposure of the buried layer is in described
The upper surface of first epitaxial layer, the doping concentration of the buried layer are higher than the doping concentration of first epitaxial layer；
The second epitaxial layer of the second conduction type is formed in first epitaxial layer upper surface；
The first groove of the buried layer is formed through second epitaxial layer and extended in second epitaxial layer；
The third epitaxial layer of the second conduction type is formed in the first groove side wall and bottom surface, makes the third epitaxial layer and institute
Buried layer connection is stated, and forms second groove in the third epitaxial layer；
Form the third groove for running through second epitaxial layer and connecting with first epitaxial layer；
The first part of dielectric layer is formed in the third groove；
Polysilicon layer is formed in the second groove, the polysilicon layer is extended into the third out of described second groove
The upper surface of epitaxial layer；
Form the first electrode connecting respectively with second epitaxial layer and the polysilicon layer；
The second electrode connecting with the substrate is formed in the lower surface of the substrate.
7. a kind of production method of power device protection chip according to claim 6, which is characterized in that described first
Epitaxial layer upper surface is formed after the second epitaxial layer of the second conduction type, further includes：
Form the first injection region of the first conduction type in second epitaxial layer, first injection region and the buried layer and
The third epitaxial layer is connected.
8. a kind of production method of power device protection chip according to claim 6, which is characterized in that in the third
It is formed in groove after the first part of dielectric layer, further includes：
The second part of the dielectric layer is formed in second epitaxial layer upper surface.
9. a kind of production method of power device protection chip according to claim 8, which is characterized in that described formed is divided
The first electrode not connecting with second epitaxial layer and the polysilicon layer specifically includes：
The first electrode is formed in the dielectric layer upper surface, the polysilicon layer through the second part and is connected into institute
State first electrode.
10. a kind of production method of power device protection chip according to claim 9, which is characterized in that the formation
The first electrode connecting respectively with second epitaxial layer and the polysilicon layer specifically includes：
The first electrode is connected through the second part and with second epitaxial layer.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| EP0001574A1 (en) * | 1977-10-25 | 1979-05-02 | International Business Machines Corporation | Semiconductor device for resistance structures in high-density integrated circuits and method for making it |
| JPS57201070A (en) * | 1981-06-05 | 1982-12-09 | Seiko Epson Corp | Semiconductor device |
| JP2000312013A (en) * | 1999-04-26 | 2000-11-07 | Rohm Co Ltd | Schottky barrier semiconductor device |
| US20030168701A1 (en) * | 2002-03-08 | 2003-09-11 | International Business Machines Corporation | Method and structure for low capacitance ESD robust diodes |
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2018
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0001574A1 (en) * | 1977-10-25 | 1979-05-02 | International Business Machines Corporation | Semiconductor device for resistance structures in high-density integrated circuits and method for making it |
| JPS57201070A (en) * | 1981-06-05 | 1982-12-09 | Seiko Epson Corp | Semiconductor device |
| JP2000312013A (en) * | 1999-04-26 | 2000-11-07 | Rohm Co Ltd | Schottky barrier semiconductor device |
| US20030168701A1 (en) * | 2002-03-08 | 2003-09-11 | International Business Machines Corporation | Method and structure for low capacitance ESD robust diodes |
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