CN108922850A - A kind of Y gate transistor device manufacturing method and transistor device - Google Patents

A kind of Y gate transistor device manufacturing method and transistor device Download PDF

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Publication number
CN108922850A
CN108922850A CN201810577762.6A CN201810577762A CN108922850A CN 108922850 A CN108922850 A CN 108922850A CN 201810577762 A CN201810577762 A CN 201810577762A CN 108922850 A CN108922850 A CN 108922850A
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metal
layer
grid
transistor device
photoresist
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CN108922850B (en
Inventor
吴淑芳
许孟凯
陈智广
陈胜男
林伟铭
林张鸿
林豪
詹智梅
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UniCompound Semiconductor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The present invention discloses a kind of Y gate transistor device manufacturing method and transistor device, including step：In the upper coated polymer layer of the epitaxial wafer with the first metal layer, Y grid metal, the first nitride layer and the second nitride layer；Exposure development at drain metal, source metal and Y grid top position on polymeric layer to form opening；Etching removal drain metal, the second nitride layer of source metal and the first nitride layer and the second nitride layer at Y grid position.Above-mentioned technical proposal passes through the coated polymer layer on the epitaxial wafer with Y grid metal, and it is open at drain metal, source metal and Y grid top position, when carrying out metal evaporation, then can drain metal, source metal the first metal layer at the top of and Y grid top position upper metal layer is deposited simultaneously, reduce the step process of manufacture craft, efficiency is not only increased, cost is also reduced.

Description

A kind of Y gate transistor device manufacturing method and transistor device
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of Y gate transistor device manufacturing method and crystal Tube device.
Background technique
The production process of Y gate transistor device before present invention improvement is as shown in Figure 1, will generally undergo following technique：Outside Prolong piece surface treatment and photoetching work at the top of device source electrode/drain metallization processes --- Y grid bottom photoetching process --- Y grid Skill --- Y grid metal depositing operation --- the first passivation layer nitride deposition process --- the first metal layer depositing operation --- Second passivation layer nitride deposition process --- the flat layer process of polymer inactivation --- second metal layer depositing operation --- Three passivation layer nitride deposition process etc..In order to promote the electric conductivity at Y grid, since Y gate length is fixed, then need to increase Y grid Cross-sectional area, also need to increase after the first metal layer depositing operation a step of step Y grid metal elevates at this time, i.e., in Y grid The metal deposit of upper progress again, will increase by one of Y grid metal more at this time and elevate depositing operation.Per pass technique includes more again A treatment process, such as surface clean, exposure development, metallization or etching deposit.In this way, the Y gate transistor that production is increased Device needs to undergo more processing step.
Summary of the invention
For this reason, it may be necessary to provide a kind of Y gate transistor device manufacturing method and transistor device, existing Y gate semiconductor is solved The more problem of making step.
To achieve the above object, a kind of Y gate transistor device manufacturing method is inventor provided, is included the following steps：
In the upper coating of the epitaxial wafer with the first metal layer, Y grid metal, the first nitride layer and the second nitride layer One photoresist；
Exposure development at drain metal, source metal and Y grid top position on the first photoresist to form opening；
Etching removal drain metal, the second nitride layer of source metal and the first nitride layer at Y grid position and the Second nitride layer；
Coated polymer；
Exposure development at drain metal, source metal and Y grid top position on polymer to form opening；
Coat the second photoresist；
Exposure development at drain metal, source metal and Y grid top position on the second photoresist to form opening；
Metal evaporation deposition is carried out, Y grid is formed in Y grid top position and elevates metal, in drain metal, source metal position Form second metal layer；
Etching the second photoresist of removal.
It further, further include step：Third nitride layer is deposited, and the second gold medal is exposed in etching on third nitride layer Belong to layer top position.
Further, the epitaxial wafer includes semiconductive material substrate layer, the FET device stacked gradually Structure sheaf.
Further, second photoresist is negative photoresist.
And the present invention also provides a kind of Y gate transistor device, the transistor device by above-mentioned any one a kind of Y Gate transistor device manufacturing method is made.
Further, the Y grid elevate metal height and the second metal layer height phase at drain metal, source metal Together.
Be different from the prior art, above-mentioned technical proposal by coating the first photoresist on the epitaxial wafer with Y grid metal, And be open at drain metal, source metal and Y grid top position, when carrying out metal evaporation, then it can drain Upper metal layer is deposited in metal, the first metal layer top of source metal and Y grid top position simultaneously, and evaporated metal layer can be two Secondary vapor deposition then forms second metal layer, also increases the cross-sectional area on Y significantly, thus once realizes the prior art In " Y grid elevate metallic deposition technique " " second metal layer depositing operation " metal layer vapor deposition, reduce manufacture craft Steps flow chart not only increases efficiency, also reduces cost.
Detailed description of the invention
Fig. 1 is the production flow diagram of transistor device described in background technique；
Fig. 2 is the structure chart of the transistor device before improving；
Fig. 3 is the structure chart of the transistor device before improving；
Fig. 4 is the structure chart of the transistor device before improving；
Fig. 5 is the structure chart of the transistor device before improving；
Fig. 6 is the production flow diagram of the transistor device of the embodiment of the present invention；
Fig. 7 is the structure chart of the transistor device of the embodiment of the present invention；
Fig. 8 is the structure chart of the transistor device of the embodiment of the present invention；
Fig. 9 is the structure chart of the transistor device of the embodiment of the present invention；
Figure 10 is the structure chart of the transistor device of the embodiment of the present invention.
Description of symbols：
1, epitaxial wafer.10, semiconductive material substrate layer；11, FET device structure sheaf；
D, drain metal (drain ohmic contact metal)；S, source metal (source electrode metal ohmic contact)；
2, photoresist, 3, photoresist, 4, metal, 40, Y grid metal；41, Y grid elevate metal.
5, the first nitride layer, the 50, second nitride layer；51, third nitride layer；6, photoresist, 7, the first metal layer, 9, second metal layer；90, second metal layer first time deposited metal；91, second of deposited metal of second metal layer；8, it polymerize Object；22, the second photoresist；24, the first metal layer, 27, source drain the first metal layer.
Specific embodiment
Technology contents, construction feature, the objects and the effects for detailed description technical solution, below in conjunction with specific reality It applies example and attached drawing is cooperated to be explained in detail.
The english nouns being likely to occur are illustrated first：
1.YGB：Y-Gate Bottom, Y grid bottom photoetching process；
2.YGT：Photoetching process at the top of Y-Gate Top, Y grid；
3.YGD：Y-Gate Deposition, Y grid metal depositing operation；
4.1PN：1st Passivation Nitride, the first passivation layer nitride deposition process；
5.1MD：1st Metal Deposition, the first metal layer depositing operation；
6.2PN：2nd Passivation Nitride, the second passivation layer nitride deposition process；
7.PP：Polyimide Passivation, the flat layer process of polymer inactivation；
8.2MD：2nd Metal Deposition, second metal layer depositing operation；
9.3PN：3rd Passivation Nitride, third passivation layer nitride deposition process.
Fig. 1 to Figure 10 is please referred to, a kind of Y gate transistor device manufacturing method is present embodiments provided, is introducing this implementation Before example, the technology before first improving the present embodiment is illustrated.Firstly, to carry out Y grid bottom photoetching process：On epitaxial wafer 1 Photoresist 2 is coated, and is open at Y grid position, is i.e. the middle opening in epitaxial wafer 1 as shown in Figure 2, original in this way one layer Photoresist 2 is split into left and right two parts, and forms a recess in middle position.It is then photoetching process at the top of Y grid：After Continuous coating photoresist 3, is open, the recess in Y grid position just has certain depth so equally at Y grid position.And carry out Y Grid metal depositing operation：Metal evaporation is carried out, then can plate 4 He of metal on the surface of photoresist 3 and the recess of Y grid position Metal 40 forms the structure as Fig. 2.Then by chemical reaction removal photoresist 2 and photoresist 3, it is left with metal 40, that is, form somewhat as shown in Figure 3 is generated similar to the Y grid metal of Y-shaped.
After generating Y grid metal, to continue in the source electrode position (shown in the S of Fig. 2) of epitaxial wafer and the drain locations (D of Fig. 2 Shown in) generate the first metal 7.It first has to carry out the first passivation layer nitride deposition process：Continue to apply in the on piece of Fig. 3 first Nitride layer 5 is covered, the nitride at source/drain position is then etched away after photoresist obstructs, exposes source/drain gold Belong to.Then carry out the first metal layer depositing operation：Photoresist 6 is coated again, and is open at source/drain position, and it is laggard Row metal vapor deposition, then plate metal 7 at photoresist 6, source/drain position, as shown in Figure 4.Final etch removes photoresist 6, then the metal 7 above photoresist 6 and photoresist 6 is removed, and retains the metal 7 at source/drain position.
Finally carry out the second passivation layer nitride deposition process --- the flat layer process of polymer inactivation --- second metal Layer depositing operation --- third passivation layer nitride deposition process and etc., just form final semiconductor junction as shown in Figure 5 Structure.Wherein, since there is larger recess in position between Y grid and the first metal layer of source/drain in the device architecture of Fig. 4, in this way Need very thick photoresist that could form difference in height after photoetching development, this cannot achieve existing technique.It then can be in Y grid The flat layer process of polymer inactivation (Polyimide Passivation) is carried out between the first metal layer of source/drain, is filled out Fill polymer 8 with so that more flat between Y grid and the first metal layer, can then carry out photoresist coating, development etching and Metal evaporation processing step.
The transistor device manufacturing method of the present embodiment can refer to Fig. 6.Specifically comprise the following steps：It is referred to first Existing device fabrication steps produce transistor device as shown in Figure 5 with polymer inactivation flatness layer 8, at this time also not Start the production of second metal layer 9 and third nitride layer 51.The final step of the prior art is the first step that the present invention starts： In the first photoetching of upper coating of the epitaxial wafer with the first metal layer, Y grid metal, the first nitride layer and the second nitride layer Glue；Exposure development at drain metal, source metal and Y grid top position on a photoresist to form opening；Etching removal leakage The first nitride layer and the second nitride layer at pole metal, the second nitride layer of source metal and Y grid position；Coating polymerization Object 8；Exposure development at drain metal, source metal and Y grid top position on polymer to form opening；Coat the second light Photoresist (i.e. in Fig. 7)；Exposure development at drain metal, source metal and Y grid top position on the second photoresist to form Opening；Metal evaporation deposition is carried out, Y grid is formed in Y grid top position and elevates metal, in drain metal, source metal position shape At second metal layer；Form the structure such as Fig. 7.Etching the second photoresist of removal, just forms the structure such as Fig. 8, thus outside Prolong the drain metal of on piece, the first metal layer top of source metal and Y grid top position and crosses second metal layer 70 respectively Metal 41 is elevated with Y grid.By this method, Y grid elevate metal and source drain can be realized on primary vapor deposition Two metal layers, without carrying out multiple metal evaporation.Due to that will be cleaned before each metal evaporation, photoresist is coated, is exposed Multiple steps such as photodevelopment, then method of the invention can greatly reduce the processing step of production process, improve production efficiency With reduce costs.
The third passivation layer nitride deposition process of technique before can then improving, as shown in Figure 9.? To produce final semiconductor structure, as shown in Figure 10.
It is as described above, subsequent nitride deposition process to be carried out to the second metal layer of Y grid and source/drain, Then this method further includes step：Third nitride layer 51 is deposited, and second metal layer top is exposed in etching on third nitride layer Portion position, post-depositional device architecture are as shown in Figure 9.In this method, nitride has insulating properties, and nitride can be nitrogen SiClx.In order to realize the etching to nitride layer, photoresist is generally coated on nitride layer, then photoetching development exposes the Two metal layer top positions, are finally again etched nitride with nitride chemical etching liquor, need to retain on nitride layer Region due to the barrier of photoresist, will not react and be retained with etching solution.Then etched away again by photoresist etching solution Photoresist thus completes nitride deposition technique.
In transistor fabrication process, the formation of metal layer will generally be coated by photoresist, photoresist photoetching development Expose in original metal layer in requisition for the position of evaporation metal, upper metal is then deposited, then metal can be bonded in original metal On layer, part adhesive is also had certainly on the photoresist not removed, and finally etching solution removes photoresist with photoresist again, so that it may To realize the removal to metal above photoresist and photoresist.Certainly, photoresist etching solution can't directly be reacted with metal.It is logical It crosses photoresist to be isolated, it is desirable to which photoresist will have certain altitude, and then the metal of opening will not be with the gold on photoresist Category is adhered.
It in certain embodiments, can be using vapor deposition realization be carried out twice in one-time process, such as second metal layer It can be seen that second metal layer 9 may include second metal layer first time deposited metal 90 and second of second metal layer in Figure 10 Deposited metal 91.By multiple metal evaporation, avoids once needing excessively high metal, the requirement to technique can be reduced.
Device of the invention can be FET device, such as high electron mobility transistor.The epitaxial wafer packet Include the semiconductive material substrate layer 10 stacked gradually, FET device structure sheaf 11.Wherein semiconductive material substrate The material of layer 10 can be the semiconductor materials such as silicon, GaAs, indium phosphide, gallium nitride, silicon carbide or sapphire.
Further, in order to realize that Y grid elevate the structure of metal, described first is negative photoresist.It is aobvious in photoetching in this way When shadow is open, the blocking realized to metal can be formed, elevates form of metal to be formed at the top of Y grid.
The present invention also provides a kind of Y gate transistor device, the transistor device is by above-mentioned transistor device manufacturing method It is made.Transistor device of the invention production when, have obvious feature, the exactly described Y grid elevate metal height with Second metal layer height is identical at drain metal, source metal.Because it is to be deposited simultaneously that Y grid, which elevate metal and second metal layer, , then it will form identical height.And it is existing unless strict control technique, the Y grid that otherwise different process step is formed elevate gold Category will not be identical with second metal layer height, this can also simply distinguish transistor device made from the method for the present invention and existing Technique made from transistor device.
It should be noted that being not intended to limit although the various embodiments described above have been described herein Scope of patent protection of the invention.Therefore, it based on innovative idea of the invention, change that embodiment described herein is carried out and is repaired Change, or using equivalent structure or equivalent flow shift made by description of the invention and accompanying drawing content, it directly or indirectly will be with Upper technical solution is used in other related technical areas, is included within scope of patent protection of the invention.

Claims (6)

1. a kind of Y gate transistor device manufacturing method, which is characterized in that include the following steps：
In the first light of upper coating of the epitaxial wafer with the first metal layer, Y grid metal, the first nitride layer and the second nitride layer Photoresist；
Exposure development at drain metal, source metal and Y grid top position on the first photoresist to form opening；
Etching removal drain metal, the second nitride layer of source metal and the first nitride layer and the second nitrogen at Y grid position Compound layer；
Coated polymer；
Exposure development at drain metal, source metal and Y grid top position on polymer to form opening；
Coat the second photoresist；
Exposure development at drain metal, source metal and Y grid top position on the second photoresist to form opening；
Metal evaporation deposition is carried out, Y grid is formed in Y grid top position and elevates metal, formed in drain metal, source metal position Second metal layer；
Etching the second photoresist of removal.
2. a kind of Y gate transistor device manufacturing method according to claim 1, which is characterized in that further include step：Deposition Third nitride layer, and second metal layer top position is exposed in etching on third nitride layer.
3. according to claim 1 to a kind of 2 described in any item Y gate transistor device manufacturing methods, it is characterised in that：It is described outer Prolonging piece includes the semiconductive material substrate layer stacked gradually, FET device structure sheaf.
4. according to claim 1 to a kind of 2 described in any item Y gate transistor device manufacturing methods, it is characterised in that：Described Two photoresists are negative photoresist.
5. a kind of Y gate transistor device, which is characterized in that the transistor device by claims 1 to 4 any one one kind Y gate transistor device manufacturing method is made.
6. a kind of Y gate transistor device according to claim 5, which is characterized in that the Y grid elevate metal height with Second metal layer height is identical at drain metal, source metal.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4213840A (en) * 1978-11-13 1980-07-22 Avantek, Inc. Low-resistance, fine-line semiconductor device and the method for its manufacture
JPH04338652A (en) * 1991-05-16 1992-11-25 Mitsubishi Electric Corp Manufacture of semiconductor device
US5358885A (en) * 1992-08-19 1994-10-25 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a field effect transistor with a T-shaped gate electrode and reduced capacitance
CN101140897A (en) * 2006-09-04 2008-03-12 中芯国际集成电路制造(上海)有限公司 Plug manufacturing method of contact plug
CN101211969A (en) * 2006-12-28 2008-07-02 富士通株式会社 High speed high power nitride semiconductor device and manufacturing method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4213840A (en) * 1978-11-13 1980-07-22 Avantek, Inc. Low-resistance, fine-line semiconductor device and the method for its manufacture
JPH04338652A (en) * 1991-05-16 1992-11-25 Mitsubishi Electric Corp Manufacture of semiconductor device
US5358885A (en) * 1992-08-19 1994-10-25 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a field effect transistor with a T-shaped gate electrode and reduced capacitance
CN101140897A (en) * 2006-09-04 2008-03-12 中芯国际集成电路制造(上海)有限公司 Plug manufacturing method of contact plug
CN101211969A (en) * 2006-12-28 2008-07-02 富士通株式会社 High speed high power nitride semiconductor device and manufacturing method thereof

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