CN115148809A - High electron mobility transistor and preparation method thereof - Google Patents

High electron mobility transistor and preparation method thereof Download PDF

Info

Publication number
CN115148809A
CN115148809A CN202210564925.3A CN202210564925A CN115148809A CN 115148809 A CN115148809 A CN 115148809A CN 202210564925 A CN202210564925 A CN 202210564925A CN 115148809 A CN115148809 A CN 115148809A
Authority
CN
China
Prior art keywords
layer
drain
wafer
source
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210564925.3A
Other languages
Chinese (zh)
Inventor
黄平
鲍利华
顾海颖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Fine Chip Semiconductor Co ltd
Original Assignee
Shanghai Fine Chip Semiconductor Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Fine Chip Semiconductor Co ltd filed Critical Shanghai Fine Chip Semiconductor Co ltd
Priority to CN202210564925.3A priority Critical patent/CN115148809A/en
Publication of CN115148809A publication Critical patent/CN115148809A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material

Abstract

The invention discloses a high electron mobility transistor (AlGaN/GaN HEMT) and a preparation method thereof, which is prepared by growing an N + type GaN layer, a GaN buffer layer, an AlGaN barrier layer and a GaN cap layer on a substrate material in sequence; the etching of the isolation groove needs to reach an N + type GaN layer; the source electrode (or the drain electrode) and the grid electrode on the front surface are provided with bump structures; depositing a plastic packaging layer on the surface and grinding to expose the source (or drain) and the grid bump; and the drain electrode (or the source electrode) is connected to the N + type GaN layer in the isolation groove through a lead, the substrate is stripped through back laser, the N + type GaN layer is exposed, and the drain electrode (or the source electrode) of the device is led out from the back surface of the wafer. The drain electrode and the source electrode of the AlGaN/GaN HEMT device are respectively arranged on two sides of the device, so that the application range of the AlGaN/GaN HEMT device is expanded, and the AlGaN/GaN HEMT device is simpler and more flexible to apply.

Description

High electron mobility transistor and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductor device preparation, in particular to a high electron mobility transistor (AlGaN/GaN HEMT) and a preparation method thereof.
Background
AlGaN/GaN HEMTs (high electron mobility transistors) mostly employ heteroepitaxial GaN films obtained by Metal Organic Chemical Vapor Deposition (MOCVD) or Hydride Vapor Phase Epitaxy (HVPE) methods. Heteroepitaxy most often selects materials such as Si, sapphire, and SiC as substrate materials on which GaN growth is performed.
For example, referring to fig. 1, a GaN buffer layer, an AlGaN barrier layer, and a GaN cap layer are sequentially grown on a substrate material using an MOCVD method. After the growth of the heterojunction material is finished, a series of key process steps of ohmic contact of a source electrode and a drain electrode, device isolation, surface passivation, grid groove etching, grid metal evaporation, protection passivation, interconnection opening, interconnection metal evaporation and the like are sequentially carried out to finish the preparation of the HEMT device.
In the typical AlGaN/GaN HEMT device structure prepared in this way, three electrodes (source, gate and drain) are on the surface side of the device. When the HEMT device is connected with other circuits or devices, the structure that the three electrodes are arranged on the surface side of the device can limit the application or inconvenience of the HEMT device in some fields.
Disclosure of Invention
One of the technical problems to be solved by the present invention is to provide a high electron mobility transistor in which the source and the drain of the three electrodes (source, gate and drain) are respectively arranged on two sides of the device, aiming at the above-mentioned disadvantages of the existing AlGaN/GaN HEMT device structure in which the three electrodes (source, gate and drain) are all arranged on one side of the surface of the device.
The second technical problem to be solved by the present invention is to provide a method for manufacturing the above-mentioned high electron mobility transistor.
The AlGaN/GaN high electron mobility transistor as the first aspect of the invention comprises a wafer, and is characterized in that the wafer is prepared by growing an N + type GaN layer, a GaN buffer layer, an AlGaN barrier layer and a GaN cap layer in sequence on a substrate material by adopting an MOCVD method, wherein a drain electrode (or a source electrode) of the transistor is led out from the back surface of the wafer, and a grid electrode and the source electrode (or the drain electrode) are led out from the front surface of the wafer.
In a preferred embodiment of the present invention, the drain (or source) of the transistor is extracted through the back N + -type GaN layer after the substrate is stripped.
In a preferred embodiment of the invention, the substrate is chosen to be sapphire.
A method for producing a high electron mobility transistor as a first aspect of the present invention includes the steps of:
1) And (3) preparing the material. On a substrate, firstly extending an N + type GaN layer, and then sequentially extending a GaN buffer layer, an AlGaN barrier layer and a GaN cap layer;
2) And firstly determining a source electrode and a drain electrode of the device on the surface of the GaN cap layer of the wafer. The source electrode contact hole and the drain electrode contact hole sequentially penetrate through the GaN cap layer and the AlGaN barrier layer until reaching the GaN buffer layer; depositing a metal layer on the surface of the wafer by a sputtering or evaporation process; forming a source electrode graph and a drain electrode graph of the device after photoetching stripping; annealing to form ohmic contact with good performance;
3) Etching to manufacture a device isolation region, wherein the depth of an isolation groove needs to reach the N + type GaN layer;
4) And depositing a first passivation layer. Specifically, a GaN cap layer, a source electrode, a drain electrode, the bottom of an isolation groove and a side wall are passivated to form a first passivation layer;
5) Determining a grid region and etching a grid groove, specifically determining the grid region on a first passivation layer between a source electrode and a drain electrode and etching the grid groove;
6) And sputtering or evaporating to prepare the grid metal. Specifically, gate metal is sputtered or evaporated on the surface of a wafer, the gate metal is patterned at a gate groove to serve as a gate electrode, and the gate metal protrudes out of a first passivation layer between a source electrode and a drain electrode;
7) And depositing a second passivation layer. The method comprises the following steps: depositing a second passivation layer on the surface of the first passivation layer and the surface of the gate metal;
8) The interconnection openings open the drain (or source) contact holes in the isolation trenches. The method comprises the following steps: opening holes on the top of the source metal, the top of the drain metal and the top of the gate metal, and simultaneously opening a drain (or source) contact hole at the bottom of the isolation groove close to one side of the drain (or source); etching away the first passivation layer and the second passivation layer on the source metal layer and the drain metal layer, etching away the second passivation layer on the gate metal layer, and etching away the first passivation layer and the second passivation layer of the drain (or source) contact hole at the bottom of the isolation groove;
9) And preparing interconnection metal, and leading the drain electrode (or the source electrode) of the device to a drain electrode (or a source electrode) contact hole in the isolation groove. The method comprises the following steps: and depositing a metal film on the surface of the wafer, etching a source electrode, a grid electrode and a drain electrode, and simultaneously connecting the drain electrode (or the source electrode) to a drain electrode (or a source electrode) contact hole at the bottom of the isolation groove to be connected with the N < + > -type GaN layer.
10 Forming a source (or drain) bump and a gate bump on the source (or drain) metal layer and the gate metal layer;
11 The front surface of the wafer is subjected to plastic package, and the formed plastic package layer covers the surface of the whole wafer and comprises source (or drain) bumps and grid bumps; then grinding the plastic packaging layer on the front surface of the wafer to expose the source (or drain) bump and the grid bump;
12 The back side of the wafer is stripped to separate the substrate from the back side of the wafer, exposing the N + -type GaN layer and thus exposing the drain (or source) of the device.
In a preferred embodiment of the present invention, the etching depth of the isolation trench needs to reach the N + type GaN layer.
In a preferred embodiment of the present invention, the molding layer is epoxy resin.
In a preferred embodiment of the present invention, in step 12), the back surface of the wafer is stripped, and the substrate is separated from the back surface of the wafer by using a laser stripping method.
The laser lift-off method adopted by the invention is a very mature processing technology. The basic principle of laser lift-off is to utilize the difference between the absorption efficiency of the epitaxial layer material and the absorption efficiency of the sapphire material for the ultraviolet laser. For example, sapphire has a high bandgap energy (9.9 eV), so sapphire is transparent to 248nm krypton fluoride (KrF) excimer laser (5 eV radiant energy), while gallium nitride (a bandgap energy of about 3.3 eV) strongly absorbs the energy of 248nm laser. The laser penetrates through the sapphire to reach the gallium nitride layer, and laser lift-off is carried out on the contact surface of the gallium nitride and the sapphire. This will create a localized blast shock wave causing the gallium nitride to separate from the sapphire there. Based on the same principle, a 193nm argon fluoride (ArF) excimer laser can be used to separate aluminum nitride (AlN) from sapphire. Aluminum nitride, which has a band gap energy of 6.3eV, can absorb ArF laser radiation of 6.4eV, while sapphire, which has a band gap energy of 9.9eV, is transparent to ArF excimer laser light.
Due to the adoption of the technical scheme, the drain electrode (or the source electrode) of the AlGaN/GaN HEMT device is led to the back surface of the wafer, so that the application range of the AlGaN/GaN HEMT device is expanded, and the application is simpler and more flexible.
Drawings
Fig. 1 is a schematic structural view of a conventional AlGaN/GaN HEMT device.
Fig. 2a to 2m are schematic flow charts of a method for manufacturing an electron mobility transistor according to embodiment 1 of the present invention.
Fig. 3a to 3m are schematic flow charts of a method for manufacturing an electron mobility transistor according to embodiment 2 of the present invention.
Detailed Description
The invention is further described below in conjunction with the appended drawings and detailed description.
Example 1
The method for manufacturing the high electron mobility transistor (AlGaN/GaN HEMT) of the embodiment includes the steps of:
1) And (3) preparing the material. Firstly extending an N + type GaN layer 2 on a sapphire substrate 1, and then sequentially extending a GaN buffer layer 3, an AlGaN barrier layer 4 and a GaN cap layer 5;
2) On the surface of the GaN cap layer 5 of the wafer, a source electrode 6 and a drain electrode 7 of the device are firstly determined. The source contact hole and the drain contact hole sequentially penetrate through the GaN cap layer 5 and the AlGaN barrier layer 4 until reaching the GaN buffer layer 3; depositing a metal layer on the surface of the wafer by a sputtering or evaporation process; forming a source electrode graph and a drain electrode graph of the device after photoetching stripping; annealing to form ohmic contact with good performance;
3) Etching to manufacture a device isolation region, wherein the depth of the isolation grooves 8 and 9 needs to reach the N + type GaN layer 2;
4) A first passivation layer 10 is deposited. Specifically, the GaN cap layer 5, the source electrode 6, the drain electrode 7, the bottoms and the side walls of the isolation grooves 8 and 9 are passivated to form a first passivation layer 10;
5) Determining a grid electrode area and etching a grid groove, specifically determining the grid electrode area on a first passivation layer 10 between a source electrode 6 and a drain electrode 7 and etching a grid groove 11;
6) The gate metal 12 is prepared by sputtering or evaporation. Specifically, gate metal is sputtered or evaporated on the surface of a wafer, the gate metal is patterned at a gate groove 11 to be used as a gate electrode 12, and the gate metal protrudes out of a first passivation layer 10 between the source electrode 6 and the drain electrode 7;
7) A second passivation layer 13 is deposited. The method comprises the following steps: depositing a second passivation layer 13 on the surface of the first passivation layer 10 and the surface of the gate metal 12;
8) The interconnection is opened while also opening the drain contact hole 8a in the isolation trench 8. The method comprises the following steps: opening 6a, 7a, 12a on the top of the source metal 6, the top of the drain metal 7 and the top of the gate metal 12, while opening a drain contact hole 8a at the bottom of the isolation trench on the side close to the drain 7; etching away the first passivation layer 10 and the second passivation layer 13 on the source metal layer 6 and the drain metal layer 7, etching away the second passivation layer 13 on the gate metal layer 12, and etching away the first passivation layer 10 and the second passivation layer 13 in the drain contact hole 8a at the bottom of the isolation groove;
9) Interconnection metal is prepared and the drain 7 of the device is brought to the drain contact hole 8a in the isolation trench. The method comprises the following steps: a metal film 14 is deposited on the surface of the wafer, and the source electrode 6b, the gate electrode 12b and the drain electrode 7b are etched, while the drain electrodes 7 and 7b are connected to a drain contact 8b at the bottom of the isolation trench, and are connected to the N + -type GaN layer 2.
10 Source bump 6c and gate bump 12c are made on source metallization 6b and gate metallization 12 b;
11 ) the front surface of the wafer is subjected to plastic packaging, and the formed plastic packaging layer 15 covers the whole surface of the wafer and comprises source bumps 6c and gate bumps 12c; then grinding the plastic packaging layer 15 on the front surface of the wafer to expose the source bump 6c and the gate bump 12c;
12 Laser lift-off is performed on the back surface of the wafer, the sapphire substrate 1 is lifted off from the back surface of the wafer, and the N + -type GaN layer 2 is exposed, and this N + -type GaN layer is connected to the drain 7/7b/8b, thereby forming the high electron mobility transistor (AlGaN/GaN HEMT) of the present embodiment. The drain 7/7b/8b of the high electron mobility transistor (AlGaN/GaN HEMT) of this embodiment is drawn from the back side of the wafer, and the source 6/6b/6c and gate 12/12b/12c are drawn from the front side of the wafer.
Example 2
The method for manufacturing the high electron mobility transistor (AlGaN/GaN HEMT) of the embodiment includes the steps of:
1) And (3) preparing the material. Firstly, an N + type GaN layer 2 is extended on a sapphire substrate 1, and then a GaN buffer layer 3, an AlGaN barrier layer 4 and a GaN cap layer 5 are sequentially extended;
2) On the surface of the GaN cap layer 5 of the wafer, a source electrode 6 and a drain electrode 7 of the device are firstly determined. The source contact hole and the drain contact hole sequentially penetrate through the GaN cap layer 5 and the AlGaN barrier layer 4 until reaching the GaN buffer layer 3; depositing a metal layer on the surface of the wafer by a sputtering or evaporation process; forming a source electrode graph and a drain electrode graph of the device after photoetching stripping; annealing to form ohmic contact with good performance;
3) Etching to manufacture a device isolation region, wherein the depth of the isolation grooves 8 and 9 needs to reach the N + type GaN layer 2;
4) A first passivation layer 10 is deposited. Specifically, the GaN cap layer 5, the source electrode 6, the drain electrode 7, the bottoms and the side walls of the isolation grooves 8 and 9 are passivated to form a first passivation layer 10;
5) Determining a gate region and etching a gate groove, specifically determining the gate region and etching a gate groove 11 on a first passivation layer 10 between a source electrode 6 and a drain electrode 7;
6) The gate metal 12 is prepared by sputtering or evaporation. Specifically, gate metal is sputtered or evaporated on the surface of a wafer, the gate metal is patterned at a gate groove 11 to be used as a gate electrode 12, and the gate metal protrudes out of a first passivation layer 10 between the source electrode 6 and the drain electrode 7;
7) A second passivation layer 13 is deposited. The method comprises the following steps: depositing a second passivation layer 13 on the surface of the first passivation layer 10 and the surface of the gate metal 12;
8) The interconnection is opened while also opening the source contact hole 9a in the isolation trench 8. The method comprises the following steps: opening 6a, 7a, 12a on the top of the source metal 6, the top of the drain metal 7 and the top of the gate metal 12, while opening a source contact hole 9a at the bottom of the isolation trench on the side close to the source 6; etching away the first passivation layer 10 and the second passivation layer 13 on the source metal layer 6 and the drain metal layer 7, etching away the second passivation layer 13 on the gate metal layer 12, and etching away the first passivation layer 10 and the second passivation layer 13 of the source contact hole 9a at the bottom of the isolation trench;
9) Interconnection metal is prepared and the source electrode 6 of the device is led to the source contact hole 9a in the isolation trench. The method comprises the following steps: a metal film 16 is deposited on the wafer surface, and the source electrode 6b, the gate electrode 12b and the drain electrode 7b are etched, while the source electrodes 6 and 6b are connected to a source contact 9b at the bottom of the isolation trench, and are connected to the N + -type GaN layer 2.
10 A drain bump 7c and a gate bump 12c are made on the drain metallization layer 7b and the gate metallization layer 12 b;
11 ) the front side of the wafer is sealed by plastic, and the formed plastic sealing layer 15 covers the whole surface of the wafer, including the drain bumps 7c and the gate bumps 12c; then grinding the plastic packaging layer 15 on the front surface of the wafer to expose the drain bump 7c and the gate bump 12c;
12 Laser lift-off is performed on the back surface of the wafer, the sapphire substrate 1 is lifted off from the back surface of the wafer, and the N + -type GaN layer 2 is exposed, and this N + -type GaN layer is connected to the source electrode 6/6b/9b, thereby forming the high electron mobility transistor (AlGaN/GaN HEMT) of the present embodiment. The source 6/6b/9b of the high electron mobility transistor (AlGaN/GaN HEMT) of this example is drawn from the back side of the wafer, and the drain 7/7b/7c and gate 12/12b/12c are drawn from the front side of the wafer.

Claims (7)

  1. The AlGaN/GaN high electron mobility transistor comprises a wafer and is characterized in that the wafer is prepared by growing an N + type GaN layer, a GaN buffer layer, an AlGaN barrier layer and a GaN cap layer on a substrate material in sequence by adopting an MOCVD method, wherein a drain electrode (or a source electrode) of the wafer is led out from the back side of the wafer, and a grid electrode and the source electrode or the drain electrode are led out from the front side of the wafer.
  2. 2. The hemt of claim 1, wherein said wafer drain or source is pulled through an N + type GaN layer after the substrate is stripped.
  3. 3. The hemt of claim 1 or 2, wherein said substrate is selected to be sapphire.
  4. 4. The preparation method of the high electron mobility transistor is characterized by comprising the following steps:
    1) And (3) preparing the material. On a substrate, firstly extending an N + type GaN layer, and then sequentially extending a GaN buffer layer, an AlGaN barrier layer and a GaN cap layer;
    2) Determining a source electrode and a drain electrode of the device on the surface of a GaN cap layer of the wafer, wherein a source electrode contact hole and a drain electrode contact hole sequentially penetrate through the GaN cap layer and the AlGaN barrier layer until reaching a GaN buffer layer; depositing a metal layer on the surface of the wafer by a sputtering or evaporation process; forming a source electrode graph and a drain electrode graph of the device after photoetching stripping; annealing to form ohmic contact with good performance;
    3) Etching to manufacture a device isolation region, wherein the depth of an isolation groove needs to reach the N + type GaN layer;
    4) Depositing a first passivation layer, namely passivating the GaN cap layer, the source electrode, the drain electrode, the bottom and the side wall of the isolation groove to form the first passivation layer;
    5) Determining a grid region and etching a grid groove, specifically determining the grid region on a first passivation layer between a source electrode and a drain electrode and etching the grid groove;
    6) Preparing gate metal by sputtering or evaporation, specifically sputtering or evaporating the gate metal on the surface of the wafer, and patterning the gate metal at the gate groove to serve as a gate electrode, wherein the gate metal protrudes out of the first passivation layer between the source electrode and the drain electrode;
    7) And depositing a second passivation layer, specifically: depositing a second passivation layer on the surface of the first passivation layer and the surface of the gate metal;
    8) The interconnection trompil also opens the drain contact hole or the source contact hole in the isolation trench simultaneously, specifically is: forming holes on the top of the source metal, the top of the drain metal and the top of the gate metal, and forming a drain contact hole or a source contact hole at the bottom of the isolation groove close to one side of the drain or the source; etching the first passivation layer and the second passivation layer on the source electrode metal layer and the drain electrode metal layer, etching the second passivation layer on the grid electrode metal layer, and etching the drain electrode contact hole at the bottom of the isolation groove or the first passivation layer and the second passivation layer of the source electrode contact hole;
    9) Preparing interconnection metal, and leading the drain electrode or the source electrode of the device to a drain electrode contact hole or a source electrode contact hole in the isolation groove, wherein the preparation method specifically comprises the following steps: depositing a metal film on the surface of the wafer, etching a source electrode, a grid electrode and a drain electrode, connecting the drain electrode or the source electrode to a drain electrode contact hole or a source electrode contact hole at the bottom of the isolation groove, and connecting the drain electrode or the source electrode contact hole with the N + type GaN layer;
    10 Manufacturing a source bump or a drain bump and a gate bump on the source or drain metal layer and the gate metal layer;
    11 The front surface of the wafer is subjected to plastic package, and the formed plastic package layer covers the surface of the whole wafer and comprises source bumps or drain bumps and grid bumps; then grinding the plastic packaging layer on the front surface of the wafer to expose the source electrode lug or the drain electrode lug and the grid electrode lug;
    12 The back side of the wafer is stripped to separate the substrate from the back side of the wafer, exposing the N + type GaN layer, and thus exposing the drain or source of the device.
  5. 5. The method of claim 4, wherein the isolation trench is etched to a depth of the N + type GaN layer.
  6. 6. The method of claim 4, wherein the molding layer is an epoxy resin.
  7. 7. The method of manufacturing a high electron mobility transistor according to claim 4, wherein the step 12) of peeling the back surface of the wafer to separate the substrate from the back surface of the wafer is performed by a laser peeling method.
CN202210564925.3A 2022-05-23 2022-05-23 High electron mobility transistor and preparation method thereof Pending CN115148809A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210564925.3A CN115148809A (en) 2022-05-23 2022-05-23 High electron mobility transistor and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210564925.3A CN115148809A (en) 2022-05-23 2022-05-23 High electron mobility transistor and preparation method thereof

Publications (1)

Publication Number Publication Date
CN115148809A true CN115148809A (en) 2022-10-04

Family

ID=83406801

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210564925.3A Pending CN115148809A (en) 2022-05-23 2022-05-23 High electron mobility transistor and preparation method thereof

Country Status (1)

Country Link
CN (1) CN115148809A (en)

Similar Documents

Publication Publication Date Title
US7045404B2 (en) Nitride-based transistors with a protective layer and a low-damage recess and methods of fabrication thereof
US8946777B2 (en) Nitride-based transistors having laterally grown active region and methods of fabricating same
US8835988B2 (en) Hybrid monolithic integration
US7408182B1 (en) Surface passivation of GaN devices in epitaxial growth chamber
CN110112215B (en) Power device with gate dielectric and etching blocking function structure and preparation method thereof
CN105914232B (en) T-gate N-surface GaN/AlGaN fin type high electron mobility transistor
TW200409304A (en) Hetero-integration of semiconductor materials on silicon
JP2009038344A (en) Formation of nitride-based optoelectronic/electronic device structure on lattice-matched substrate
JP2008512874A (en) HEMT apparatus and manufacturing method
US20230327009A1 (en) Semiconductor layer structure
KR101450521B1 (en) manufacturing method of semiconductor devices with Si trench
CN109300974B (en) Nonpolar InAlN/GaN high electron mobility transistor and preparation method thereof
CN115148809A (en) High electron mobility transistor and preparation method thereof
CN117080183A (en) Diamond-single crystal AlN-GaNAlGaN composite wafer and preparation method and application thereof
CN114883406B (en) Enhanced GaN power device and preparation method thereof
WO2021226839A1 (en) Group iii nitride structure and manufacturing method therefor
WO2019095924A1 (en) Method for preparing enhancement mode gan-based transistor using polarization doping
CN111952175A (en) Transistor groove manufacturing method and transistor
CN112599586B (en) High-reliability gallium nitride-based power device and preparation method thereof
CN216528895U (en) HEMT device with small channel resistance
CN116487274A (en) Manufacturing method of GaN HEMT power device of embedded integrated PWM control circuit
US11380786B2 (en) Insulating structure of high electron mobility transistor and manufacturing method thereof
WO2020228018A1 (en) Preparation method for semiconductor structure
CN112133632A (en) Method for reducing stress of HEMT (high electron mobility transistor) and HEMT
CN115223871A (en) Preparation method of GaN enhanced HEMT device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination