CN1089204C

CN1089204C - Qiepu clock restoring device for quick correcting error

Info

Publication number: CN1089204C
Application number: CN98120500A
Authority: CN
Inventors: 胡爱群; 吴冬生
Original assignee: University of Hong Kong HKU
Current assignee: University of Hong Kong HKU
Priority date: 1998-10-28
Filing date: 1998-10-28
Publication date: 2002-08-14
Anticipated expiration: 2018-10-28
Also published as: CN1219040A

Abstract

The present invention relates to a Qiepu clock restoring device for quickly correcting errors for a direct sequence spread spectrum BPSK/QPSK communication receiver, which comprises parts, such as a fixed correlator, a shift correlator, a VCO control loop, a gate circuit, a data feedback branch, an L counter, etc. A Qiepu clock restoring part is not only provided with a fixed correlator added with a shift correlator, but also provided with a feedback branch and a gate circuit. A VCO which generates a Qiepu clock is simultaneously controlled by output errors of the fixed correlator and the shift correlator to reduce an error rate. The present invention can improve Qiepu clock restoring tracking speed and quality, and can be widely applied to communication receivers; the present invention is suitable for point-to-point spread spectrum communication, point-to-multi-point spread spectrum communication and CDMA mobile communication.

Description

The chip clock recovery device of quick correcting error

The present invention relates to the clock recovery tracking means in a kind of modulation and demodulation technology, correlation reception technology and the PHASE-LOCKED LOOP PLL TECHNIQUE of electric communication technique field spread spectrum technic, particularly relate to the chip clock recovery device of the quick correcting error of a kind of direct sequence spread spectrum phase-shift keying (BPSK/QPSK) communication control processor.

Spread spectrum technic reaches its maturity at present, and has obtained to use widely.Direct sequence spread spectrum communication is comparatively general spread spectrum mode, acquiring pseudo code in its receiver and tracking are of paramount importance rings, the recovery of itself and chip clock is closely-related, particularly for pseudo-code tracing, need be to providing real-time regulating error in order to the VCO (voltage controlled oscillator) that produces chip clock (chip Clock) in the receiver, make the chip clock of receiver reach with the chip clock of transmitter good synchronously, thereby create conditions for correct despreading and the output of judgement data.

Existing chip clock recovery device is to produce an error signal by relevant receiver at every symbol (Symbol) to remove to regulate VCO.Since the speed of chip clock be data symbol rate L doubly, this speed multiple L is generally from tens to hundred times, even bigger; When speed multiple L hour, the output of correlation receiver is affected by noise bigger, makes regulating error affected by noise; And when speed multiple L was big, the adjusting real-time of chip clock was relatively poor, and error is regulated slow, and chip is followed the tracks of more coarse.Therefore no matter speed multiple L size, the quality of chip clock all has direct influence to the error performance of dateout.

The direct sequence spread spectrum communication technology is that data message waiting for transmission is modulated on the pseudo random sequence (PN), promptly uses a PN sequence representative information bit " 0 ", and represents information bit " 1 " with its radix-minus-one complement, the spread spectrum process of Here it is direct sequence.Sequence behind the spread spectrum is carried out the BPSK/QPSK modulation, produce intermediate frequency (IF) signal, launch by radio-frequency apparatus again.At receiving terminal, behind the radio frequency receiving equipment, obtain intermediate frequency (IF) signal, carry out processes such as down-conversion, matched filtering (or differential ference spiral) and integration cleaning, produce data decision output.Wherein, the BPSK/QPSK demodulation is finished in the lump in matched filtering (or differential ference spiral) link.Down-conversion in the receiver needs carrier synchronization, and it is synchronous that other subsequent process be unable to do without chip clock.The part that a key is arranged in receiver----correlator, its PN sequence with the transmission of local PN sequence and transmitting terminal is carried out related operation, provide the required control information of each several part constantly at correlation peak, constantly etc. as the synchronizing information of chip error, matched filter and data decision.

Existing direct sequence spread spectrum communication products, it all is roughly to adopt above-mentioned technology.As the Z2000 spread spectrum communication chip of U.S. Zilog company, it is under the QPSK mode, and follow-up control is 1/4 of data rate to the maximum.With U.S. Qualcomm is that IS-95 CDMA (code division multiple access) standard of representative also adopts direct sequence spread spectrum skill.

Correlation technique is the core technology that spread spectrum receives, and is mostly to adopt sliding correlation method.Local PN sequence leaves in the fixing register, list entries enters in the shift register with local sequence equal length by the sampling rate pointwise, when list entries adopt with local identical PN sign indicating number modulation and immigration register after with local PN sign indicating number on time, correlator will be exported a maximum (being peak value Peak Value); When two sequence misalignment have when departing from, correlation is very little.Therefore can judge PN sequence synchronous situation by the size of correlation, produce error signal and control VCO, regulate the chip clock of flip-flop shift, local sequence be aimed at fully with receiving sequence, and then solve data message by phase-locked loop.This correlator can be realized by serial or parallel.

The clock recovery device of above-mentioned existing direct sequence spread spectrum BPSK/QPSK communication control processor is owing to adopt every symbol to produce the method for first-order error control VCO, and the control frequency is not high so it has, clock recovery does not reach the defective that influences demodulation performance etc. soon.This shows that the clock recovery device of above-mentioned existing direct sequence spread spectrum BPSK/QPSK communication control processor still has many defectives, and the assistant officer waits to be improved.

Because the drawback that above-mentioned existing chip clock recovery device exists, the inventor is based on abundant technical work practical experience and professional knowledge thereof, through constantly studying, design, and after studying sample repeatedly and improving, creates the present invention finally.

Main purpose of the present invention is, overcome the existing defective of above-mentioned existing chip clock recovery device, and provide a kind of chip clock recovery device of quick correcting error of direct sequence spread spectrum BPSK/QPSK communication control processor, make its for pseudo-code tracing to providing real-time regulating error in order to the VCO (voltage controlled oscillator) that produces chip clock (chipClock) in the receiver, make the chip clock of receiver can reach with the chip clock of transmitter good synchronously, thereby can be correct judgement data output creates conditions, and the output that makes correlation receiver is affected by noise less, make the adjusting real-time of chip clock better, chip is followed the tracks of than very fast, thereby can obtain good chip clock, improve error performance.

Another object of the present invention is to, a kind of chip clock recovery device of quick correcting error of direct sequence spread spectrum BPSK/QPSK communication control processor is provided, make it in receiver, add a gate circuit and support circuit thereof, in every symbol time, VCO is regulated several times, thereby can improve the erection rate of clocking error, increase follow-up control.

The objective of the invention is to realize by following technical scheme.The chip clock recovery device of the quick correcting error of the direct sequence spread spectrum BPSK/QPSK communication control processor that proposes according to the present invention, be provided with fixedly correlator, VCO control loop and L counter, it is characterized in that it comprises fixedly parts such as correlator, mobile correlator, VCO control loop, gate circuit, data feedback branch and L counter, wherein: this is correlator and mobile correlator fixedly, it is the X correlator of two symmetrical structures, fixedly correlator is caught the PN sequence in the input signal, realizes the synchronously thick of chip clock; This X correlator is symmetrical structure, has eliminated the influence of carrier phase deviation to chip synchronization; The round-off error of its chip clock is not only from fixing correlator, and more the correction come from mobile correlator, can revise fast, recovers and follow the tracks of; This VCO control loop is the voltage controlled oscillator loop; This gate circuit is subjected to the peak value output control of mobile correlator, and output high-speed pulse stream drives mobile correlator action; This data feedback branch is eliminated the influence that the modulation intelligence in the received signal is exported mobile correlator; This L counter is the L frequency division, produces the required clock of data demodulates; Digital baseband spread-spectrum signal I and Q behind the A/D converter after the down-conversion send into fixedly correlator, and send into feedback branch, and the output Id and the Qd of feedback branch send into mobile correlator; Fixedly after the error addition that produces of correlator and mobile correlator as the input of VCO loop, the VCO loop is output as chip clock, supply with fixedly correlator and mobile correlator, supply with the L counter simultaneously and produce data clock and export, the resetting of L counter controlled by the correlator peak pulse fixedly; The peak pulse of mobile correlator send gate circuit, and mobile correlator is supplied with in the output of gate circuit; Said structure is combined, constitutes the chip clock recovery device of direct sequence spread spectrum communication control processor of the present invention.

Purpose of the present invention can also further realize by following technical measures.

The chip clock recovery device of aforesaid quick correcting error, the signal workflow and the circuit connecting relation of its chip clock recovery device are as follows: signal IB after the down-conversion and QB become digital signal I, i.e. I[0:7 after the A/D conversion]) and Q (be Q[0:7]) send into the fixedly signal input part of correlator; This this locality sequencer, its output PNI and PNQ are connected to local sequence PNI and PNQ output; This VCO loop, its output MAINCLK is connected to input end of clock; Output Xoutf is fixing relevant output, and it is connected to VCO loop 1XCOROUT[00:15] input, as one of error source of VCO, this signal is connected to the input of L counter simultaneously, as the usefulness of this L counter O reset; The highest significant position of this signal also links to each other with the RESTART end of mobile correlator, as the usefulness of the local sequence location in the mobile correlator; Should be fixedly in its auxiliary circuit of correlator, the MAINCLK input clock is through L, L=192 herein, the IQDMP that frequency division produces exports and exports as chip clock; Digital signal I[0:7] and Q[0:7] behind the delay line of the fixing FIFO of correlator, obtain the IDD[0:7 after a symbol postpones] and QDD[0:7] signal, be connected to DELAYI[0:7] and DELAYQ[0:7] data input pin of feedback branch, multiply each other in data bit FEEDBACKIHE and FEEDBACKQ road after here exporting with judgement, remove the modulation intelligence in the received signal, it exports ID[0:7] and QD[0:7] send into mobile correlator; The local mobile sequence generator of this mobile correlator, its output PNIM and PNQM are as the input PNIM and the PNQM of the local mobile sequence of mobile correlator; The output XOUTM of this mobile correlator links the 2XCOROUT[00:15 of VCO loop] input, as another error source of VCO; The highest significant position of this signal is connected to the input of gate circuit simultaneously, as its starting impulse; The output signal of this gate circuit is high-speed pulse string HIGHSPEEDPULSES, and it is connected to the input of mobile sequence generator; The output 2XCOROUT[08:15 of mobile correlator] and the fixing output 2XCOROUT[08:15 of correlator] extract in error and to form the required error signal of VCO in the circuit, the output MAINCLK of VCO produces IQDMP behind the L frequency division, this IQDMP clock is through quick corrected chip clock.

The chip clock recovery device of aforesaid quick correcting error, it is relevant respectively with local fixed sequence program with two input signals for wherein said fixedly correlator, again with addition behind two correlated results square, the result of addition eliminates the influence of down-conversion carrier phase error to correlation as the fixedly output of correlator; Be somebody's turn to do fixedly correlator, it comprises: two signal shift registers, one or two PN sequence receptacle, two related operation devices, two squarers, an adder and threshold compatarors; Input signal I and Q serial respectively send into shift register, each unit output of shift register is carried out related operation with each of local PN sequence, squarer is sent in the output of related operation, the output addition of two squarers, send threshold compataror with value, this and value surpass the just output of setting of thresholding, and this output is the fixedly output Xoutf of correlator.

The chip clock recovery device of aforesaid quick correcting error, wherein said mobile correlator is relevant respectively with local mobile sequence with two input signals, again with addition behind this two correlated results square, the result of addition eliminates the influence of down-conversion carrier phase error to correlation as the output of mobile correlator; This mobile correlator comprises two shift registers, one or two movably PN sequence receptacle, two related operation devices, two squarers, an adder and a threshold compataror; Input signal Id and Qd serial respectively send into shift register, each unit output of shift register is carried out related operation with each of local movably PN sequence, be that correspondence multiplies each other, and all multiplied result are added up, squarer is sent in the output of related operation, and the output addition and the value of two squarers are sent threshold compataror, if this and value surpass the just output of setting of thresholding, this output is the output Xoutm of mobile correlator; Resetting of local PN sequence receptacle in the mobile correlator is subjected to the fixedly control of correlator peak pulse.

The chip clock recovery device of aforesaid quick correcting error, the shift register of wherein said its input signal of fixedly correlator is the shift register of 8 bit parallels, signal sampling point of every input, correlator carries out the related operation of a vice-minister for L with shift register content and local PN sequence, soon each bit of each location contents of shift register and local PN sequence multiplies each other and adds up, and exports a correlation; Fixedly each correlator in the correlator comprises L multiplier and L accumulator, sampled point of every input, and accumulator is got a sub-value and zero clearing; At the BPSK spread spectrum communication mode, fixedly the local PN sequence of correlator has only one, and at the QPSK spread spectrum communication mode, consistent with transmitting terminal, two different local PN sequences can be arranged.The two-way input is relevant with two local PN sequences respectively.

The chip clock recovery device of aforesaid quick correcting error, wherein said its circuit connection structure of fixedly correlator is as follows: two shift registers are made up of U2-U7 and U22-U27FIFO (74F433) respectively; Two correlators are made of the auxiliary circuit that monolithic accumulator STEL-2410 (U9) and U11-U14 form; Two squarers, an adder and a threshold compataror are born by monolithic TMC2249A (U8); Digital signal I[0:7] behind U17 and U18 (74HC157) selector, enter 8 parallel-by-bit shift registers, be U3 → U2 → U4, U6 → U5 → U7, digital signal Q[0:7] behind U28 and U29 (74HC157) selector, entering 8 parallel-by-bit shift registers is U23 → U22 → U24, U26 → U25 → U27; Local sequence PNI and PNQ send into correlator U9, under the effect of master clock MAINCLK, the digital signal of input is relevant in correlator U9 with local sequence, correlated results IOUT[0:7] and QOUT[0:7] send into a square adder U8, it exports 1XCOROUT[00:15] be the fixedly output Xoutf of correlator; Sampled point I[0:7 of every input] and Q[0:7], U17-U18 and the action of U28-U29 selector are once inserted sampled point in the parallel signal shift register, carry out related operation then one time, promptly carry out the sum operation that multiplies each other 192 times; Whenever the addition of once multiplying each other, the signal shift register cyclic shift is once; U11-U14 finishes 192 tally functions, guarantee to make the signal of input and local sequence to carry out 192 additions of multiplying each other after, export once result.

The chip clock recovery device of aforesaid quick correcting error, its physical circuit signal connection structure of wherein said fixedly correlator is as follows: I[0:7] be connected to 2,5,11,14 pin of U17, U18, Q[0:7] be connected to 2,5,11,14 pin of U28, U29; MAINCLK is connected to 2 pin of U11, U12,2 pin of U3, U6, U23, U26,14 pin of U9; PNI and PNQ are connected respectively to 17,55 pin of U9; QDMP is the output of U14A, is connected to 1 pin of U11, U12,1 pin of U17, U18, U28, U29,31,40 pin of U9,1 pin of U8, output at last; 18,19,20,21 of U4, U7 forms 8 bit data bus, 18,19,20,21 of U24, U27 forms 8 bit data bus, is connected respectively to the IDD[0:7 of U9] (1,3,4,5,6,7,8,9 pin) and QDD[0:7] (60,61,62,64,65,66,68 pin); The IOUT[0:7 of U9] (27,26,25,24,23,22,20,18 pin), be connected respectively to the B[4:11 of U8] (38,39,40,41,43,44,45,47 pin) and A[4:11] (55,54,53,52,51,50,49,48 pin); The QOUT[0:7 of U9] (44,45,46,47,48,49,50,51 pin), be connected respectively to the D[4:11 of U8] (111,110,109,108,107,105,104,103 pin) and C[4:11] (94,95,96,97,98,99,100,101 pin; Numeral threshold level THRES[00:15] be connected in the CAS[0:15 of U8] (82,81,80,79,78,77,76,75,74,73,71,70,69,68,67,66 pin); The S[8:15 of U8] (15,14,13,11,10,9,7,6 pin), meet output 1XCOROUT[8:15].

The chip clock recovery device of aforesaid quick correcting error, wherein said its circuit connection structure of mobile correlator is as follows: two shift registers are made up of U2-U7 and U22-U27FIFO (74F433) respectively; Two correlators are made of the auxiliary circuit that monolithic accumulator STEL-2410 (U9) and U11-U14 form; PNI sequence and PNQ sequence are PNIM and PNQM sequence; Two squarers, an adder and a threshold compataror are born by monolithic TMC2249A (U8); Digital signal ID[0:7] behind U17 and U18 (74HC157) selector, entering 8 parallel-by-bit shift registers is U3 → U2 → U4, U6 → U5 → U7, digital signal QD[0:7] behind U28 and U29 (74HC157) selector, entering 8 parallel-by-bit shift registers is U23 → U22 → U24, U26 → U25 → U27; Local sequence PNIM and PNQM send into correlator U9, under the effect of master clock MAINCLK, the digital signal of input is relevant in correlator U9 with local sequence, correlated results IOUT[0:7] and QOUT[0:7] send into a square adder U8, it exports 2XCOROUT[00:15] be the fixedly output Xoutm of correlator; Sampled point ID[0:7 of every input] and QD[0:7], U17-U18 and the action of U28-U29 selector are once inserted sampled point in the parallel signal shift register, carry out related operation then one time, promptly carry out the sum operation that multiplies each other 192 times; Whenever the addition of once multiplying each other, the signal shift register cyclic shift is once; U11-U14 finishes 192 tally functions, after guaranteeing to make input signal and local sequence carry out 192 additions of multiplying each other, exports once result; Aforesaid mobile correlator the and fixedly structure of correlator is basic identical, difference is: fixedly the local PN sequence (length=64) of correlator is fixed with respect to input signal, and promptly the shift clock of PNI and PNQ is PNCLK; The local sequence of mobile correlator is sudden fast moving with respect to input signal, and promptly the shift clock of PNIM and PNQM is PNCLKM.

The chip clock recovery device of aforesaid quick correcting error, its physical circuit syndeton of wherein said mobile correlator is as follows: PN sign indicating number in the mobile correlator produces PN sign indicating number generation circuit in signal annexation and the fixing correlator in circuit, the mobile correlator, fixedly the signal connecting circuit structural relation in the correlator is basic identical, its difference is as follows: ID[0:7] for I[0:7], QD[0:7] for Q[0:7]; PNIM, PNQM are respectively for PNI, PNQ; The S[8:15 of U8] (15,14,13,11,10,9,7,6 pin), meet output 2-XCOROUT[8:15].

The chip clock recovery device of aforesaid quick correcting error, wherein said its error signal of VCO loop moves the error sum that correlator produces from the sum of errors of fixedly correlator generation; This VCO loop, it includes an adder, three grades of shift registers, a subtracter, a D/A converter, a low pass filter and a voltage controlled oscillator VCO; Fixedly send into three shift registers after correlator output signal Xoutf and the mobile correlator output signal Xoutm addition, the output of left and right two registers is subtracted each other, send into low pass filter again, its output is as the voltage control input of VCO, and the output of this VCO is the chip clock of recovery; This clock is also supplied with the shift clock of three grades of shift registers in the VCO loop, and despreading matched filter and the required clock of data demodulates in the receiver is provided for the shift clock of the shift register in the fixedly correlator and the correlator that is shifted.

The chip clock recovery device of aforesaid quick correcting error, its three grades of shift registers of wherein said VCO loop are 8 parallel-by-bit shift registers, about the value of two register cells subtract each other departure as VCO, when after the low pass filter that connects when being analog filter, need between subtracter and filter, to insert digital to analog converter (being D/A), when being digital realization, need not D/A converter.

The chip clock recovery device of aforesaid quick correcting error, wherein said its circuit connection structure of VCO loop is as follows: 1XCOROUT[08:15] (being Xoutf) and reverse signal thereof, constantly lock in the latch of U11, U12 at T1 (left side) and T3 (right side), and addition in the adder that U9, U10 constitute, 1DA[0:7] come down to the error of the output of fixing correlator in left and right two moment; Similarly, 2XCOROUT[08:15] (being Xoutm) and reverse signal thereof, constantly lock in the latch of U16, U17, and addition in the adder that U14, U15 constitute 2DA[0:7 at T1 (left side) and T3 (right side)] output that comes down to mobile correlator about two constantly errors; These two errors are converted to analog signal through U1 and U2 (DAC08), and addition in U3 and U4A, send VCO U5 (MC1648) behind the low pass filter of R13 and C8 composition; Foregoing circuit has been realized Xoutf and Xoutm addition, moves into the left, center, right register, and left and right two register values are subtracted each other, D/A conversion again, and low-pass filtering waits VCO loop overall process until VCO control; The pulse in T1, T2, three moment of T3, it is made of U6 (74161), U7 (7404) and U8 (7432) logical circuit, its input signal is the peak signal 2XCOROUT15 and the chip clock IQDMP of mobile correlator, promptly when peak value appears in mobile correlator, write down first, second, third pulse position that surpasses threshold value.

The chip clock recovery device of aforesaid quick correcting error, its physical circuit syndeton of wherein said VCO loop is as follows: T1 receives 11 pin of U11, U16, and T3 receives 11 pin of U12, U17; 1XCOROUT[08:15] be connected to the D[0:7 of U11] input of (2,3,4,5,6,7,8,9 pin), U7, U13; 2XCOROUT[08:15] be connected to the D[0:7 of U16] input of (2,3,4,5,6,7,8,9 pin), U18, U13; The output S[1:4 of U9 and U10] (4,1,13,10 pin) composition 8 bit data bus, the output S[1:4 of U14 and U15] form 8 bit data bus, be connected respectively to the B[1:8 of U1, U2] (9,10,11,12,13,14,15,16 pin); The OUT of U5 (3 pin) is connected to output MAINCLK.

The chip clock recovery device of aforesaid quick correcting error, it produces a string high-speed pulse wherein said gate circuit under starting impulse control, this gate circuit comprises: a gate, counter, an oscillator (OSC), a pulse stretcher and a trigger; This gate circuit is exported M pulse train under starting impulse control, M is the maximum count value of the counter of setting; Starting impulse opens the sluices, and the clock that allows oscillator OSC is by gate, and unison counter is counted the clock periodicity by gate, and closed shutter when the full M of counter meter just opens the sluices again up to the arrival of next starting impulse.

The chip clock recovery device of aforesaid quick correcting error, wherein said the gate circuit wherein frequency of oscillation of oscillator OSC are higher than the chip clock frequency, can make the frequency of oscillation of oscillator equal the twice of chip clock frequency; Its starting impulse is the peak pulse of mobile correlator, this pulse is given one " with door " for high level behind broadening, this " with door " also sent in the output of OSC, M is sent in the output of " with door " counter, the full back of meter carry signal triggering one trigger is a low level by the high level redirect, and this level is sent into " with door " and sealed its output, be that M high-speed pulse of gate circuit output just stops, up to the arrival of the peak pulse of mobile correlator next time; The output state of above-mentioned trigger is constantly put height at the peak value of mobile correlator; The maximum count value M of counter is provided with the erection rate that has determined the chip clock error, and M is big more, and correction is slow more, otherwise the more little correction of M is fast more; The M minimum can not be less than the sampling number of every chip, and this installs every chip samples 3 points, and the M maximum can not be greater than the fixing correlation length L of correlator and mobile correlator; When M equals L, the speed of device before the erection rate of this chip clock error equals, demodulation performance does not improve.

The chip clock recovery device of aforesaid quick correcting error, the circuit connection structure of wherein said gate circuit close and are: circuit design condition: direct sequence spread spectrum, spreading gain=64; The QPSK modulation; Every chip (Chip) sampling 3 points, the every chip samples of correlation length L=is counted and be multiply by spreading gain=192; The PN sequence is the Gold sequence, length=64; Chip clock erection rate parameter M=12=3*4, promptly per 4 chip corrections once.

The chip clock recovery device of aforesaid quick correcting error, it is made up of wherein said feedback branch two one symbol delay devices and two multipliers, behind the signal multiplication of a feedback data and a symbol delay as the output of this feedback branch, DI links to each other with DQ under the BPSK mode, and DI and DQ branch is opened under the QPSK mode.

The chip clock recovery device of aforesaid quick correcting error, its physical circuit syndeton of wherein said gate circuit is as follows: this gate circuit, and it comprises: oscillation source U4 (OSCB), gate U3A (74HC10) and M (M=16) counter U5 (74161); The peak value output of mobile correlator is sign bit 2XCOR-OUT15 control signal as gate after U6A (74123) pulse stretching, and the carry of M counter U5 (74161) is sent into the control signal that U10A (d type flip flop) produces closed gate; The output high-speed pulse HIGHSPEEDPULSES of gate gives mobile correlator.The clock of the U3A of gate circuit (74HC10) is from a fixing oscillator U4 (OSCB), and the frequency of OSCB is higher than the sampling rate of input signal, gets 2 times here.

The chip clock recovery device of aforesaid quick correcting error, its physical circuit syndeton of wherein said feedback branch is as follows: two multipliers are made of the XOR gate of U1A-U1D, U2A-U2D, U3A-U3D, U4A-U4D; Local sequence is a binary sequence, the digital signal of input and the multiplying of binary sequence can replace with XOR, digital signal I[0:7 after the down-conversion in the receiver] and Q[0:7] signal DELAYI[0:7 after a data symbol postpones] be IDD[0:7]) and DELAYQ[0:7] be QDD[0:7]) respectively with feedback data bit FEEDBACKI and FEEDBACKQ step-by-step XOR, be output as ID[0:7] and QD[0:7], as the signal input of mobile correlator, FEEDBACKI here (I Data Out) and FEEDBACKQ (Q Data Out) are the output of data demodulator.

The chip clock recovery device of aforesaid quick correcting error, it is that the maximum count amount is the asynchronous resetting counter of L for wherein said counter, and L is the sampling number that spreading gain multiply by every chip, and it equals the fixedly correlation length of correlator and mobile correlator; This counter has reset (zero clearing) input, input end of clock and L frequency division output terminal; This counter carries out the L frequency division to input clock, makes counter O reset under the reset pulse effect immediately, its frequency division output and reset terminal signal Synchronization.

The chip clock recovery device of aforesaid quick correcting error, its physical circuit syndeton of wherein said L counter is as follows: this L counter, constitute by U1 (7404), U2 (74161), U7 (74161), U8 (7420) and U9 (7432) logical circuit, the input clock of circuit is chip clock IQDMP, maximum count value L is 192, be output as CLKOUT, supply with matched filter and data demodulator; Counter is in the fixedly peak value zero clearing constantly of correlator, and the anti-phase back of 1XCOROUT15 is as the clear signal of counter U2, U7, and L counter meter is the back self-zeroing completely.

The chip clock recovery device of aforesaid quick correcting error, its physical circuit syndeton of wherein said gate circuit is as follows: 2XCOROUT15 is connected to 1 pin of U6A, 4 pin of U10A; The OUT of U4 (3 pin) is connected to 1 pin of U3A, and the Q of U6A (13 pin) is connected to 2 pin of U3A, and the Q of U10A (5 pin) is connected to 13 pin of U3A; 12 pin of U3A are connected to 2 pin of U5, send output HIGHSPEEDPULSES simultaneously.

In the chip clock recovery device of above-mentioned quick correcting error, fixedly correlator and mobile correlator, both have identical structure.Fixedly the local PN sequence in the correlator is fixed for the modulation sequence in the received signal, and the local sequence of this mobile correlator is movably, and it moves the output high-speed pulse that is subjected to gate circuit and controls.Mobile correlator always is in a kind of fast moving--〉and waits for and catch--〉and among the dynamic circulation of fast moving, each circulation all can produce minor peaks output, thereby produces the VCO error one time.Fixedly once peak value output of the every data symbol of correlator, its output joins in the output of mobile correlator, guarantees that the performance of this device is not inferior to existing method in the past.Fixedly correlator mainly provides symbol slightly synchronous, and mobile correlator mainly produces the error signal of VCO.Behind the VCO loop-locking, even received signal to noise ratio is relatively poor or signal(-) carrier frequency moment departs from greatlyyer, this device will make VCO enter locking once more fast.

The present invention compared with prior art has tangible advantage and good effect.By above technical scheme as can be known, the present invention relates to a kind of chip clock recovery device of direct sequence spread spectrum BPSK/QPSK communication control processor, existing traditional chip clock reset mode, be with relevant after the acknowledge(ment) signal down-conversion with local sequence, local sequence maintains static, in a symbol time, produce minor peaks output, or get the chip clock error one time, implement once to regulate.The present invention increases a mobile correlator and auxiliary equipment in receiver, make to obtain a plurality of peak value outputs in a symbol time, obtains repeatedly chip clock error, implements repeatedly to regulate, and number of times can reach the number of chips in the symbol at most.

Technical essential of the present invention is the chip clock recovered part in the direct sequence spread spectrum communication control processor, and except keeping original fixedly correlator, other adds a mobile correlator, and is aided with feedback branch and gate circuit.The voltage controlled oscillator (VCO) that is used to produce chip clock is subjected to the control of the output error of the output error of fixing correlator and mobile correlator simultaneously, guarantees that the recovery tracking velocity of chip clock is not inferior to traditional method.

Innovative point of the present invention mainly is on the recovery problem of chip clock, method in the past is that near the peak value output time (or) (promptly a data symbol in) at correlator produces the phase place that the first-order error signal removes to regulate clock, since regulate number of times than spreading rate slowly many, just require the centre frequency of VCO can not differ too much, otherwise the data error performance will variation with the frequency of making a start.

The present invention designs apparatus of the present invention from increase regulating the purpose of number of times, its can every M (M＜＜L) sampled point calculates first-order error, regulates one time phase place.In a data bit, regulate or follow the tracks of number of times like this and be L/M (this device L=192, M=12, L/M=16), thus can very fast error identifying, implement adjusting.

The tracking performance that experiment showed, apparatus of the present invention improves (L/M) doubly than previous method, even when received signal to noise ratio is very poor, its performance is also much better than preceding method.Behind this device of utilization, the carrier synchronization of receiver down converter is required also to descend a lot.

The present invention can be widely used in improving the resume speed and the quality of chip clock with in the direct sequence spread spectrum communication BPSK/QPSK receiver, reduces the error rate of communication.Be applicable to point-to-point spread spectrum communication, point-to-multipoint spread spectrum communication and cdma mobile communication.

In sum, the chip clock recovery device of the quick correcting error of direct sequence spread spectrum phase-shift keying of the present invention (BPSK/QPSK) communication control processor, it is in the technology of the present invention field, no matter structurally or on the function all be significantly improved, and very much progress is arranged technically, and produced handy and practical effect, and have the enhancement effect really, thereby being suitable for practicality more, really is a new and innovative, progressive, practical new design.

Concrete structure of the present invention, mode are provided in detail by following examples and accompanying drawing thereof.

Fig. 1 is the structural representation of direct sequence spread spectrum (DSSS) receiver, expresses the structural relation of the present invention in direct sequence spread spectrum (DSSS) receiver.

Fig. 2 is the structural representation of the chip clock recovery device of quick correcting error of the present invention.

Fig. 3 is the structural representation of fixedly correlator of the present invention.

Fig. 4 is the structural representation of mobile correlator of the present invention.

Fig. 5 is the structural representation in the VCO loop of chip clock recovery of the present invention.

Fig. 6 is the structural representation of gate circuit of the present invention.

Fig. 7 is the structural representation of BPSK/QPSK mode feedback branch of the present invention.

Fig. 8 is the structural representation of related operation structure of the present invention.

Fig. 9 is the structural representation of the present invention when using.

Figure 10 a is the circuit diagram that the PN sign indicating number in the fixedly correlator of the present invention produces circuit.

Figure 10 b is the electrical schematic diagram of fixedly correlator of the present invention.

Figure 11 a is the circuit diagram that the PN sign indicating number in the mobile correlator of the present invention produces circuit.

Figure 11 b is the electrical schematic diagram of mobile correlator of the present invention.

Figure 12 a is the circuit diagram that the error in the VCO loop of the present invention is extracted circuit.

Figure 12 b is the circuit diagram of the voltage-controlled circuit in the VCO loop of the present invention.

Figure 12 c is the circuit diagram that the latch pulse in the VCO loop of the present invention produces circuit.

Figure 13 is the electrical schematic diagram of gate circuit of the present invention.

Figure 14 is the electrical schematic diagram of feedback branch of the present invention.

Figure 15 is the electrical schematic diagram that data clock of the present invention produces circuit.

Below in conjunction with accompanying drawing and preferred embodiment thereof, its concrete structure of chip clock recovery device, feature and the effect of the quick correcting error of the direct sequence spread spectrum BPSK/QPSK communication control processor that foundation the present invention is proposed, describe in detail as after.

See also shown in Figure 1, be the structural representation of direct sequence spread spectrum (DSSS) receiver, express the structural relation of chip clock recovery device in direct sequence spread spectrum (DSSS) receiver of the quick correcting error of direct sequence spread spectrum BPSK/QPSK communication control processor of the present invention simultaneously.

The chip clock recovery device of the quick correcting error of direct sequence spread spectrum BPSK/QPSK communication control processor of the present invention, this device is different from former chip clock recovery device, has had more gate circuit, mobile correlator and feedback branch in this device.In this device, chip clock is defined as in the receiver clock to base-band spread-spectrum signal IB after the down-conversion and QB sampling.If every chip (Chip) of spread spectrum PN sequence is sampled 3 points, then chip clock (ChipClock) is three times of PN spreading rate (CPRT).

See also shown in Figure 2, the chip clock recovery device of the quick correcting error of direct sequence spread spectrum BPSK/QPSK communication control processor of the present invention, it comprises: fixing parts such as correlator, mobile correlator, VCO control loop, gate circuit, data feedback branch and L counter; Wherein, fixedly correlator and mobile correlator are the X correlators of two symmetrical structures, and the VCO control loop is voltage controlled oscillator (being called for short VCO, down together) loop; Fixedly correlator is used for catching the PN sequence of input signal, realizes the synchronously thick of chip clock; This X correlator has been eliminated the influence of carrier phase deviation to chip synchronization owing to adopted symmetrical structure; This gate circuit is subjected to the peak value output control of mobile correlator, and output high-speed pulse stream drives mobile correlator action; This data feedback branch is used for eliminating the influence of the modulation intelligence of received signal to mobile correlator output; This L counter is used for the L frequency division, produces the required clock of data demodulates.Inventive point of the present invention existing chip clock recovery device part different from the past is the part that is positioned at figure lower middle portion frame of broken lines, and the empty frame (chain-dotted line) among the figure has been indicated the part that this device has more than device in the past.The chip clock recovery device of quick correcting error of the present invention, it comprises feedback branch, and mobile correlator and gate circuit, the round-off error of its chip clock are not only from fixing correlator, and more straightener can reach the purpose of quick correction, recovery and tracking from mobile correlator.

Digital baseband spread-spectrum signal after the down-conversion (behind the A/D converter among Fig. 1) I and Q send into fixedly correlator, and send into feedback branch, and the output Id and the Qd of this feedback branch send into mobile correlator; Fixedly after the error addition that produces of correlator and mobile correlator as the input of VCO loop, the VCO loop is output as chip clock, supply with fixedly correlator and mobile correlator, supply with the L counter simultaneously and produce data clock and export, the resetting of L counter controlled by the correlator peak pulse fixedly; The peak pulse of mobile correlator send gate circuit, and mobile correlator is supplied with in the output of gate circuit.

The chip clock recovery device of the combined formation of said structure direct sequence spread spectrum communication control processor of the present invention, this device is different from former chip clock recovery device, after adopting apparatus of the present invention, in every data symbol, mobile correlator will have the output of several times peak value, the output of 16 minor peaks is arranged in this Design of device, and a minor peaks of conventional device output before no longer being, thereby the tracking resume speed that makes clock has improved 16 times, and revise the error of chip clock fast, improve the performance of despreading and demodulation significantly.

Below with reference to Fig. 3-Fig. 8 the structure of various piece of the present invention is done further deep description.The electrical schematic diagram that it is pointed out that the each several part that the present invention is given is one embodiment of the present invention, and Fig. 1～technical scheme shown in Figure 8 is only overall technology design of the present invention place.

See also shown in Figure 3, it is the structure of fixedly correlator of the present invention, it is used for catching the PN sequence of input signal, its structure is different from existing common correlator, it carries out related operation to the two-way input signals in quadrature simultaneously, and, eliminate of the influence of the deviation of down-conversion carrier phase to correlation with addition behind the correlated results square.Identical with local PN sequence in the fixing correlator and when the PN sequence in the input signal fully on time, fixing peak value of correlator output.Should be fixedly correlator be that two input signals are relevant respectively with local fixed sequence program, with addition behind two correlated results square, the fixedly output of correlator of result's conduct of addition is so eliminated the influence of down-conversion carrier phase error to correlation again.

Be somebody's turn to do fixedly correlator, it comprises: two signal shift registers, one or two PN sequence receptacle, two related operation devices, two squarers, an adder and threshold compatarors.

Input signal I and Q serial respectively send into shift register, it (is corresponding multiplying each other that each unit output of shift register is carried out related operation with each of local PN sequence, and all multiplied result are added up), squarer is sent in the output of related operation, the output addition of two squarers, send threshold compataror with value, just export if this surpasses the thresholding of setting with value, this output is the fixedly output Xoutf of correlator.

Seeing also shown in Figure 4ly, is the structure of mobile correlator of the present invention, and it also is the PN sequence that is used for catching input signal, and it is different from existing common correlator, also is different from above-mentioned fixedly correlator.The local sequence of this mobile correlator is movably, promptly is displacement capable of circulation, like this with regard to available it catch the list entries of different time skew.Identical with local PN sequence in the mobile correlator and when the PN sequence in the input signal fully on time, peak value of this mobile correlator output then.Because the error of VCO depends on the appearance of correlation peak, therefore this mobile correlator is being brought into play important effect in the present invention.This mobile correlator is that two input signals are relevant respectively with local mobile sequence, and with addition behind two correlated results square, the result of addition has eliminated the influence of down-conversion carrier phase error to correlation as the output of mobile correlator again.

This mobile correlator, it comprises: two shift registers, one or two movably PN sequence receptacle, two related operation devices, two squarers, an adder and a threshold compataror.

Input signal Id and Qd serial respectively send into shift register, each unit output of shift register is carried out related operation with each of local movably PN sequence, be that correspondence multiplies each other, and all multiplied result are added up, squarer is sent in the output of related operation, and the output addition and the value of two squarers are sent threshold compataror, if this and value surpass the just output of setting of thresholding, this output is the output Xoutm of mobile correlator.

Resetting of local PN sequence receptacle in the mobile correlator is subjected to the fixedly control of correlator peak pulse.

See also shown in Figure 5, it is the structure in the VCO loop of chip clock recovery of the present invention, it is accepted from the fixing signal in the peak value moment of correlator and mobile correlator, and the formation error signal relevant with the chip clock instantaneous phase error, remove to control VCO and change instantaneous frequency, the change of its frequency is always towards the direction that chip clock instantaneous phase error absolute value is diminished.Its error signal of VCO loop moves the error sum that correlator produces from the sum of errors of fixedly correlator generation.

This VCO loop, it comprises: adder, one three grades shift registers (left, center, right), a subtracter, a D/A converter, a low pass filter and a voltage controlled oscillator VCO.

Fixedly send into three shift registers (left, center, right) after correlator output signal Xoutf and the mobile correlator output signal Xoutm addition, with about the output of two registers subtract each other, send into low pass filter again, its output is as the voltage control input of VCO, and the output of this VCO is the chip clock of recovery.This clock is also supplied with the shift clock of three grades of shift registers in the VCO loop, and despreading matched filter and the required clock of data demodulates in the receiver is provided for the shift clock of the shift register in the fixedly correlator and the correlator that is shifted.

Above-mentioned VCO loop as shown in Figure 5,, its three grades of shift registers are 8 parallel-by-bit shift registers, about the value of two register cells subtract each other departure as VCO, when after the low pass filter that connects when being analog filter, need between subtracter and filter, to insert digital to analog converter (being D/A), when being digital realization, need not D/A converter.

Seeing also shown in Figure 6ly, is the structure of gate circuit of the present invention, and it is used to produce one group one group high-speed pulse string, and the local PN sequence that promotes in the mobile correlator moves forward some steps, waits the arrival of same sequence in the input signal then.

This gate circuit, it produces a string high-speed pulse under starting impulse control, this gate circuit, it comprises: a gate, counter, an oscillator (OSC, down together), a pulse stretcher and a trigger.

This gate circuit is exported M pulse train under starting impulse control, M is the maximum count value of the counter of setting.Starting impulse opens the sluices, and the clock that allows oscillator OSC is by this gate, and unison counter is counted the clock periodicity by gate, and closed shutter when the full M of counter meter just opens the sluices again up to the arrival of next starting impulse.

This gate circuit, the frequency of oscillation of oscillator OSC wherein is higher than the chip clock frequency, can make the frequency of oscillation of oscillator equal the twice of chip clock frequency; Its starting impulse is the peak pulse of mobile correlator, this pulse is given one " with door " for high level behind broadening, this " with door " also sent in the output of OSC, M is sent in the output of " with door " counter, the full back of meter carry signal triggering one trigger is a low level by the high level redirect, this level is sent into " with door " and is sealed its output, and promptly M high-speed pulse of this gate circuit output just stops, up to the arrival of the peak pulse of mobile correlator next time.The output state of above-mentioned trigger is constantly put height at the peak value of mobile correlator.

The maximum count value M of counter is provided with the erection rate that has determined the chip clock error.M is big more, and correction is slow more, otherwise the more little correction of M is fast more.The M minimum can not be less than the sampling number (this installs every chip samples 3 points) of every chip, and the M maximum can not be greater than the fixing correlation length L of correlator and mobile correlator.When M equaled L, the erection rate of the chip clock error of this device equaled the speed of previous method, and demodulation performance does not improve.

Please in conjunction with consulting among Fig. 2 shown in the L counter portion, the said counting device, it is that the maximum count amount is the asynchronous resetting counter of L, and L is the sampling number that spreading gain multiply by every chip, and it equals the fixedly correlation length of correlator and mobile correlator.This counter has reset (zero clearing) input, input end of clock and L frequency division output terminal, and it constitutes as L counter portion among Fig. 2.This counter carries out the L frequency division to input clock, makes counter O reset under the reset pulse effect immediately, its frequency division output and reset terminal signal Synchronization.

Seeing also shown in Figure 7ly, is the structure of BPSK/QPSK mode feedback branch of the present invention, its be used for eliminating mobile correlator since the modulated data information in the input signal to the influence of mobile correlation.This feedback branch is formed (as shown in Figure 7) by two one symbol delay devices and two multipliers.Behind the signal multiplication of a feedback data and a symbol delay as the output of this feedback branch.Under the BPSK mode, DI link to each other with DQ (shown in the dotted line among Fig. 7); Under the QPSK mode, DI and DQ branch are opened.

Seeing also shown in Figure 8ly, is a kind of parallel related operation structure of the present invention, and its corresponding unit with list entries and local sequence multiplies each other, and with all multiplied result additions.This related operation structure also available strings line correlation device realizes.This serial correlator is only done at every turn and is once taken advantage of and one-accumulate, for finishing the related operation function, must be provided with supporting sequential and circuit, and it mainly is that circulating register and support circuit thereof are set.Chip clock recovery device of the present invention has just adopted this structure at the correlator of Figure 10 a, 10b and Figure 11 a, 11b, and it uses FIFO as circulating register.

As shown in Figure 8, it is the computing structure of correlator, the shift register of its input signal of said fixing correlator is the shift register of 8 bit parallels, signal sampling point of every input, correlator carries out the related operation of a vice-minister for L with shift register content and local PN sequence, soon each bit of each location contents of shift register and local PN sequence multiplies each other and adds up, and exports a correlation.The computing structure of correlator as shown in Figure 8.Fixedly each correlator in the correlator comprises L multiplier and L accumulator, sampled point of every input, and accumulator is got a sub-value and zero clearing.

At the BPSK spread spectrum communication mode, fixedly the local PN sequence of correlator has only one, and at the QPSK spread spectrum communication mode, consistent with transmitting terminal, two different local PN sequences can be arranged.The two-way input is relevant with two local PN sequences respectively.

See also Figure 10 to shown in Figure 15, a kind of specific embodiment for the chip clock recovery device of quick correcting error of the present invention specifies circuit connecting relation below.

The design condition of foregoing circuit is:

Direct sequence spread spectrum, spreading gain=64;

The QPSK modulation;

Every chip (Chip) sampling 3 points,

The every chip samples of correlation length L=is counted and be multiply by spreading gain=192;

The PN sequence is the Gold sequence, length=64;

Chip clock erection rate parameter M=12=3*4, promptly per 4 chip corrections once (previous method be per 64 chip corrections once, the erection rate of this device is 16 times of previous method).

General structure of the present invention sees also shown in Figure 2, and Fig. 3 to Fig. 8 is the each several part structure chart.A kind of specific implementation of the present invention such as Figure 10 are to shown in Figure 15, wherein: fixedly correlator shown in Figure 3, and its physical circuit is shown in Figure 10 a, 10b; Mobile correlator shown in Figure 4, its physical circuit is shown in Figure 11 a, 11b; VCO loop shown in Figure 5, its physical circuit is shown in Figure 12 a, 12b, 12c; Gate circuit shown in Figure 6, its physical circuit is as shown in figure 13; Feedback branch shown in Figure 7, its physical circuit is as shown in figure 14; L counter shown in Figure 2, its physical circuit is as shown in figure 15;

See also shown in Figure 2ly, the signal workflow and the circuit connecting relation of this device are as follows: signal IB after the down-conversion and QB become the signal input part that digital signal I (be I[0:7]) and Q (be Q[0:7]) send into the fixedly correlator of Figure 10 b after the A/D conversion; Figure 10 a is local sequencer, and its output PNI and PNQ are connected to local sequence PNI and the PNQ output of Figure 10 b; Figure 12 b is the VCO loop, and its output MAINCLK is connected to the input end of clock of Figure 10 b; The output Xoutf of Figure 10 b is fixing relevant output, and it is connected to the VCO loop 1XCOROUT[00:15 of Figure 12 a] input, as one of error source of VCO; This signal is connected to the input of the L counter of Figure 15 simultaneously, as the usefulness of this L counter O reset; The highest significant position of this signal also links to each other with the RESTART end of the mobile correlator of Figure 11 a, as the usefulness of the local sequence location in the mobile correlator; In the auxiliary circuit of the fixedly correlator shown in Figure 10 b, the MAINCLK input clock is exported as chip clock through the IQDMP output that L (L=192) frequency division produces.

Digital signal I[0:7] and Q[0:7] behind the delay line of the FIFO of the fixedly correlator of Figure 10 b, obtain the IDD[0:7 after a symbol postpones] and QDD[0:7] signal, be connected to the DELAYI[0:7 of Figure 14] and DELAYQ[0:7] data input pin of feedback branch, multiply each other in data bit FEEDBACKIHE and FEEDBACKQ road after here exporting with judgement, remove the modulation intelligence in the received signal, it exports ID[0:7] and QD[0:7] send into Figure 11 b and move correlator; Figure 11 a is the local mobile sequence generator of mobile correlator, and its output PNIM and PNQM move the input PNIM and the PNQM of the local mobile sequence of correlator as Figure 11 b; The output XOUTM that Figure 11 b moves correlator links the 2XCOROUT[00:15 of Figure 12 aVCO loop] input, as another error source of VCO; The highest significant position of this signal is connected to the input of Figure 13 gate circuit simultaneously, as its starting impulse; The output signal of this gate circuit is high-speed pulse string HIGHSPEEDPULSES, and it is connected to the input of the mobile sequence generator of Figure 11 a.

The output 2XCOROUT[08:15 of mobile correlator] and the fixing output 2XCOROUT[08:15 of correlator] extract in the error of Figure 12 a and to form the required error signal of VCO in the circuit, the output MAINCLK of VCO produces IQDMP behind the L frequency division, this IQDMP clock is through quick corrected chip clock.

See also Figure 10 a fixedly the PN sign indicating number in the correlator produce circuit and Figure 10 b fixedly shown in the correlator circuit, above-mentioned fixedly correlator, its physical circuit as shown in the figure.In Figure 10 b, the parallel signal shift register of forming by correlator U9 (STEL-2410), square adder and threshold compataror U8 (TMC2249A), U2-U7 and U22-U27 (7F433) FIFO, and constituted by the auxiliary circuit that U11 ~ U14 forms.

Please shown in Figure 3 in conjunction with consulting, two shift registers are made up of U2-U7 among Figure 10 b and U22-U27FIFO (74F433) respectively; Two auxiliary circuit formations that correlator is made up of monolithic accumulator STEL-2410 (U9) and U11-U14 in Figure 10 b; PNI sequence and PNQ sequence are produced by Figure 10 a; Two squarers, an adder and a threshold compataror are born by monolithic TMC2249A (U8) in Figure 10 b.

In Figure 10 b, digital signal I[0:7] behind U17 and U18 (74HC157) selector, enter 8 parallel-by-bit shift register (U3 → U2 → U4, U6 → U5 → U7), digital signal Q[0:7] behind U28 and U29 (74HC157) selector, enter 8 parallel-by-bit shift registers (U23 → U22 → U24, U26 → U25 → U27); Local sequence PNI and PNQ send into correlator U9, under master clock MAINCLK effect, the digital signal of input is relevant in correlator U9 with local sequence, correlated results IOUT[0:7] and QOUT[0:7] send into a square adder U8, it exports 1XCOROUT[00:15] be the fixedly output Xoutf of correlator.

A sampled point I of every input (0:7) and Q (0:7), U17-U18 and the action of U28-U29 selector are once inserted sampled point in the parallel signal shift register, carry out related operation then one time, promptly carry out the sum operation that multiplies each other 192 times.Whenever the addition of once multiplying each other, the signal shift register cyclic shift once.

U11-U14 finishes 192 tally functions, after guaranteeing to make input signal and local sequence carry out 192 additions of multiplying each other, exports once result.

Because the correlator U9 (STEL-2410) that selects be the cascade connection type correlator, only finish at every turn and once take advantage of and once add, so part sequential and aforesaid principle part are different.

See also shown in Figure 10 a, the 10b, above-mentioned fixedly correlator, the signal annexation in its physical circuit is as follows:

I[0:7] be connected to 2,5,11,14 pin of U17, U18, Q[0:7] be connected to 2,5,11,14 pin of U28, U29; MAINCLK is connected to 2 pin of U11, U12,2 pin of U3, U6, U23, U26,14 pin of U9;

PNI, PNQ are connected respectively to 17,55 pin of U9; QDMP is the output of U14A, is connected to 1 pin of U11, U12,1 pin of U17, U18, U28, U29,31,40 pin of U9,1 pin of U8, output at last;

18,19,20,21 of U4, U7 forms 8 bit data bus, 18,19,20,21 of U24, U27 forms 8 bit data bus, is connected respectively to the IDD[0:7 of U9] (1,3,4,5,6,7,8,9 pin) and QDD[0:7] (60,61,62,64,65,66,68 pin);

The IOUT[0:7 of U9] (27,26,25,24,23,22,20,18 pin), be connected respectively to the B[4:11 of U8] (38,39,40,41,43,44,45,47 pin) and A[4:11] (55,54,53,52,51,50,49,48 pin);

The QOUT[0:7 of U9] (44,45,46,47,48,49,50,51 pin), be connected respectively to the D[4:11 of U8] (111,110,109,108,107,105,104,103 pin) and C[4:11] (94,95,96,97,98,99,100,101 pin;

Numeral threshold level THRES[00:15] be connected in the CAS[0:15 of U8] (82,81,80,79,78,77,76,75,74,73,71,70,69,68,67,66 pin);

The S[8:15 of U8] (15,14,13,11,10,9,7,6 pin), meet output 1XCOROUT[8:15].

Above-mentioned fixedly correlator, its physical circuit syndeton sees also shown in Figure 10 a, be connected to 2 pin of U4 (74161) from the MAINCK information of VCD loop among Figure 12 b, and form PNCLK output by 15 pin, simultaneously, this signal is connected to 2 pin of 1 pin, U2 and U7 (74161) of U5A (7401) and 11 pin of U1 (74HC574) again respectively, and the pin 2 of this U5A is connected with the pin of U4; 15 pin of U2 are connected with 7 pin of U7, and the signal that 14,13,12,11 pin of U2 and U7 form is connected 8,7,6,5,4,3,2,1 pin that adds to U3 respectively; 9,10,11,12,13,14,15,16,17 pin of U3 are connected with 2,3,4,5,6,7,8,9 pin of U1 respectively, and 19,18 pin of U1 are for pointing out PNI and PNQ respectively.

See also shown in Figure 10 b, output signal I (0:7) is connected to 2,5,11,14 pin of U17 and U18, and Q (0:7) is connected to 2,5,11,14 pin of U28 and U29.Be connected to 2 pin, U3 and the U6 of U11 and U12,2 pin of U23, U26 and 14 pin of U9 from the MAUNCK signal of VCDQ loop among Figure 12 b; PNI, PNQ are connected respectively to 17 pin and 55 pin of U9,3 pin of U14A (T432) form the IQDMP output signal, be connected to 1 pin, U17 and the U18 of U11 and U12,1 pin of U28, U29,31 pin of U9 and 1 pin of 40 pin and U8 respectively, and export the VCD loop among Figure 12 C to.

In above-mentioned fixedly correlator, wherein, 4,7,9,12 pin of U17, U18, U28, U29 are for being connected to 3,4,5,6 pin of U3, U6, U23, U26 respectively; 22,21,20,19,18 pin of U3, U6, U23, U26 are connected to 2,3,4,5,6 pin of U2, U5, U22, U25 respectively, and 22,21,20,19,18 pin of U2, U5, U22, U25 are connected to 2,3,4,5,6 pin of U4, U7, U24, U27 respectively; 14,13,12,11 pin of U11, U12 are connected to 1,2,4,5 pin of U13A (7420) and 1 pin of U19A, 9,10,13 pin of U13B respectively, 2 pin of U19A (7404) are connected with 12 pin of U13B, 8 pin of U13B are connected with 2 pin of U14A (7838), and 5 pin of U13A are connected with 1 pin of U14 (7432).18,19,20,21 pin of U4, U7 are connected and consist of 8 bit data bus, 18,19,20,21 pin of U24, U27 are connected and consist of 8 bit data bus, and be connected to IDD (0:7) 1,3,4,5,6,7,8,9 pin of U9 and QDD (0:7) 60,61,62,63,64,65,66,68 pin respectively.18,20,21,22,23,24,25,26 pin of U9 are connected respectively to B (4:11) 38,39,40,41,43,44,45,47 pin and A (4:11) 55,54,53,52,51,50,49,48 pin of U8, and the QOUT of U9 (0:7) 44,45,46,47,48,49,50,51 pin are connected respectively to D (4:11) 111,110,109,108,107,105,104,103 pin and C (4:11) 94,95,96,97,98,99,100,101 pin of U8.Numeral threshold level THRES (00:15) is connected in CAS (0:15) 82,81,80,79,78,77,76,75,74,73,71,70,69,68,67,66 pin of U8; The S of U8 (8:15) 15,14,13,11,10,9,7,6 pin connect output 1XCOROUT (8:15).

See also Figure 11 a and move PN sign indicating number in the correlator and produce shown in the circuit that circuit and Figure 11 b move correlator, above-mentioned mobile correlator, its concrete circuit is as shown in FIG..In Figure 11 b, the parallel signal shift register of forming by correlator U9 (STEL-2410), square adder and threshold compataror U8 (TMC2249A), by U2-U7 and U22-U27 (7F433) FIFO, and constituted by the auxiliary circuit that U11-U14 forms.

Signal annexation and the signal annexation among Figure 10 a, Figure 10 b among physical circuit Figure 11 a, Figure 11 b of mobile correlator are basic identical, and its difference is as follows: ID[0:7] for I[0:7], QD[0:7] for Q[0:7]; PNIM, PNQM are respectively for PNI, PNQ; The S[8:15 of U8] (15,14,13,11,10,9,7,6 pin), meet output 2-XCOROUT[8:15].

Its physical circuit of mobile correlator is shown in Figure 11 a, Figure 11 b.Please shown in Figure 4 in conjunction with consulting, two shift registers are made up of U2-U7 among Figure 11 b and U22-U27 FIFO (74F433) respectively; Two auxiliary circuit formations that correlator is made up of monolithic accumulator STEL-2410 (U9) and U11-U14 in Figure 11 b; PNI sequence and PNQ sequence promptly are PNIM and the PNQM sequence that is produced by Figure 11 a; Two squarers, an adder and a threshold compataror are born by monolithic TMC2249A (U8) in Figure 11 b.

In Figure 11 b, digital signal ID[0:7] behind U17 and U18 (74HC157) selector, enter 8 parallel-by-bit shift register (U3 → U2 → U4, U6 → U5 → U7), digital signal QD[0:7] behind U28 and U29 (74HC157) selector, enter 8 parallel-by-bit shift registers (U23 → U22 → U24, U26 → U25 → U27); Local sequence PNIM and PNQM send into correlator U9, under the effect of master clock MAINCLK, the digital signal of input is relevant in correlator U9 with local sequence, correlated results IOUT[0:7] and QOUT[0:7] send into a square adder U8, it exports 2XCOROUT[00:15] be the fixedly output Xoutm of correlator.

Sampled point ID[0:7 of every input] and QD[0:7], U17-U18 and the action of U28-U29 selector are once inserted sampled point in the parallel signal shift register, carry out related operation then one time, promptly carry out the sum operation that multiplies each other 192 times.Whenever the addition of once multiplying each other, the signal shift register cyclic shift once.

Mobile correlator the and fixedly structure of correlator is basic identical, difference is: fixedly the local PN sequence (length=64) of correlator is fixed with respect to input term signal, promptly the shift clock of PNI and PNQ is PNCLK (being produced by Fig. 1 Oa); The local sequence of mobile correlator is sudden fast moving with respect to input term signal, and promptly the shift clock of PNIM and PNQM is PNCLKM (being produced by Figure 11 a).

See also shown in Figure 11 a, the PN sign indicating number of this mobile correlator produces circuit, its circuit structure and Figure 10 a fixedly the PN sign indicating number in the correlator to produce the circuit signal annexation of circuit basic identical, its difference is, 15 pin of U4 (74161) are connected to 1 pin of U6A (7486), the HIGHSPEEDPULES signal is connected to 2 pin of U6A (7486), and its output 3 pin form the PNCLKM signal, and are connected to 2 pin of U2, U7 and 11 pin of U1 simultaneously.

See also shown in Figure 11 b, this signal annexation that moves the fixedly correlator among correlator and Figure 10 b is also basic identical, and its difference is, has replaced I (0:7) with ID (0:7), and QD (0:7) has replaced Q (0:7); PNIM, PNQM have replaced PNI, PNQ respectively, and the S among the U8 (8:15) 15,14,13,11,10,9,7,6 pin connect output 2XCOROUT (8:15).

See also voltage-controlled circuit and the latch pulse in Figure 12 cVCO loop that the error in Figure 12 aVCO loop extracts in circuit, Figure 12 bVCO loop and produce shown in the circuit, above-mentioned VCO loop, its circuit structure is as shown in FIG..Fixedly the output 2XCOROUT (08:15) of the output 1XCOROUT (08:15) of correlator and mobile correlator is as the input of circuit among Figure 12 a.The pulse in two moment is used for latch input signal about pulse T1, T3 correlation peak, by the circuit generation of Figure 12 c.U11 among Figure 12 a, U12, U16, U17 are 8 parallel-by-bit latchs, and U9-U10 and U14-U15 are respectively 8 full adders.1DA[0:7] be 1XCOROUT[08:15] result that constantly subtracts each other at T1 and T3 two, 2DA[0:7] be 2XCOROUT[08:15] result that constantly subtracts each other at T1 and T3 two, they are delivered to D/A converter U1 and U2 (DAC08) among Figure 12 b respectively, be converted into and be fit to VCO (U5) analog signal (MC1648).U3A, U3B, U4A constitute adder, with the addition of two-way analog signal, the result of addition gives the low pass filter of being made up of R13 and C8, the output of filter is added on the FREQUENCY CONTROL variable capacitance diode D1 of oscillator of VCO, to change the output frequency of VCO, the output MAINCLK of VCO is 192 times of chip clock, and the IQDMP signal is 192 frequency divisions of MAINCLK, is chip clock.

The physical circuit of VCO loop, see also shown in Figure 12 a, Figure 12 b, Figure 12 c, and it is please shown in Figure 5 in conjunction with consulting, in Figure 12 a, 1XCOROUT[08:15] (being Xoutf) and reverse signal thereof, constantly lock in the latch of U11, U12, and addition in the adder that U9, U10 constitute 1DA[0:7 at T1 (left side) and T3 (right side)] output that comes down to fixing correlator about the error in two moment; Equally, 2XCOROUT[08:15] (being Xoutm) and reverse signal thereof, constantly lock in the latch of U16, U17, and addition in the adder that U14, U15 constitute 2DA[0:7 at T1 (left side) and T3 (right side)] output that comes down to mobile correlator about two constantly errors.These two errors are converted to analog signal through U1 and U2 (DAC08) in Figure 12 b, and addition in U3 and U4A, send VCO U5 (MC1648) behind the low pass filter of R13 and C8 composition.Foregoing circuit has been realized Xoutf and the Xoutm addition among Fig. 5, moves into the left, center, right register, and with about two register values subtract each other, D/A conversion again, low-pass filtering is until overall process such as loop such as VCO such as VCO control grade.

The pulse in pulse T1, T2, three moment of T3 is produced by the circuit shown in Figure 12 c, and it is to be made of U6 (74161), U7 (7404) and U8 (7432) logical circuit.Its input signal is the peak signal 2XCOROUT15 and the chip clock IQDMP of mobile correlator, promptly when peak value appears in mobile correlator, writes down first, second, third pulse position that surpasses threshold value.

See also shown in Figure 12 a, the error in this VCO loop is extracted circuit, and the circuit signal annexation of its VCO loop is as follows: T1 receives 11 pin of U11, U16, and T3 receives 11 pin of U12, U17; 1XCOROUT[08:15] be connected to the D[0:7 of U11] input of (2,3,4,5,6,7,8,9 pin), U7, U13; 2XCOROUT[08:15] be connected to the D[0:7 of U16] input of (2,3,4,5,6,7,8,9 pin), U18, U13; The output S[1:4 of U9 and U10] (4,1,13,10 pin) composition 8 bit data bus, the output S[1:4 of U14 and U15] form 8 bit data bus, be connected respectively to the B[1:8 of U1, U2] (9,10,11,12,13,14,15,16 pin); The OUT of U5 (3 pin) is connected to output MAINCLK.

The physical circuit signal annexation of this VCO loop is as follows: T1 is connected to U11,11 pin of U16, T3 is connected to U12,11 pin of U17,1XCOROUT (08:15) is connected to the D (0:7) 2 of U11,3,4,5,6,7,8,9 pin, U13A-U13D, the input 1 of U7C-U7F, 3,5,9 pin and 5,9,11,13 pin, 2XCORUT (08:15) is connected to the D (0:7) 2 of U16,3,4,5,6,7,8,9 pin, U18C-U18F and U13E, U13F, U18A, the input 5 of U18B, 9,11,13 pin and 11,13,1,3 pin, the input 2 of U13A-U13D, 3,4,8 pin, the output 6 of U7C-U7F, 8,10,12 pin are connected respectively to the D (0:7) 2 of U12,3,4,5,6,7,8,9 pin, the output 6 of U18C-U18F, 8,10,12 pin, U13E, U13F, U18A, the output 10 of U18B, 12,2,4 pin; Receive D (0:7) 2,3,4,5,6,7,8,9 pin of U17 respectively; Output 19,18,17,16,15,14,13,12 pin of U11 connect R1 (0:7) and V1 (0:7) respectively; Be connected with 5,3,14,12 pin of U9, U10 respectively, 19,18,17,16,15,14,13,12 pin of U16 are connected to V1 (0:7) and link to each other with 5,3,14,12 pin of U14, U15 respectively, 19,18,17,16,15,14,13,12 pin of U12 are connected to R2 (0:7), are connected with 6,2,15,11 pin of U9, U10 respectively.19,18,17,16,15,14,13,12 pin of U17 are connected to V2 (0:7) and are connected with 1,2,15,11 pin of U14, U15 respectively.9 pin of U9, U14 link to each other with 7 pin of U10, U15 respectively, output S (1:4) 4,1,13,10 pin of U9 and U10 are formed 8 bit data bus, the output S (1:4) of U14, U15 forms 8 bit data bus, and the OUT3 pin that is connected to U1, U2 among Figure 12 b, B (1:8) 9,10,11,12,13,14,15,16 pin, U5 respectively is connected to output MAINCLK.2 pin of U3A and 8 pin of U1 link to each other, 1 pin of U3A links to each other with 5 pin of U1, and link to each other through input 2 pin of resistance R 8 and U14A, 6 of U3 B, 7 pin and U2 (DACO8) 8,5 pin link to each other, 7 pin of U3B link to each other through 2 pin of resistance R 7 and U4A, R9 is the feedback resistance of U4A (AD847), U4A exports 1 pin through R13 and D, C6 links to each other, U5,12 pin and L1,10 pin and the L1 of the continuous U5 of D1, C5 links to each other, C8, C6 is connected to DR13 and plays the bypass effect, R12, R11 series connection be connected to respectively U5 5 pin and+the 5V power supply plays and adjusts the voltage effect, 5 pin that C7 is connected to U5 play the power supply filter action.

See also shown in Figure 12 C, 1,2 of U6 (74161) links to each other with 3 pin of U7B, 1 pin of USA with the 2XCOROUT15 of Figure 11 b output and 14 pin of IQDMP, U6 respectively, 13 pin of U6 link to each other with 5 pin of 11 pin of U7A, U8B, the 4 pin outputs of U7B link to each other with

input

4,9 pin of U8B, U8C respectively, output 2 pin of U7A link to each other with

input

2,10 pin of U8A, U8C respectively, and

output

3,6, the 8 pin output signals of USA, U8B, U8C are respectively T1, T3 and are connected to 11 pin of U11, U16 of Figure 12 a and 11 pin of U12, U17 respectively.

See also Fig. 6, shown in Figure 13, the U4 among the figure is OSC, and U3A is a gate, and U6A is a pulse stretcher, and U10A is a trigger, and U5 is M counter (M=16 here).See also shown in Figure 13 gate circuit, above-mentioned gate circuit, it is by oscillation source U4 (OSCB), gate U3A (74HC10) and M (M=16) counter U5 (74161).The peak value output of mobile correlator is sign bit 2XCOR-OUT15 control signal as gate after U6A (74123) pulse stretching, and the carry of M counter U5 (74161) is sent into the control signal that U10A (d type flip flop) produces closed gate.The output high-speed pulse HIGHSPEEDPULSES of gate gives mobile correlator.The clock of the U3A of gate circuit (74HC10) is from a fixing oscillator U4 (OSCB), and the frequency of OSCB is higher than the sampling rate of input signal, and present embodiment is got 2 times here.

See also shown in Figure 13, this gate circuit, its concrete circuit signal syndeton relation is as follows: 2XCOROUT15 is connected to 1 pin of U6A, 4 pin of U10A; The OUT of U4 (3 pin) is connected to 1 pin of U3A, and the Q of U6A (13 pin) is connected to 2 pin of U3A, and the Q of U10A (5 pin) is connected to 13 pin of U3A; 12 pin of U3A are connected to 2 pin of U5, send output HIGHSPEEDPULSES simultaneously.Promptly, the 2XCOROUT15 signal that is moved correlator output by Figure 11 b is connected to 1 pin of U6A and 4 pin of U10A, the OUT3 pin of U4 is connected with 1 pin of U3A, 13 pin of U6A are connected respectively to 2 pin of U3A and 1,9,7,10 pin of U5,5 pin of U10A are connected with 13 pin of U3A, 15 pin of U5 are connected with 3 pin of U10A, and 12 pin of U3A are connected with 2 pin of U5, and export HIGHSPEEDPUZSES simultaneously.

See also shown in Figure 14 feedback branch, above-mentioned feedback branch is made up of the XOR gate of U1-U4.The physical circuit of feedback branch as shown in figure 14, and is please shown in Figure 7 in conjunction with consulting, and two one symbol delay devices among the figure are realized in the fixedly correlator circuit of Figure 10 a, so no longer comprise this two delayers in Figure 14.Two multipliers among Fig. 7 are made of the XOR gate of U1A-U1D, U2A-U2D, U3A-U3D, U4A-U4D in Figure 14.

Because local sequence is a binary sequence, so the digital signal of input and the multiplying of binary sequence can replace with XOR.Digital signal I[0:7 after the down-conversion in the receiver] and Q[0:7] signal DELAYI[0:7 after a data symbol postpones] (be the IDD[0:7 of Figure 10 b]) and DELAYQ[0:7] (be the QDD[0:7 of Figure 10 b]) respectively with feedback data bit FEEDBACKI and FEEDBACKQ step-by-step XOR, be output as ID[0:7] and QD[0:7], as the signal input of mobile correlator, FEEDBACKI here (I Data Out) and FEEDBACKQ (Q Data Out) are the output of data demodulator.

The particular circuit configurations of this feedback branch, can be formed by the XOR gate of U1-U4, wherein DELAYI (0:7) (being the IDD (0:7) among Figure 10 b) is connected with 1,4,9,12 pin of U1, U2, DELAYQ (0:7) (being the QDD (0:7) among Figure 10 b) is connected with 1,4,9,12 pin of U3, U4, respectively with feedback signal FEEDBACKI (being connected) step-by-step XOR with U1, U22,5,10,13 pin, 3,6,8,11 pin of U1, U2 are output as ID (0:7), and 3,5,8,11 pin of U3, U4 are output as QD (0:7).

See also Figure 15 data clock of the present invention and produce shown in the circuit, above-mentioned L counter, it is to be made of U1 (7404), U2 (74161), U7 (74161), U8 (7420) and U9 (7432) logical circuit.The connection of L counter sees also shown in Figure 2, and the input clock of this circuit is chip clock IQDMP, and maximum count value L is 192, is output as CLKOUT, supplies with matched filter and data demodulator.Counter is in the peak value zero clearing constantly of as shown in Figure 3 fixedly correlator, and the anti-phase back of 1XCOROUT15 is as the clear signal of counter U2, U7, and L counter meter is the back self-zeroing completely.

This data clock produces circuit, its physical circuit syndeton is as follows: 1XCOROUT15 connects 1 pin of U1A, output 2 pin of U1A link to each other with 15 pin of U2, U3 and 10 pin of U3 respectively, 14,13,12,11 pin of U2 are connected with 1,2,4,5 pin of U4A, 12 pin of U3 are connected with 3 pin of U1B, 4 pin of U1B are connected with 12 pin of U4B,

output

6,8 pin of U4A, U4B are connected with 1,2 pin of U5A respectively, output 3 pin of U5A are connected with 9 pin of U2, U3,11 pin of U3 are connected with 13 pin of U4B, and export CLKOUT simultaneously.

In the present invention, every chip bit sample 3 points, promptly the sample rate of correlator input signal is three times of spreading rate.Existing in the past technical scheme is every chip bit sample 2 points, and its advantage of technical scheme of the present invention be follow the tracks of meticulousr, PN sequence synchronously better, it is more accurate to insert and clean the pulse location, can further improve the data demodulates performance.After acquisition success and clock loop locking, in the chip width of peak, will have three spot correlation values and surpass threshold value, 2 amplitude differences are as the error signal of controlling VCO about getting.When left side value was worth greater than the right, clock phase was transferred left, otherwise transferred to the right.

It is the correlator of the fixedly register of L that local sequence adopts length, is referred to as fixedly correlator, and a minor peaks appears in every L sampled point; It is the correlator of the shift register of L that local sequence adopts length, is referred to as mobile correlator, and a minor peaks appears in every M sampled point, 1＜M＜L.The effect of these two correlators is different, and the former is used for the cleaning pulse with the demodulation integrator of inserting of catching of PN sequence and local sequence, and the latter is used to produce error, implements the quick adjustment to VCO.

Below the operation principle of the present invention and the course of work are described as follows.Send into the chip clock recovery device of quick correcting error of the present invention through the pseudo random sequence signal (homophase after being the receiver down-conversion and orthogonal signalling) of data message modulation, fixedly the local sequence of correlator is motionless, as long as pseudo random sequence and the position alignment identical in the input signal with local sequence, will produce a minor peaks, produce a reset pulse constantly in maximum, this pulse is the L counter O reset, and the local shift register sequential machine content of mobile correlator is set to local sequence.Fixedly correlator joins in the error signal of mobile correlator peak in the error of the peak error as the initial adjustment chip clock.The L counter is as frequency divider, produces data clock.In a single day the output of mobile correlator surpass threshold value, just starts M high-speed pulse of gate circuit output, and local sequence is advanced the M step, is in wait state then, and list entries constantly moves into, and the output meeting of mobile correlator surpasses threshold value again, circulation like this.Local sequential register in the mobile correlator is a circulating register, and it is exported at last and return the first order again under the clock effect.This interdynamic mechanism of local sequence and list entries resembles two individual races, local sequence is run the M step earlier and marquis's state such as is in, after list entries arrival, touch local sequence and run the M step again, continue always, both are whenever approaching once, just produce the error of a chip clock, control VCO adjusts phase place, and M is more little, and it is just many more to adjust chance.This principle and technical conceive be the core place of technical solution of the present invention just.

Owing to contain the data message of modulation in the list entries, it makes mobile correlator can not produce peak value output sometimes when catching up with local sequence, and causes omission.Tracing it to its cause is because the one-period of data message and local sequence is asynchronous, and correlation is changed.Data feedback branch of the present invention has then solved this problem effectively.Because dateout is in time than the late data symbol of list entries, so list entries is postponed to multiply each other with dateout behind the data symbol again, just removed the data message in the list entries, sent into mobile correlator again, made related operation with the mobile sequence of this locality.

See also Fig. 1, Fig. 2, shown in Figure 9, it is in the BPSK/QPSK receiver of means of communication that the present invention can be used for the direct sequence spread spectrum skill, and its typical connection as shown in Figure 9.The chip clock recovery device of quick correcting error of the present invention is as the important step in the direct sequence spread spectrum communication BPSK/QPSK receiver, the many link construction systems of in receiver other, the chip clock recovery and the data clock that can replace in original receiver recover this two parts, its homophase road signal I and positive cross-channel signal Q after with down-conversion and A/D conversion in original receiver sends into this device, as the fixing input signal of correlator; Data are exported Data out (to be annotated: in the BPSK mode, have only one tunnel output; And in the QPSK mode, two-way output is arranged) also as the input of this device, I and Q after a data bit postpones respectively with Data out signal multiplication, Id and Qd send into mobile correlator as a result for they; The ChipClock output of this device is given receiver as chip clock, replaces original chip clock; Output replaces original data clock to the CLKOut of this device as data clock.

Below application of the present invention and effect thereof are described as follows.It is in the BPSK/QPSK receiver of means of communication that the present invention can be used for the direct sequence spread spectrum skill, improves the tracking velocity to the PN sequence, makes the clock synchronization that recovers better, thereby the error rate of data message is reduced.It can be widely used in point-to-point spread spectrum communication machine, point-to-multipoint spread spectrum communication system and CDMA mobile communication system etc.

Because spread spectrum communication is the means of communication that develops rapidly in recent years, to replace other communication system more and more, therefore the chip clock recovery device of quick correcting error of the present invention can be made special chip, its range of application is more extensive, and meaning is more great.

The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, every foundation technical spirit of the present invention all still belongs in the scope of technical solution of the present invention any simple modification, equivalent variations and modification that above embodiment did.

Claims

1, a kind of chip clock recovery device of quick correcting error of direct sequence spread spectrum BPSK/QPSK communication control processor, be provided with fixedly correlator, VCO control loop and L counter, it is characterized in that it comprises fixedly parts such as correlator, mobile correlator, VCO control loop, gate circuit, data feedback branch and L counter, wherein:

Fixedly correlator and mobile correlator are the X correlators of two symmetrical structures, and fixedly correlator is caught the PN sequence in the input signal, realize the synchronously thick of chip clock; This X correlator is symmetrical structure, has eliminated the influence of carrier phase deviation to chip synchronization; The round-off error of its chip clock is not only from fixing correlator, and more revises from mobile correlator, can revise fast, recovers and follow the tracks of;

This VCO control loop is the voltage controlled oscillator loop;

This gate circuit is subjected to the peak value output control of mobile correlator, and output high-speed pulse stream drives mobile correlator action;

This data feedback branch is eliminated the influence that the modulation intelligence in the received signal is exported mobile correlator;

This L counter is the L frequency division, produces the required clock of data demodulates;

Digital baseband spread-spectrum signal I and Q behind the A/D converter after the down-conversion send into fixedly correlator, and send into feedback branch, and the output Id and the Qd of feedback branch send into mobile correlator;

Fixedly after the error addition that produces of correlator and mobile correlator as the input of VCO loop, the VCO loop is output as chip clock, supply with fixedly correlator and mobile correlator, supply with the L counter simultaneously and produce data clock and export, the resetting of L counter controlled by the correlator peak pulse fixedly;

The peak pulse of mobile correlator send gate circuit, and mobile correlator is supplied with in the output of gate circuit;

Said structure is combined, constitutes the chip clock recovery device of direct sequence spread spectrum communication control processor of the present invention.

2, the chip clock recovery device of quick correcting error according to claim 1, the signal workflow and the circuit connecting relation that it is characterized in that the chip clock recovery device are as follows: signal IB after the down-conversion and QB become digital signal I, i.e. I[0:7 after the A/D conversion]) and Q (be Q[0:7]) send into the fixedly signal input part of correlator; This this locality sequencer, its output PNI and PNQ are connected to local sequence PNI and PNQ output; This VCO loop, its output MAINCLK is connected to input end of clock; Output Xoutf is fixing relevant output, and it is connected to VCO loop 1XCOROUT[00:15] input, as one of error source of VCO, this signal is linked the input of L counter simultaneously, as the usefulness of this L counter O reset; The highest significant position of this signal also links to each other with the RESTART end of mobile correlator, as the usefulness of the local sequence location in the mobile correlator; Should be fixedly in its auxiliary circuit of correlator, the MAINCLK input clock is through L, L=192 herein, the IQDMP that frequency division produces exports and exports as chip clock;

Digital signal I[0:7] and Q[0:7] behind the delay line of the fixing FIFO of correlator, obtain the IDD[0:7 after a symbol postpones] and QDD[0:7] signal, be connected to DELAYI[0:7] and DELAYQ[0:7] data input pin of feedback branch, multiply each other in data bit FEEDBACKIHE and FEEDBACKQ road after here exporting with judgement, remove the modulation intelligence in the received signal, it exports ID[0:7] and QD[0:7] send into mobile correlator; The local mobile sequence generator of this mobile correlator, its output PNIM and PNQM are as the input PNIM and the PNQM of the local mobile sequence of mobile correlator; The output XOUTM of this mobile correlator links the 2XCOROUT[00:15 of VCO loop] input, as another error source of VCO; The highest significant position of this signal is connected to the input of gate circuit simultaneously, as its starting impulse; The output signal of this gate circuit is high-speed pulse string HIGHSPEEDPULSES, and it is connected to the input of mobile sequence generator;

The output 2XCOROUT[08:15 of mobile correlator] and the fixing output 2XCOROUT[08:15 of correlator] extract in error and to form the required error signal of VCO in the circuit, the output MAINCLK of VCO produces IQDMP behind the L frequency division, this IQDMP clock is through quick corrected chip clock.

3, the chip clock recovery device of quick correcting error according to claim 1, it is relevant respectively with local fixed sequence program with two input signals to it is characterized in that described fixedly correlator, again with addition behind two correlated results square, the result of addition eliminates the influence of down-conversion carrier phase error to correlation as the fixedly output of correlator;

Be somebody's turn to do fixedly correlator, it comprises two signal shift registers, one or two PN sequence receptacle, two related operation devices, two squarers, an adder and a threshold compataror;

Input signal I and Q serial respectively send into shift register, each unit output of shift register is carried out related operation with each of local PN sequence, squarer is sent in the output of related operation, the output addition of two squarers, send threshold compataror with value, this and value surpass the just output of setting of thresholding, and this output is the fixedly output Xoutf of correlator.

4, the chip clock recovery device of quick correcting error according to claim 1, it is characterized in that described mobile correlator is relevant respectively with local mobile sequence with two input signals, again with addition behind two correlated results square, the result of addition eliminates the influence of down-conversion carrier phase error to correlation as the output of mobile correlator;

This mobile correlator comprises two shift registers, one or two movably PN sequence receptacle, two related operation devices, two squarers, an adder and a threshold compataror;

Input signal Id and Qd serial respectively send into shift register, each unit output of shift register is carried out related operation with each of local movably PN sequence, be that correspondence multiplies each other, and all multiplied result are added up, squarer is sent in the output of related operation, and the output addition and the value of two squarers are sent threshold compataror, if this and value surpass the just output of setting of thresholding, this output is the output Xoutm of mobile correlator;

5, according to the chip clock recovery device of claim 3 or 4 described quick correcting errors, the shift register that it is characterized in that described its input signal of fixedly correlator is the shift register of 8 bit parallels, signal sampling point of every input, correlator carries out the related operation of a vice-minister for L with shift register content and local PN sequence, soon each bit of each location contents of shift register and local PN sequence multiplies each other and adds up, and exports a correlation; Fixedly each correlator in the correlator comprises L multiplier and L accumulator, sampled point of every input, and accumulator is got a sub-value and zero clearing;

6,, it is characterized in that described its circuit connection structure of fixedly correlator is as follows according to the chip clock recovery device of claim 1 or 3 described quick correcting errors:

Two shift registers are made up of U2-U7 and U22-U27FIFO (74F433) respectively; Two correlators are made of the auxiliary circuit that monolithic accumulator STEL-2410 (U9) and U11-U14 form; Two squarers, an adder and a threshold compataror are born by monolithic TMC2249A (U8);

Digital signal I[0:7] behind U17 and U18 (74HC157) selector, enter 8 parallel-by-bit shift registers, be U3 → U2 → U4, U6 → U5 → U7, digital signal Q[0:7] behind U28 and U29 (74HC157) selector, enter 8 parallel-by-bit shift registers, i.e. U23 → U22 → U24, U26 → U25 → U27; Local sequence PNI and PNQ send into correlator U9, under master clock MAINCLK effect, the digital signal of input is relevant in correlator U9 with local sequence, correlated results IOUT[0:7] and QOUT[0:7] send into a square adder U8, it exports 1XCOROUT[00:15] be the fixedly output Xoutf of correlator;

Sampled point I[0:7 of every input] and Q[0:7], U17-U18 and the action of U28-U29 selector are once inserted sampled point in the parallel signal shift register, carry out related operation then one time, promptly carry out the sum operation that multiplies each other 192 times; Whenever the addition of once multiplying each other, the signal shift register cyclic shift is once;

7, the chip clock recovery device of quick correcting error according to claim 6 is characterized in that its physical circuit signal connection structure of described fixedly correlator is as follows:

18,19,20,21 pin of U4, U7 are formed 8 bit data bus, 18,19,20,21 pin of U24, U27 are formed 8 bit data bus, are connected respectively to the IDD[0:7 of U9] (1,3,4,5,6,7,8,9 pin) and QDD[0:7] (60,61,62,64,65,66,68 pin);

The S[8:15 of U8] (15,14,13,11,10,9,7,6 pin), meet output 1XCOROUT[8:15].

8,, it is characterized in that described its circuit connection structure of mobile correlator is as follows according to the chip clock recovery device of claim 1 or 3 described quick correcting errors:

Two shift registers are made up of U2-U7 and U22-U27FIFO (74F433) respectively; Two correlators are made of the auxiliary circuit that monolithic accumulator STEL-2410 (U9) and U11-U14 form; PNI sequence and PNQ sequence are PNIM and PNQM sequence; Two squarers, an adder and a threshold compataror are born by monolithic TMC2249A (U8);

Digital signal ID[0:7] behind U17 and U18 (74HC157) selector, entering 8 parallel-by-bit shift registers is U3 → U2 → U4, U6 → U5 → U7, digital signal QD[0:7] behind U28 and U29 (74HC157) selector, entering 8 parallel-by-bit shift registers is U23 → U22 → U24, U26 → U25 → U27; Local sequence PNIM and PNQM send into correlator U9, under the effect of master clock MAINCLK, the digital signal of input is relevant in correlator U9 with local sequence, correlated results IOUT[0:7] and QOUT[0:7] send into a square adder U8, it exports 2XCOROUT[00:15] be the fixedly output Xoutm of correlator;

Sampled point ID[0:7 of every input] and QD[0:7], U17-U18 and the action of U28-U29 selector are once inserted sampled point in the parallel signal shift register, carry out related operation then one time, promptly carry out the sum operation that multiplies each other 192 times; Whenever the addition of once multiplying each other, the signal shift register cyclic shift is once;

U11-U14 finishes 192 tally functions, after guaranteeing to make input signal and local sequence carry out 192 additions of multiplying each other, exports once result;

Aforesaid mobile correlator the and fixedly structure of correlator is basic identical, difference is: fixedly the local PN sequence (length=64) of correlator is fixed with respect to input signal, and promptly the shift clock of PNI and PNQ is PNCLK; The local sequence of mobile correlator is sudden fast moving with respect to input signal, and promptly the shift clock of PNIM and PNQM is PNCLKM.

9, the chip clock recovery device of quick correcting error according to claim 8 is characterized in that its physical circuit syndeton of described mobile correlator is as follows:

PN sign indicating number in the mobile correlator produces PN sign indicating number generation circuit in signal annexation and the fixing correlator in circuit, the mobile correlator, fixedly the signal connecting circuit structural relation in the correlator is basic identical, its difference is as follows: ID[0:7] for I[0:7], QD[0:7] for Q[0:7]; PNIM, PNQM are respectively for PNI, PNQ; The S[8:15 of U8] (15,14,13,11,10,9,7,6 pin), meet output 2-XCOROUT[8:15].

10, the chip clock recovery device of quick correcting error according to claim 1 is characterized in that described its error signal of VCO loop moves the error sum that correlator produces from the sum of errors of fixedly correlator generation;

This VCO loop, it includes an adder, three grades of shift registers, a subtracter, a D/A converter, a low pass filter and a voltage controlled oscillator VCO;

Fixedly send into three shift registers after correlator output signal Xoutf and the mobile correlator output signal Xoutm addition, the output of left and right two registers is subtracted each other, send into low pass filter again, its output is as the voltage control input of VCO, and the output of this VCO is the chip clock of recovery; This clock is also supplied with the shift clock of three grades of shift registers in the VCO loop, and despreading matched filter and the required clock of data demodulates in the receiver is provided for the shift clock of the shift register in the fixedly correlator and the correlator that is shifted.

11, the chip clock recovery device of quick correcting error according to claim 10, it is characterized in that its three grades of shift registers of described VCO loop are 8 parallel-by-bit shift registers, about the value of two register cells subtract each other departure as VCO, when after the low pass filter that connects when being analog filter, need between subtracter and filter, to insert digital to analog converter (being D/A), when being digital realization, need not D/A converter.

12,, it is characterized in that described its circuit connection structure of VCO loop is as follows according to the chip clock recovery device of claim 1 or 11 described quick correcting errors:

1XCOROUT[08:15] (being Xoutf) and reverse signal thereof, constantly lock in the latch of U11, U12 at T1 (left side) and T3 (right side), and addition in the adder that U9, U10 constitute, 1DA[0:7] come down to the error of the output of fixing correlator in left and right two moment; Similarly, 2XCOROUT[08:15] (being Xoutm) and reverse signal thereof, constantly lock in the latch of U16, U17, and addition in the adder that U14, U15 constitute 2DA[0:7 at T1 (left side) and T3 (right side)] output that comes down to mobile correlator about two constantly errors; These two errors are converted to analog signal through U1 and U2 (DAC08), and addition in U3 and U4A, send VCO U5 (MC1648) behind the low pass filter of R13 and C8 composition; Foregoing circuit has been realized Xoutf and Xoutm addition, moves into the left, center, right register, and left and right two register values are subtracted each other, D/A conversion again, and low-pass filtering waits VCO loop overall process until VCO control;

The pulse in T1, T2, three moment of T3, it is made of U6 (74161), U7 (7404) and U8 (7432) logical circuit, its input signal is the peak signal 2XCOROUT15 and the chip clock IQDMP of mobile correlator, promptly when peak value appears in mobile correlator, write down first, second, third pulse position that surpasses threshold value.

13, the chip clock recovery device of quick correcting error according to claim 12 is characterized in that its physical circuit syndeton of described VCO loop is as follows:

T1 receives 11 pin of U11, U16, and T3 receives 11 pin of U12, U17;

1XCOROUT[08:15] be connected to the D[0:7 of U11] input of (2,3,4,5,6,7,8,9 pin), U7, U13;

2XCOROUT[08:15] be connected to the D[0:7 of U16] input of (2,3,4,5,6,7,8,9 pin), U18, U13;

The output S[1:4 of U9 and U10] (4,1,13,10 pin) composition 8 bit data bus, the output S[1:4 of U14 and U15] form 8 bit data bus, be connected respectively to the B[1:8 of U1, U2] (9,10,11,12,13,14,15,16 pin);

The OUT of U5 (3 pin) is connected to output MAINCLK.

14, the chip clock recovery device of quick correcting error according to claim 1, it is characterized in that described gate circuit it produces a string high-speed pulse under starting impulse control, and this gate circuit comprises a gate, counter, an oscillator (OSC), a pulse stretcher and a trigger:

This gate circuit is exported M pulse train under starting impulse control, M is the maximum count value of the counter of setting; Starting impulse opens the sluices, and the clock that allows oscillator OSC is by gate, and unison counter is counted the clock periodicity by gate, and closed shutter when the full M of counter meter just opens the sluices again up to the arrival of next starting impulse.

15, the chip clock recovery device of quick correcting error according to claim 14, it is characterized in that described gate circuit wherein the frequency of oscillation of oscillator OSC be higher than the chip clock frequency, can make the frequency of oscillation of oscillator equal the twice of chip clock frequency; Its starting impulse is the peak pulse of mobile correlator, this pulse is given one " with door " for high level behind broadening, this " with door " also sent in the output of OSC, M is sent in the output of " with door " counter, the full back of meter carry signal triggering one trigger is a low level by the high level redirect, this level is sent into " with door " and is sealed its output, i.e. M high-speed pulse of gate circuit output just stops, the arrival of the peak pulse of mobile correlator next time in upright arrangement; The output state of above-mentioned trigger is constantly put height at the peak value of mobile correlator;

The maximum count value M of counter is provided with the erection rate that has determined the chip clock error, and M is big more, and correction is slow more, otherwise the more little correction of M is fast more; The M minimum can not be less than the sampling number of every chip, and this installs every chip samples 3 points, and the M maximum can not be greater than the fixing correlation length L of correlator and mobile correlator; When M equals L, the speed of device before the erection rate of this chip clock error equals, demodulation performance does not improve.

16, the chip clock recovery device of quick correcting error according to claim 15 is characterized in that the circuit connection structure pass of described gate circuit is:

The circuit design condition:

Direct sequence spread spectrum, spreading gain=64;

The QPSK modulation;

Every chip (Chip) sampling 3 points,

The PN sequence is the Gold sequence, length=64;

Chip clock erection rate parameter M=12=3*4, promptly per 4 chip corrections once.

17, the chip clock recovery device of quick correcting error according to claim 1, it is made up of two one symbol delay devices and two multipliers to it is characterized in that described feedback branch, behind the signal multiplication of a feedback data and a symbol delay as the output of this feedback branch, DI links to each other with DQ under the BPSK mode, and DI and DQ branch is opened under the QPSK mode.

18,, it is characterized in that its physical circuit syndeton of described gate circuit is as follows according to the chip clock recovery device of claim 1 or 17 described quick correcting errors:

This gate circuit, it comprises: oscillation source U4 (OSCB), gate U3A (74HC10) and M (M=16) counter U5 (74161); The peak value output of mobile correlator is sign bit 2XCOR-OUT15 control signal as gate after U6A (74123) pulse stretching, and the carry of M counter U5 (74161) is sent into the control signal that U10A (d type flip flop) produces closed gate; The output high-speed pulse HIGHSPEEDPULSES of gate gives mobile correlator.The clock of the U3A of gate circuit (74HC10) is from a fixing oscillator U4 (OSCB), and the frequency of OSCB is higher than the sampling rate of input signal, gets 2 times here.

19,, it is characterized in that its physical circuit syndeton of described feedback branch is as follows according to the chip clock recovery device of claim 1 or 17 described quick correcting errors:

Two multipliers are made of the XOR gate of U1A-U1D, U2A-U2D, U3A-U3D, U4A-U4D;

Local sequence is a binary sequence, the digital signal of input and the multiplying of binary sequence can replace with XOR, digital signal I[0:7 after the down-conversion in the receiver] and Q[0:7] signal DELAYI[0:7 after a data symbol postpones] be IDD[0:7]) and DELAYQ[0:7] be QDD[0:7]) respectively with feedback data bit FEEDBACKI and FEEDBACKQ step-by-step XOR, be output as ID[0:7] and QD[0:7], as the signal input of mobile correlator, FEEDBACKI here (I Data Out) and FEEDBACKQ (Q Data Out) are the output of data demodulator.

20, the chip clock recovery device of quick correcting error according to claim 1, it is that the maximum count amount is the asynchronous resetting counter of L to it is characterized in that described counter, L is the sampling number that spreading gain multiply by every chip, and it equals the fixedly correlation length of correlator and mobile correlator; This counter has reset (zero clearing) input, input end of clock and L frequency division output terminal; This counter carries out the L frequency division to input clock, makes counter O reset under the reset pulse effect immediately, its frequency division output and reset terminal signal Synchronization.

21, the chip clock recovery device of quick correcting error according to claim 20 is characterized in that its physical circuit syndeton of described L counter is as follows:

This L counter, be made of U1 (7404), U2 (74161), U7 (74161), U8 (7420) and U9 (7432) logical circuit, the input clock of circuit is chip clock IQDMP, and maximum count value L is 192, be output as CLKOUT, supply with matched filter and data demodulator; Counter is in the fixedly peak value zero clearing constantly of correlator, and the anti-phase back of 1XCOROUT15 is as the clear signal of counter U2, U7, and L counter meter is the back self-zeroing completely.

22, the chip clock recovery device of quick correcting error according to claim 1 is characterized in that its physical circuit syndeton of described gate circuit is as follows:

2XCOROUT15 is connected to 1 pin of U6A, 4 pin of U10A;

The OUT of U4 (3 pin) is connected to 1 pin of U3A, and the Q of U6A (13 pin) is connected to 2 pin of U3A, and the Q of U10A (5 pin) is connected to 13 pin of U3A;

12 pin of U3A are connected to 2 pin of U5, send output HIGHSPEEDPULSES simultaneously.