CN1089174C

CN1089174C - Radar image card

Info

Publication number: CN1089174C
Application number: CN96109208A
Authority: CN
Inventors: 陈振民; 刘华生; 尹学诚; 冯涛
Original assignee: Institute of Automation of Chinese Academy of Science
Current assignee: PANHOST INDUSTRIAL (SHENZHEN) Co Ltd
Priority date: 1996-07-29
Filing date: 1996-07-29
Publication date: 2002-08-14
Anticipated expiration: 2016-07-29
Also published as: CN1172306A

Abstract

The present invention relates to a radar image card which is used for treating trigger pulses and video images of radars, the rotation and pitching motion of antennae, etc. in real time and inputting the cases into a computer. The present invention is characterized in that the radar image card is composed of a line memory unit [2], a link signal line-by-line normalization unit [1], a decoding unit [3], etc., and the present invention belongs to an image interface technology. In the present invention, radar trigger pulses are used as time references, the rotation and pitching information of radar antennae are compressed and normalized in a radar line scan video signal blind area, and the rotation and pitching information is transmitted into a computer in a memory mapping mode during scan retrace so that the computer can simultaneously treat various cases of radars.

Description

The radar image scanning input device

The present invention relates to a kind of rotation of trigger pulse, video image and antenna, radar image scanning input device that computing machine was handled and sent into to the multiple information of luffing state in real time of being suitable for, belong to the Image Information Processing interfacing radar.

The processing of radar information and countermeasure, mainly depend on the breaths such as scene that the radar video image comprises the waveform character of atural object, target, noise, interference etc. and antenna movement state thereof etc., therefore to obtain be radar system to radar information, particularly those non intelligent radar systems extremely important problem.About this problem, mostly adopt classic methods such as data storage, recorder trace to solve at present both at home and abroad.The shortcoming of classic method is: 1, can not handle in real time; 2, can not Fast Reconstruction the scene of any time; 3, Ji Lu data is incomplete, and particularly the motion state of antenna is difficult to record.

The objective of the invention is to: press the definition of computing machine notch, design a kind of formula radar image scanning input device, this graph card is time standard with the trigger pulse, to multiple incidents such as the rotation of trigger pulse, video image and the antenna of radar, luffing state line by line normalizing handle, and penetrate by internal memory calamity and to send into computing machine, make those ordinary radars also can handle its video image in real time by appliance computer, even the configuration intelligence system.

Purpose of the present invention can realize by following proposal:

Shown in Figure 1 as radar image scanning input media schematic diagram, the present invention by signal line by line normalizing unit [1], row is deposited body unit [2], decoding unit [3] is formed; The components and parts and the connecting relation thereof of its three unit are as described below:

A, signal line by line normalizing unit [1] by photoelectrical coupler IC1 and IC13, three gate circuit IC2, IC7 and IC21, three amplifier IC20, IC26 and IC29, A/D converter IC25 and IC30, three stabilivolt D2, D3 and D4, analog switch IC11, five monostable IC3, IC6, IC10, IC12 and IC14, nine ten frequency counter IC4, IC5, IC15, IC17, IC18, IC19, IC22, IC23 and IC24, ten two divided-frequency counter IC27 and IC28, triode BG1 and BG2, diode D1, trigger IC8 and IC9, Phase Lock Loop IC 16, potentiometer W1～W4, resistor R 1～R39, capacitor C1～C18 and socket CT1～CT7 forms; The connection of IC1 is: its 5th, 7 pin ground connection, and its 1st, 3 pin connects power Vcc 2 through resistor R 1, R5 respectively, and its 6th, 8 pin connects power Vcc 1 through resistor R 2, R6 respectively, and its 2nd, 4 pin connects the socket CT1 on shell connection ground, the fuse of CT2 respectively; The connection of IC13 is: its 5th pin ground connection, and its 6th, 7 pin connects power Vcc 1 through resistor R 17, R40 respectively, and its 2nd pin connects power Vcc 2 through resistor R 16, and its 3rd pin connects the fuse of the socket CT3 on shell connection ground; The connection of IC2 is: its 1st, 4,10 pin ground connection, and its 2nd, 5 pin and Qi Di 9 pin connect the 6th, 8 pin of IC1 and the 6th pin of IC13 respectively; The connection of IC20 is: its 3rd pin is termination resistor R24 over the ground, its the 2nd pin resistors in parallel R21, R22, R23 and R25, the fuse of the socket CT4 on another termination enclosure connection ground of resistor R 21, the 4th pin of another termination IC25 of resistor R 22, the other end ground connection of resistor R 23, the other end of its 6th pin termination resistor R25; The connection of IC25 is: its 1st, 2 pin ground connection, its the 15th pin is termination resistor R27 over the ground, its the 3rd, 13 pin meets capacitor C14, C13 respectively over the ground, its the 3rd pin also and between its 16th pin meets capacitor C15, its the 14th pin resistors in parallel R26, the 1st end of potentiometer W3 and the positive pole of D3, another termination power Vcc 3 of resistor R 26, the adjustable side of the 2nd termination D3 of potentiometer W3, the 3rd end of potentiometer W3 and the minus earth of D3, its the 5th～12 pin is distinguished the 1st～8 pin of combination hub CT5, the 9th, the 10 pin ground connection of socket CT5 successively; The connection of IC29 is: its 3rd pin is termination resistor R36 over the ground, its the 2nd pin resistors in parallel R33, R34, R35 and R37, the fuse of the socket CT6 on another termination enclosure connection ground of resistor R 33, the 4th pin of another termination IC25 of resistor R 34, the other end ground connection of resistance R 35, the other end of its 6th pin termination resistor R37; The connection of IC30 is: its 1st, 2 pin ground connection, its the 15th pin is connecting resistance R39 over the ground, its the 3rd, 13 pin meets capacitor C17, C16 respectively over the ground, its the 3rd pin also and between its 16th pin meets capacitor C18, its the 14th pin resistors in parallel R38, the 1st end of potentiometer W4 and the positive pole of D4, another termination power Vcc 3 of resistor R 38, the adjustable side of the 2nd termination D4 of potentiometer W4, the 3rd end of potentiometer W4 and the minus earth of D4, its the 5th～12 pin is distinguished the 1st～8 pin of combination hub CT7, the 9th, the 10 pin ground connection of socket CT7 successively; The connection of IC11 is: its 2nd, 7 pin connects the 6th pin of IC20, IC29 respectively, the 1st pin of its 1st pin IC21 in parallel and the 6th pin of IC8, its the 8th pin connects the 2nd pin of IC21, its the 9th pin connects the 5th pin of IC9, the 3rd pin of its 16th pin resistors in parallel R8 and IC7, the other end parallel connection of its 17th pin and resistor R 8 is termination resistor R9 over the ground; The connection of IC3 is: its 4th, 7 pin ground connection, termination resistor R3 after its 3rd, 14 pin parallel connection, its the 10th pin meets capacitor C1, the other end of its 11st pin termination resistor R3 and capacitor C1 two element, the 3rd pin of its 5th pin IC2 in parallel and the 4th pin of IC9, the 1st pin of its 6th pin IC4 in parallel and the 5th pin of IC10; The connection of IC4 and IC5 is: its 3rd, 5,7 pin parallel connections separately, and its 2nd, 6,10 pin separately ground connection in parallel, the 11st pin of its IC4 connects the 1st pin of IC5; The connection of IC6 is: its 7th pin ground connection, and termination resistor R4 after its 3rd, 14 pin parallel connection, its 10th pin meets capacitor C2, the other end of its 11st pin resistors in parallel R4 and capacitor C2 two element, its 5th pin connects the 12nd pin of IC5; The connection of IC7 is: its 7th pin ground connection, and the 6th pin parallel connection of its 1st, 4 pin and IC12 is termination resistor R12 over the ground, and its 5th pin connects the 6th pin of IC6, and its 6th pin connects the 12nd pin of IC8, and its 2nd pin connects the 6th pin of IC10; The connection of IC8 is: its 7th pin ground connection, its 3rd, 4,5,9,10,11,13,14 pin parallel connection; The connection of BG1 is: the 4th pin parallel connection of its emitter and IC6 is termination resistor R10 over the ground, the positive pole of its collector and capacitor C4 connects power Vcc 1, termination resistor R11 over the ground after the negative pole of its base stage and capacitor C4 and the negative pole of D1 are in parallel, the anodal series capacitor C5 of D1 connects the 8th pin of IC8; The connection of BG2 is: the 2nd pin parallel connection of its collector and IC8 is termination resistor R14 over the ground, and the positive pole of its emitter and capacitor C7 connects power Vcc 1, and the negative pole parallel connection of its base stage and capacitor C7 is termination resistor R15 over the ground; The connection of IC9 is: its 7th pin ground connection, and its 3rd pin connects the 6th pin of IC2; The connection of IC10 is: its 4th, 7 pin ground connection, and termination resistor R7 after its 3rd, 14 pin parallel connection, its 10th pin meets capacitor C3, the other end of its 11st pin resistors in parallel R7 and capacitor C3 two element; The connection of IC14 is: its 4th, 7 pin ground connection, termination resistor R18 after its 3rd, 14 pin parallel connection, its the 10th pin meets capacitor C8, the other end of its 11st pin resistors in parallel R18 and capacitor C8 two element, its the 5th pin connects the 8th pin of IC2, and the 14th pin that its 6th pin meets IC15 is connected to the capable B point of depositing in the body [2] afterwards again; The connection of IC15 is: its 3rd, 5,7 pin parallel connection, and its 2nd, 6,10 pin ground connection, its 12 pin connects the 14th pin of IC16; The connection of IC16 is: it is the 5th years old, 8 pin ground connection, positive pole and the capacitor C11 of its 16th pin shnt capacitor C12, the other end ground connection of the negative pole of capacitor C12 and capacitor C11, it is the 6th years old, meet capacitor C10 between 7 pin, its the 13rd pin termination resistor R19, the other end parallel connection of its 9th pin and resistor R 19 meets capacitor C9 over the ground, its the 11st pin connects the 1st end of potentiometer W1, the 2nd of potentiometer W1,3 end ground connection, its the 10th pin resistors in parallel R20, the 1st end of the positive pole of D2 and potentiometer W2, another termination power Vcc 1 of resistor R 20, the 2nd end of the adjusting termination potentiometer W2 of D2, the 3rd end ground connection of the negative terminal of D2 and resistance position device W2; The connection of IC21 is: its 7th pin ground connection, and its 3rd, 5 pin also connects the 4th pin of IC16, and its 4th, 6 pin connects the 1st pin of IC22 and IC27 respectively; The connection of six counter IC17, IC18, IC19, IC22, IC23, IC24 is: its 2nd, 6,10 pin separately ground connection in parallel, its the 3rd, 5,7 pin parallel connections separately, its the 11st, 14 pin parallel connections separately, the 12nd pin of its IC22 connects the 1st pin of IC23, the 12nd pin of its IC23 connects the 1st pin of IC24, the 12nd pin of its IC24 connects the 1st pin of IC19, the 12nd pin of its IC19 connects the 14th pin of IC18, the 14th pin of the 12nd pin of its IC18 IC17 in parallel and the 5th pin of IC12, the 12nd pin of its IC17 connects the 3rd pin of IC16; The connection of IC12 is: its 4th, 7 pin ground connection, and termination resistor R13 after its 3rd, 14 pin parallel connection, its 10th pin meets capacitor C6, the other end of its 11st pin resistors in parallel R3 and capacitor C6 two element; The connection of IC27 is: its 10th pin ground connection, and its 5th, 6 pin parallel connection, its 9th pin connects the 1st pin of IC28; The connection of IC28 is: its 10th pin ground connection, and its 5th, 6 pin parallel connection, its 7th pin connects after the 7th pin of IC27 also and its 9th pin is connected to capable C, the D point of depositing in the body unit [2] respectively; The connection of IC26 is: its 3rd pin is termination resistor R32 over the ground, its the 2nd pin resistors in parallel R28～R31, the other end of resistor R 29, R30 connects the 3rd, 6 pin of IC11 respectively, the other end of resistor R 28 is connected to the 17th pin of IC11, is connected to the capable A point of depositing in the body unit [2] after the other end of its 6th pin termination resistor R31; + 5V power Vcc 1 ,+5V digital power Vcc2 ,+15V power Vcc 3 and-15V power Vcc 4 gives each chip power supply;

B, row is deposited body unit [2] by three monostable IC31, IC33 and IC35, triode BG3, diode D5 and D6, gate circuit IC21 and IC32, three three-stable state IC36, IC42 and IC43, trigger IC34, three counter IC37, IC38 and IC39, A/D converter IC40, memory IC 41, clear 0 K switch 1, resistor R 40～R46 and capacitor C19～C33 form, wherein: the connection of IC31 is: it is the 4th years old, 7 pin ground connection, it is the 3rd years old, termination resistor R40 after the 14 pin parallel connections, its the 10th pin meets capacitor C19, the other end of its 11st pin resistors in parallel R40 and capacitor C19 two element, its 5th pin is connected to signal the 6th pin of the IC14 in normalizing unit [1] line by line through interface B; BG3, two diode D5, D6, the connection of gate circuit IC21 and five devices of K1 is: the 1st termination power Vcc1 of the collector of BG3 and K1, the base stage of BG3 and the negative pole of D5 termination resistor over the ground in parallel R42, the positive pole of D5 over the ground termination resistor R41 the time also through 6th pin of capacitor C20 series connection to IC31, the emitter resistors in parallel R43 of BG3, the negative pole of D6, capacitor C22, K1 the 2nd end, the 3rd pin of IC37～39, the 13rd pin of IC21 and interface C, the ground connection anodal in parallel of the other end of resistor R 43 and capacitor C22 and D6, interface C is connected to signal the 7th pin of the IC27 in normalizing unit [1] line by line again, the the 1st and the 13rd pin of the 12nd pin of IC21 IC34 in parallel, the 9th pin of IC21 connects the 10th pin, the 1st of the 8th pin of IC21 IC32 in parallel, 2 pin, the 3rd of IC34, the 5th pin of 11 pin and IC35; The connection of IC32 is: its 7th pin ground connection, and its 3rd, 4 pin connects the 5th, 6 pin of IC33 respectively, and its 6th pin connects the 21st pin of IC41; The connection of IC33 is: its 4th, 7 pin ground connection, and termination resistor R22 after its 3rd, 14 pin parallel connection, its 10th pin meets capacitor C21, the other end of its 11st pin resistors in parallel R22 and capacitor C21 two element; The connection of IC35 is: its 4th, 7 pin ground connection, and termination resistor R45 after its 3rd, 14 pin parallel connection, its 10th pin meets capacitor C23, the other end of its 11st pin resistors in parallel R45 and capacitor C23 two element, its 6th pin connects the 18th pin of IC40; The connection of IC34 is: its 7th pin ground connection, and its 5th pin connects its 12nd pin, and its 2nd pin connects the 9th pin of IC39, and its 9th pin connects the 4th pin of IC36, the 14th pin, the 1st, 9 pin of IC36 and the 5th pin of IC32 of its 8th pin IC40 in parallel; The connection of IC36 is: its 7th pin ground connection, the 14th pin of its 3rd, 6 pin IC37 in parallel, its the 2nd pin connects after the 11st pin of IC21 through interface D again and is connected to signal the 9th pin of the IC28 in normalizing unit [1] line by line, and its 5th, 8 pin is connected to the 13rd pin of the IC44 in the decoding unit [3], the 9th pin of CT8 respectively after connecting the 11st pin of the 20th pin, IC43 of IC41 respectively again; The connection of IC37 is: its 10th pin ground connection, and its 2nd pin connects its 5th pin, the 8th pin of its 1st, 12 pin IC41 in parallel, its 9th, 8 pin connects the 7th, 6 pin of IC41 respectively, the 14th pin of its 11st pin IC38 in parallel and the 5th pin of IC41; The connection of IC38 is: its 10th pin ground connection, and its 2nd pin connects the 5th pin, the 4th pin of its 1st, 12 pin IC41 in parallel, its 9th, 8 pin connects the 3rd, 2 pin of IC39 respectively, the 14th pin of its 11st pin IC39 in parallel and the 1st pin of IC41; The connection of IC39 is: its 10th pin ground connection, and its 2nd pin connects its 5th pin, the 23rd pin of its 1st, 12 pin IC41 in parallel; The connection of IC40 is: its 1st～8 pin connects the 9th of IC41 successively respectively, 10,11,13,14,15,16, also connect the 2nd of IC42 in the time of 17 pin successively respectively, 5,9, the 2nd of 12 pin and IC43,5,9,12 pin, it is the 11st years old, 15,17,19 pin ground connection, it is the 10th years old, 15,20,23 pin meet capacitor C28～C31 successively respectively over the ground, its the 24th pin meets positive pole and the capacitor C24 of capacitor C25, the other end ground connection of the negative pole of capacitor C25 and capacitor C24, it is the 12nd years old, meet positive pole and the capacitor C27 of capacitor C26 after the 13 pin parallel connections, the other end ground connection of the negative pole of capacitor C26 and capacitor C27, its the 22nd pin resistors in parallel R46, the 1st end of the positive pole of D7 and potentiometer W5, another termination power Vcc 3 of resistor R 46, the 2nd end of the adjusting termination potentiometer W5 of D7, the 3rd end ground connection of the negative terminal of D7 and potentiometer W5, it is the 16th years old, 21 pin parallel connections are after interface A is connected to signal the 6th pin of the IC26 in normalizing unit [1] line by line; The connection of IC41 is: its 18th, 19,22 pin ground connection, positive pole and the capacitor C33 of its 24th pin shnt capacitor C32, the other end ground connection of the negative pole of capacitor C32 and capacitor C33; The connection of IC42, IC43 is: its two the 7th pin ground connection, its the two the 1st, 4,10,13 pin all and be attached to the 12nd pin of the IC44 in the decoding unit [3], the 3rd, 6,8,11 pin of its IC42 and the 3rd, 6,8,11 pin of IC43 are connected to the 2nd～9 pin of the A face of the plug CT8 in the decoding unit [3] successively respectively; + 5V power Vcc 1 ,+5V digital power Vcc2 and+15V power Vcc 3 gives each chip power supply;

C, decoding unit [3] are made up of gate circuit IC44, IC45, IC46, IC47 and plug CT8, wherein: the connection of IC44 is: its 7th pin ground connection, its the 1st, 3 pin is the 11st, 23 pin of plug CT8 A face respectively, its the 8th, 11 pin connects the 13rd, 6 pin of IC47 respectively, and its 10th pin connects its 13rd pin; The connection of IC45 is: its 7th pin ground connection, and the 14th pin of its 1st pin plug CT8 B face, its 2nd, 4,5 pin be the 24th, 29,30 pin of plug CT8 A face respectively, and its 6th pin connects the 5th pin of IC44; The connection of IC46 is: its 7th pin ground connection, its the 2nd, 5,6,11,12 pin is distinguished the 22,25～28 pin of plug CT8 A face successively, its the 1st, 3 pin connects the 2nd, 4 pin of IC44 respectively, and its 4th pin connects the 3rd pin of IC45, the 1st, 4 pin of its 8th pin IC47 in parallel; The connection of IC47 is: its 7th pin ground connection, and the 6th pin of its 2nd, 3 pin IC44 in parallel, the 31st pin of its 5th pin plug CT8 A face and the 9th pin of IC44, its 12nd pin are connected to the 10th pin that row is deposited the IC36 in the body unit [2]; + 5V power Vcc 1 is given each chip power supply.

The invention has the advantages that:

1, handles by normalizing line by line and penetrate and send into computing machine with the internal memory calamity, make computing machine can handle multiple incidents such as the rotation of trigger pulse, video image and the antenna of radar, luffing state in real time, even make those common radars, also can handle its video image even configuration intelligence system in real time by appliance computer;

2,, and provide distance, orientation, height and waveform character or the like the information of its atural object, Zheng Bei, target, interference etc. by capable addressing can reappear the digital picture of the on-the-spot radar of any time fast to normalizing;

3, no standard restriction, and the various radars of compatible with digital amount and analog quantity.

Description of drawings:

Fig. 1 is a radar image scanning input device schematic diagram, and among the figure: [1] is signal normalizing element circuit figure line by line; [2] be that row is deposited body unit; [3] be decoding unit; A, B, C, D are signal normalizing unit [1] and the capable interface of body unit [2] of depositing line by line;

Fig. 2 is the circuit diagram that row is deposited body unit [2] and decoding unit [3].

Embodiment:

This radar image scanning input device according to the requirement of its applied environment, can be applied in desk-top computer, notebook and the embedded special purpose computer.Here be object with the desk-top computer,, be illustrated as an embodiment.

Present embodiment is pressed the circuit requirement of Fig. 1, Fig. 2, it is designed in a printed board, form the radar image scanning input device of a whole straight cutting, wherein plug CT8 is made in the printed board according to the desk-top computer standard, so that directly insert within the standard notch that the computing machine master pulls, signal plug CT1～CT7 then is configured in the Hou side of its radar image scanning input device, so that the radar image scanning input device inserts the computing machine master and pulls notch Hou, can draw its signal electricity from the Hou face of computing machine and look at and be connected to radar, obtain radar information.

Shown in Figure 1 as schematic diagram, present embodiment by signal line by line normalizing unit [1], row is deposited body unit [2], decoding unit [3] is formed.The components and parts of its each unit, connecting relation itself and the principle of work and power be as follows:

B, row is deposited body unit [2] as shown in Figure 2, by three monostable 74LS121 IC31, IC33 and IC35, triode 3DG237 BG3, two diode 1N4148 D5 and D6, gate circuit 74LS04 IC21,74LS03 IC32, three three-stable state 74LS126 IC36, IC42 and IC43, trigger 74LS74 IC34, three counter 74LS93 IC37, IC38 and IC39, A/D converter CA3318CE IC40, storer HY6116 IC41, clear 0 K switch 1, resistor R 40～R46 and capacitor C19～C33 form, wherein: the connection of 74LS121 IC31 is that it is the 4th years old, 7 pin ground connection, it is the 3rd years old, termination resistor R40 after the 14 pin parallel connections, its the 10th pin meets capacitor C19, the other end of its 11st pin resistors in parallel R40 and capacitor C19 two element, its the 5th pin is connected to signal the 6th pin of the 74LS121 IC14 in normalizing unit [1] line by line through interface B; 3DG237 BG3, two diode 1N4148 D5, D6, the connection of gate circuit chip 74S04 IC21 and five devices of K1 is, the 1st termination power Vcc1 of the collector of 3DG237 BG3 and K1, the base stage of 3DG237 BG3 and the negative pole of IN4148 D5 termination resistor over the ground in parallel R42, the positive pole of IN4148 D5 also is connected to the 6th pin of 74LS121 IC31 over the ground termination resistor R41 the time through capacitor C20, the emitter resistors in parallel R43 of 3DG237 BG3, the negative pole of 1N4148D6, capacitor C22, K1 the 2nd end, the 3rd pin of three 74LS93 IC37～39, the 13rd pin of 74LS04 IC21 and interface C, the ground connection anodal in parallel of the other end of resistor R 43 and capacitor C22 and C1N4148 D6, interface C is connected to signal the 7th pin of the 74LS92 IC27 in normalizing unit [1] line by line again, the the 1st and the 13rd pin of the 12nd pin of 74LS04 IC21 74LS74 IC34 in parallel, the 9th pin of 74LS04 IC21 connects the 10th pin, the 1st of the 8th pin of 74LS04 IC21 74LS30 IC32 in parallel, 2 pin, the 3rd of 74LS74 IC34, the 5th pin of 11 pin and 74LS121IC35, these devices and connecting relation thereof constitute clear 0 circuit with above-mentioned 74LS121 IC31, and export clear 0 signal from the emitter of 3DG237 BG3; The connection of 74LS03 IC32 is that its 7th pin ground connection, its 3rd, 4 pin connect the 5th, 6 pin of 74LS121 IC33, the 21st pin that its 6th pin meets HY6116 IC41 respectively; The connection of 74LS121 IC33 is that termination resistor R22, its 10th pin connect the other end of capacitor C21, its 11st pin resistors in parallel R22 and capacitor C21 two element after its 4th, 7 pin ground connection, its 3rd, 14 pin parallel connection; The connection of 74LS121 IC35 is, termination resistor R45, its 10th pin connect the other end of capacitor C23, its 11st pin resistors in parallel R45 and capacitor C23 two element, the 18th pin that its 6th pin meets CA3318 IC40 after its 4th, 7 pin ground connection, its 3rd, 14 pin parallel connection, 74LS04 IC21,74LS03 IC32, the 74LS121 IC33 of this connection of this chip 74LS121 IC35 in above-mentioned connection constitutes and interviews and writes signal circuit, and export respectively from the 6th pin of its 74LL121 IC35 and 74LS03 IC32 adopt, signal; The connection of 74LS74 IC34 is that its 7th pin ground connection, its 5th pin connect the 12nd pin, its 2nd pin connects the 9th pin of 74LS93 IC39, the 4th pin that its 9th pin meets 74LS126 IC36, the 14th pin, the 1st, 9 pin of 74LS126 IC36 and the 5th pin of 74LS03 IC32 of its 8th pin CA3318C IC40 in parallel; The connection of 74LS126 IC36 is, is connected to signal through interface D again after the 14th pin of its 7th pin ground connection, its 3rd, 6 pin 74LS93 IC37 in parallel, the 11st pin that its 2nd pin meets 74LS04 IC21 and is connected to the 13rd pin of the 74LS04 IC44 in the decoding unit [3], the 9th pin of CT8 more respectively after the 11st pin of the 9th pin, the 20th pin that its 5th, 8 pin connects HY6116 IC41 respectively, the 74LS126 IC43 of the 74LS92 IC28 in normalizing unit [1] line by line; The connection of 74LS93 IC37 is that its 10th pin ground connection, its 2nd pin connect the 8th pin of the 5th pin, its 1st, 12 pin HY6116 IC41 in parallel, the 7th, 6 pin that its 9th, 8 pin meets HY6116 IC41 respectively, the 14th pin of its 11st pin 74LS93 IC38 in parallel and the 5th pin of HY6116 IC41; The connection of 74LS93 IC38 is that its 10th pin ground connection, its 2nd pin connect the 4th pin of the 5th pin, its 1st, 12 pin HY6116IC41 in parallel, the 3rd, 2 pin that its 9th, 8 pin meets HY6116 IC39 respectively, the 14th pin of its 11st pin 74LS93 IC39 in parallel and the 1st pin of HY6116 IC41; The connection of 74LS93 IC39 is, its the 10th pin ground connection, its 2nd pin connect the 23rd pin of the 5th pin, its 1st, 12 pin HY6116 IC41 in parallel, this connection of this chip 74LS93 IC19 74LS74 IC34,74LS126 IC36, two 74LS93 IC37, IC38 in above-mentioned connection constitute the multiplexing address circuit, form multiplexing address, and allow signal from the 8th, the 9 pin output reading and writing of its 74LS74 IC34; The connection of CA3318CE IC40 is, its the 1st～8 pin connects the 9th of HY6116 IC41 successively respectively, 10,11,13,14,15,16, also connect the 2nd of 74LS126 IC42 in the time of 17 pin successively respectively, 5,9, the 2nd of 12 pin and 74LS126 IC43,5,9,12 pin, it is the 11st years old, 15,17,19 pin ground connection, it is the 10th years old, 15,20,23 pin meet capacitor C28～C31 successively respectively over the ground, its the 24th pin meets positive pole and the capacitor C24 of capacitor C25, the other end ground connection of the negative pole of capacitor C25 and capacitor C24, it is the 12nd years old, meet positive pole and the capacitor C27 of capacitor C26 after the 13 pin parallel connections, the other end ground connection of the negative pole of capacitor C26 and capacitor C27, its the 22nd pin resistors in parallel R46, the 1st end of the positive pole of LM336-5.0 D7 and potentiometer W5, another termination power Vcc 3 of resistor R 46, the 2nd end of the adjusting termination potentiometer W5 of LM336-5.0 D7, the 3rd end ground connection of the negative terminal of LM336-5.0 D7 and potentiometer W5, it is the 16th years old, 21 pin parallel connections are after interface A is connected to signal the 6th pin of the LM318 IC26 in normalizing unit [1] line by line; The connection of HY6116 IC41 is, the positive pole of its 18th, 19,22 pin ground connection, its 24th pin shnt capacitor C32 and the negative pole of capacitor C33, capacitor C32 and the other end ground connection of capacitor C33, the CA3318 IC40 of this connection of this chip HY6116IC41 in above-mentioned connection constitutes the A/D memory circuit, and radar normalizing signal is carried out A/D conversion and storage line by line; The connection of two 74LS126 IC42, IC43 is, its the two the 7th pin ground connection, its two the 1st, 4,10,13 pin all and the 3rd, 6,8,11 pin that are attached to the 3rd, 6,8,11 pin of the 12nd pin, its IC42 of the 74LS04 IC44 in the decoding unit [3] and IC43 be connected to the 2nd～9 pin of the A face of the plug CT8 in the decoding unit [3] successively respectively, this connection composition data on-off circuit of this chip 74LS126 IC42, IC43, regularly with radar line by line the normalizing data send into computing machine; + 5V power Vcc 1 ,+5V digital power Vcc2 and+15V power Vcc 3 gives each chip power supply;

C, decoding unit [3] are as shown in Figure 3, formed by gate circuit 74LS04 IC44,74LS26 IC45,74LS30 IC46,74LS27 IC47 and plug CT8, wherein: the connection of 74LS04 IC44 is, the 11st of plug CT8A face the, 23 pin, its 8th, 11 pin connect the 13rd, 6 pin, its 10th, 13 pin parallel connection of 74LS27 IC47 respectively respectively successively for its 7th pin ground connection, its 1st, 3 pin; The connection of 74LS26 IC45 is, the 14th pin of its 7th pin ground connection, its 1st pin plug CT8 B face, its 2nd, 4,5 pin be the 24th, 29,30 pin, the 5th pin that its 6th pin meets 74LS04 IC44 of plug CT8 A face respectively; The connection of 74LS30 IC46 is that the 22nd of plug CT8A face the, 25～28 pin, its 1st, 3 pin connect the 2nd, 4 pin of 74LS04 IC44, the 3rd pin that its 4th pin meets 74LS26IC45, the 1st, 4 pin of its 8th pin 74LS27 IC47 in parallel successively respectively respectively successively for its 7th pin ground connection, its 2nd, 5,6,11,12 pin; The connection of 74LS27 IC47 is, its the 7th pin ground connection, it is the 2nd years old, the 6th pin of 3 pin 74LS04 IC44 in parallel, the 31st pin of its 5th pin plug CT8 A face and the 9th pin of 74LS04 IC44, its the 12nd pin is connected to the 10th pin that row is deposited the 74LS126 IC36 in the body unit [2], 74LS04 IC44 in this connection of this chip 74LS27 IC47 and above-mentioned the connection, 74LS126 IC45,74LS30 IC46 constitutes the interface IP address circuit together, form respectively at the 10th pin of the 12nd pin of its 74LS27 IC47 and 74LS04 IC44 and to read to allow signal, be used to detect address 279H and read clock address 278H; The 2nd～9 pin of plug CT8A face is connected to row and deposits body unit [2]; + 5V power Vcc 1 is given each chip power supply.

The method applied in the present invention, be as time reference with the radar trigger pulse, the rotation of radar antenna, pitching Information Compression normalizing among the blind area of radar line scanning vision signal, and among the time of its scan retrace, send into computing machine in the internal memory calamity mode of penetrating, make computing machine both can handle the multiple incident of radar simultaneously, can recover the full detail of antenna movement state again by decompression processing, for real-time processing.Circuit theory according to the designed circuit diagram of this method is as follows:

1, normalizing unit [1] as shown in Figure 1 line by line for signal, it is as time reference with trigger pulse, pass through phase-locked loop circuit, provide clear line by line 0 signal, normalizing clock and address clock, and under the management of its normalizing clock, carry out following processing: by the antenna condition compressor circuit, rotation, the pitching signal of the light lotus root being isolated handled radar antenna compress processing, obtain rotation, pitching compressed signal; Antenna condition normalizing circuit carries out normalizing with above-mentioned rotation, pitching compressed signal to be handled, and obtains rotation, pitching compression normalizing signal and embeds among the scan video blind area; The normalizing supercircuit is subjected to the control of normalizing control circuit line by line, and above-mentioned rotation, pitching compression normalizing signal and the handled vision signal of video circuit are superimposed as normalizing radar signal line by line together.

2, row is deposited body unit [2] as shown in Figure 2: clear 0 circuit, provide clear line by line 0 signal, and guarantee the time synchronized of radar image scanning input device; Interview and write circuit, according to the signal address clock sequential in normalizing unit [1] line by line, regularly obtain to adopt, write signal; The multiplexing address circuit, in the scan(ing) stroke after clear 0 line by line, 74LS74 IC34 remains on and writes enable state, its signal of gating is the address clock in normalizing unit [1] line by line, provide the write address of HY6116IC41 through 74LS93 IC37～IC39 frequency division Hou, last two function of this address is to be used for compensating two initial invalid datas of CA3318CE IC40 and to pass through 74LS74 IC34 obtaining two clock delays, so that 74LS74 IC34 is transformed into and reads enable state by writing enable state, finish scan(ing) stroke and enter the journey scan retrace, 278H address clock in the gating decoding unit [3], through 74LS93 IC37～IC39 frequency division, provide the address of reading of HY6116 IC41, this is read, write the conversion of process, be to detect by timing by software to read to the 279H address, write enable state identification management, because it is read, write enable state and be with trigger pulse as time reference, can guarantee that therefore the state of the processing of computing machine and radar is harmonious; The A/D memory circuit, according to the control of above-mentioned signal, the trace of scanning will be line by line the normalizing radar signal carry out A/D conversion, storage, and give the retrace interval that has stayed a scanning so that institute's canned data is read;

3, decoding unit [3] as shown in Figure 2, because plug CT8 is according to the standard notch design of computing machine, read to allow to detect address 279H and read clock address 278H because of beguine forms according to its interface IP address circuit, just row can be deposited the radar digital signal of normalizing line by line of storage in the body unit [2] by software and send into computing machine in the internal memory calamity mode of penetrating.

Claims

1, a kind of rotation of trigger pulse, video image and antenna to radar, radar image scanning input device that computing machine was handled and sent into to the multiple information of luffing state in real time of being suitable for is characterized in that: this radar image scanning input device by signal line by line normalizing unit [1], row is deposited body unit [2], decoding unit [3] is formed; The components and parts and the connecting relation thereof of its three unit are as described below:

A, signal line by line normalizing unit [1] by photoelectrical coupler IC1 and IC13, three gate circuit IC2, IC7 and IC21, three amplifier IC20, IC26 and IC29, A/D converter IC25 and IC30, three stabilivolt D2, D3 and D4, analog switch IC11, five monostable IC3, IC6, IC10, IC12 and IC14, nine ten frequency counter IC4, IC5, IC15, IC17, IC18, IC19, IC22, IC23 and IC24, ten two divided-frequency counter IC27 and IC28, triode BG1 and BG2, diode D1, trigger IC8 and IC9, Phase Lock Loop IC 16, potentiometer W1～W4, resistor R 1～R39, capacitor C1～C18 and socket CT1～CT7 forms; The connection of IC1 is: its 5th, 7 pin ground connection, and its 1st, 3 pin connects power Vcc 2 through resistor R 1, R5 respectively, and its 6th, 8 pin connects power Vcc 1 through resistor R 2, R6 respectively, and its 2nd, 4 pin connects the socket CT1 on shell connection ground, the fuse of CT2 respectively; The connection of IC13 is: its 5th pin ground connection, and its 6th, 7 pin connects power Vcc 1 through resistor R 17, R40 respectively, and its 2nd pin connects power Vcc 2 through resistor R 16, and its 3rd pin connects the fuse of the socket CT3 on shell connection ground; The connection of IC2 is: its 1st, 4,10 pin ground connection, and its 2nd, 5 pin and Qi Di 9 pin connect the 6th, 8 pin of IC1 and the 6th pin of IC13 respectively; The connection of IC20 is: its 3rd pin is termination resistor R24 over the ground, its the 2nd pin resistors in parallel R21, R22, R23 and R25, the fuse of the socket CT4 on another termination enclosure connection ground of resistor R 21, the 4th pin of another termination IC25 of resistor R 22, the other end ground connection of resistor R 23, the other end of its 6th pin termination resistor R25; The connection of IC25 is: its 1st, 2 pin ground connection, its the 15th pin is termination resistor R27 over the ground, its the 3rd, 13 pin meets capacitor C14, C13 respectively over the ground, its the 3rd pin also and between its 16th pin meets capacitor C15, its the 14th pin resistors in parallel R26, the 1st end of potentiometer W3 and the positive pole of D3, another termination power Vcc 3 of resistor R 26, the adjustable side of the 2nd termination D3 of potentiometer W3, the 3rd end of potentiometer W3 and the minus earth of D3, its the 5th～12 pin is distinguished the 1st～8 pin of combination hub CT5, the 9th, the 10 pin ground connection of socket CT5 successively; The connection of IC29 is: its 3rd pin is termination resistor R36 over the ground, its the 2nd pin resistors in parallel R33, R34, R35 and R37, the fuse of the socket CT6 on another termination enclosure connection ground of resistor R 33, the 4th pin of another termination IC25 of resistor R 34, the other end ground connection of resistance R 35, the other end of its 6th pin termination resistor R37; The connection of IC30 is: its 1st, 2 pin ground connection, its the 15th pin is connecting resistance R39 over the ground, its the 3rd, 13 pin meets capacitor C17, C16 respectively over the ground, its the 3rd pin also and between its 16th pin meets capacitor C18, its the 14th pin resistors in parallel R38, the 1st end of potentiometer W4 and the positive pole of D4, another termination power Vcc 3 of resistor R 38, the adjustable side of the 2nd termination D4 of potentiometer W4, the 3rd end of potentiometer W4 and the minus earth of D4, its the 5th～12 pin is distinguished the 1st～8 pin of combination hub CT7, the 9th, the 10 pin ground connection of socket CT7 successively; The connection of IC11 is: its 2nd, 7 pin connects the 6th pin of IC20, IC29 respectively, the 1st pin of its 1st pin IC21 in parallel and the 6th pin of IC8, its the 8th pin connects the 2nd pin of IC21, its the 9th pin connects the 5th pin of IC9, the 3rd pin of its 16th pin resistors in parallel R8 and IC7, the other end parallel connection of its 17th pin and resistor R 8 is termination resistor R9 over the ground; The connection of IC3 is: its 4th, 7 pin ground connection, termination resistor R3 after its 3rd, 14 pin parallel connection, its the 10th pin meets capacitor C1, the other end of its 11st pin termination resistor R3 and capacitor C1 two element, the 3rd pin of its 5th pin IC2 in parallel and the 4th pin of IC9, the 1st pin of its 6th pin IC4 in parallel and the 5th pin of IC10; The connection of IC4 and IC5 is: its 3rd, 5,7 pin parallel connections separately, and its 2nd, 6,10 pin separately ground connection in parallel, the 11st pin of its IC4 connects the 1st pin of IC5; The connection of IC6 is: its 7th pin ground connection, and termination resistor R4 after its 3rd, 14 pin parallel connection, its 10th pin meets capacitor C2, the other end of its 11st pin resistors in parallel R4 and capacitor C2 two element, its 5th pin connects the 12nd pin of IC5; The connection of IC7 is: its 7th pin ground connection, and the 6th pin parallel connection of its 1st, 4 pin and IC12 is termination resistor R12 over the ground, and its 5th pin connects the 6th pin of IC6, and its 6th pin connects the 12nd pin of IC8, and its 2nd pin connects the 6th pin of IC10; The connection of IC8 is: its 7th pin ground connection, its 3rd, 4,5,9,10,11,13,14 pin parallel connection; The connection of BG1 is: the 4th pin parallel connection of its emitter and IC6 is termination resistor R10 over the ground, the positive pole of its collector and capacitor C4 connects power Vcc 1, termination resistor R11 over the ground after the negative pole of its base stage and capacitor C4 and the negative pole of D1 are in parallel, the anodal series capacitor C5 of D1 connects the 8th pin of IC8; The connection of BG2 is: the 2nd pin parallel connection of its collector and IC8 is termination resistor R14 over the ground, and the positive pole of its emitter and capacitor C7 connects power Vcc 1, and the negative pole parallel connection of its base stage and capacitor C7 is termination resistor R15 over the ground; The connection of IC9 is: its 7th pin ground connection, and its 3rd pin connects the 6th pin of IC2; The connection of IC10 is: its 4th, 7 pin ground connection, and termination resistor R7 after its 3rd, 14 pin parallel connection, its 10th pin meets capacitor C3, the other end of its 11st pin resistors in parallel R7 and capacitor C3 two element; The connection of IC14 is: its 4th, 7 pin ground connection, termination resistor R18 after its 3rd, 14 pin parallel connection, its the 10th pin meets capacitor C8, the other end of its 11st pin resistors in parallel R18 and capacitor C8 two element, its the 5th pin connects the 8th pin of IC2, and the 14th pin that its 6th pin meets IC15 is connected to the capable B point of depositing in the body [2] afterwards again; The connection of IC15 is: its 3rd, 5,7 pin parallel connection, and its 2nd, 6,10 pin ground connection, its 12nd pin connects the 14th pin of IC16; The connection of IC16 is: it is the 5th years old, 8 pin ground connection, positive pole and the capacitor C11 of its 16th pin shnt capacitor C12, the other end ground connection of the negative pole of capacitor C12 and capacitor C11, it is the 6th years old, meet capacitor C10 between 7 pin, its the 13rd pin termination resistor R19, the other end parallel connection of its 9th pin and resistor R 19 meets capacitor C9 over the ground, its the 11st pin connects the 1st end of potentiometer W1, the 2nd of potentiometer W1,3 end ground connection, its the 10th pin resistors in parallel R20, the 1st end of the positive pole of D2 and potentiometer W2, another termination power Vcc 1 of resistor R 20, the 2nd end of the adjusting termination potentiometer W2 of D2, the 3rd end ground connection of the negative terminal of D2 and resistance position device W2; The connection of IC21 is: its 7th pin ground connection, and its 3rd, 5 pin also connects the 4th pin of IC16, and its 4th, 6 pin connects the 1st pin of IC22 and IC27 respectively; The connection of six counter IC17, IC18, IC19, IC22, IC23, IC24 is: its 2nd, 6,10 pin separately ground connection in parallel, its the 3rd, 5,7 pin parallel connections separately, its the 11st, 14 pin parallel connections separately, the 12nd pin of its IC22 connects the 1st pin of IC23, the 12nd pin of its IC23 connects the 1st pin of IC24, the 12nd pin of its IC24 connects the 1st pin of IC19, the 12nd pin of its IC19 connects the 14th pin of IC18, the 14th pin of the 12nd pin of its IC18 IC17 in parallel and the 5th pin of IC12, the 12nd pin of its IC17 connects the 3rd pin of IC16; The connection of IC12 is: its 4th, 7 pin ground connection, and termination resistor R13 after its 3rd, 14 pin parallel connection, its 10th pin meets capacitor C6, the other end of its 11st pin resistors in parallel R3 and capacitor C6 two element; The connection of IC27 is: its 10th pin ground connection, and its 5th, 6 pin parallel connection, its 9th pin connects the 1st pin of IC28; The connection of IC28 is: its 10th pin ground connection, and its 5th, 6 pin parallel connection, its 7th pin connects after the 7th pin of IC27 also and its 9th pin is connected to capable C, the D point of depositing in the body unit [2] respectively; The connection of IC26 is: its 3rd pin is termination resistor R32 over the ground, its the 2nd pin resistors in parallel R28～R31, the other end of resistor R 29, R30 connects the 3rd, 6 pin of IC11 respectively, the other end of resistor R 28 is connected to the 17th pin of IC11, is connected to the capable A point of depositing in the body unit [2] after the other end of its 6th pin termination resistor R31; + 5V power Vcc 1 ,+5V digital power Vcc2 ,+15V power Vcc 3 and-15V power Vcc 4 gives each chip power supply;

C, decoding unit [3] are made up of gate circuit IC44, IC45, IC46, IC47 and plug CT8, wherein: the connection of IC44 is: its 7th pin ground connection, its the 1st, 3 pin is the 11st, 23 pin of plug CT8 A face respectively, its the 8th, 11 pin connects the 13rd, 6 pin of IC47 respectively, and its 10th pin connects its 13rd pin; The connection of IC45 is: its 7th pin ground connection, and the 14th pin of its 1st pin plug CT8 B face, its 2nd, 4,5 pin be the 24th, 29,30 pin of plug CT8 A face respectively, and its 6th pin connects the 5th pin of IC44; The connection of IC46 is: its 7th pin ground connection, its the 2nd, 5,6,11,12 pin is distinguished the 22nd, 25～28 pin of plug CT8 A face successively, its the 1st, 3 pin connects the 2nd, 4 pin of IC44 respectively, and its 4th pin connects the 3rd pin of IC45, the 1st, 4 pin of its 8th pin IC47 in parallel; The connection of IC47 is: its 7th pin ground connection, and the 6th pin of its 2nd, 3 pin IC44 in parallel, the 31st pin of its 5th pin plug CT8 A face and the 9th pin of IC44, its 12nd pin are connected to the 10th pin that row is deposited the IC36 in the body unit [2]; + 5V power Vcc 1 is given each chip power supply.