CN1185856C - Image scanning memory - Google Patents

Abstract

The present invention provides a technical scheme of an image scanning memory, which is characterized in that the present invention is composed of two stage control memories, a bus controller and an SCSI interface, wherein the first stage control memory is composed of a programmable logic array, a correction memory and a collection buffer memory, and can be mainly used for providing various clock signals, line synchronizing signals and motor control signals; image data can be output after the image data is collected for correction and two-valued pattern processing; the second stage control memory is composed of a programmable logic array and a transmission buffer memory, and mainly adopts a transfer pattern to receive the image data; then, the image data can be converted to a DMA pattern and output to the SCSI interface.

Description

A kind of image scanning memory

Affiliated technical field:

The present invention relates to be a kind of be a kind of image scanning memory in scanner, the especially scanner of scanning input with contact image scanning sensor CIS.

Background technology:

Image scanning memory is the middle bridge that visual sampled data and pictorial data transmit, and also is the principal element that influences sweep speed.One page file is decided by three parts used sweep time, and one is the sweep time of every row and the sweep time that the number of scanning lines is determined, its two, be to forward next line to after finishing a line scanning, the paper feed time of motor, its three, be the delivery time of scan-data.After contact image sensor CIS was selected, the paper feed time of sweep time and motor was definite substantially, if will improve sweep speed, can only improve the transmission speed of scanned picture data, just will improve the data transmission bauds of image scanning memory.In the prior art, common image scanning memory is an one-level storage, the image scanning memory of single-stage is in scanning process, the data of each sampled point are deposited in video memory, delegation's rear motor paper feed is finished in every scanning, then, the pictorial data of full line is sent out by small computer system interface SCSI, the advantage of this single-stage image scanning memory is lower to the capacity requirement of memory, its weak point is in one-level storage, the data/address bus that the sampled data of image and pictorial data can not take memory simultaneously, therefore cause the transmission speed of scanned picture data too low, also just can not bring into play the transmission advantage of small computer system interface SCSI bus.

Summary of the invention:

Purpose of the present invention, be exactly at the existing in prior technology deficiency, and provide a kind of technical scheme of image scanning memory, this scheme adopts two-stage control storage structure, the memory of oneself is respectively established in collection and transmission in pictorial data, the image data bus of image and the transmission data/address bus of image are provided with respectively, this just can finish the transmission of scanning of image data in scanning of image, reduced whole sweep time, the transmission speed of image scanning memory is improved.

This programme is realized by following technical measures.This image scanning memory is by the two-stage control storage, bus control unit and small computer system interface SCSI form, first order control storage is by programmable logic array FPGA1 chip U102 in the described two-stage control storage, revising memory chip U204 and acquisition buffer memory chip U201 forms, it mainly acts on is to central processor CPU, contact image sensor CIS and analog-digital converter A/D provide the line synchronizing signal of clock signal and contact image sensor CIS, provide timing control signal to motor, the binary pattern processing of gathering pictorial data and revising and in programmable logic array FPGA1, carrying out, and the pictorial data of output through revising and handling; Second level control storage is made up of programmable logic array FPGA2 chip U103 and transmission buffer memory chip U202, it mainly acts on is to adopt transfer mode to receive the pictorial data of first order control storage output, then, convert pictorial data to direct memory access (DMA) DMA pattern and export to small computer system interface SCSI chip U101, again by small computer system interface SCSI output image data; Bus control unit chip U203 then controls the bus switch of two-stage control storage.

The concrete circuit connection of each chip is as follows:

Programmable logic array FPGA1 in the described first order control storage adopts programmable logic array chip U102, its model is EPM7128ST, 23 of U102 chip, 24,25,27,28,29,30,31,32 pin connect by revising the correction pictorial data DF that memory U204 comes, U102 pin 41,40,35,37,19,42,44,20,21,45,22 meet correction memory U204, the high 8-18 bit address signal AF (8-18) of memory is revised in output, the pin 81 of U102,83,84,93,92,96,97 connect the address of central processing unit CUP, data multiplex bus AD, the pin 53 of U102,50,48,46,47,49,52,54 deliver to acquisition buffer memory U201 with acquisition buffer memory block write data DC, in addition, the clock signal of the 87 pin input crystal oscillator of U102,88,89 pin connect reading of central processor CPU, write signal, 77 pin are exported to contact image sensor CIS clock CIS-CLOK, 78 pin are exported to contact image sensor CIS line synchronizing signal CIS-SIO, pin 98,99,100,1 meets the timing control signal/INA of motor, INA, / INB, INB issues Electric Machine Control, the output of 36 pin is revised memory output and is allowed signal FLASH-OE to give U204,58,60,61,63,64, pin meets SET respectively, MOV-NUM, LOCK, ADD4W, the ADD4R signal removes to control programmable logic array FPGA2, the clock CPU-CLA of 67 pin output central processor CPU, 90 pin receive the address latch signal ALE that central processor CPU is sent here, 17 pin are exported to A/D converter clock AD-CLKO, 56 pin output acquisition buffer district write signal RAM1W give U201, the output of 71 pin has been swept delegation's interrupt signal and has been given central processor CPU, and 75 pin output small computer system interface SCSI chip selection signal/SCSI-CS give small computer system interface SCSI chip U101.

Correction memory U204 in the described first order control storage, its model is M29F010B, 12,11,10,9,8,7,6,5 pin of U204 receive the image scanning signal AF (0-7) of A/D converter output, pin 27,26,23,25,4,28,29,3,2,30 and 1 receives the AF (8-18) of U102 output, pin 13,14,15,17,18,19,20 and 21 is to U102 output DF, and 24 pin connect U102 output FLASH-OE signal.

Acquisition buffer memory U201 in the described first order control storage, its model is 628512,12,11,10,9,8,7,6,5,27,26,23,25,4,28,3,31,2,30 and 1 pin of U201 meets the acquisition buffer regional address AB by programmable logic array FPGA2 chip U103 output, and pin 29 is by the acquisition buffer district write signal RAM1-W of U102 output, and pin 24 is by the acquisition buffer district read signal RAM1-R of U103 output.

Programmable logic array FPGA2 chip U103 in the control storage of the described second level, its model is EPM7128ST, 22 of U103,23,25,36,35,33,32,45,44,37,42,30,46,29,48,28,47,27 pin meet acquisition buffer regional address AB, the pin 54 of U103,55,57,58,61,64,67,69,65,63,56,60,71,68,72,75 meet transmit buffering regional address AC removes transmission buffer memory U202, the pin 49 of U103,50,52 connect switch are set, pin 94,92,85,84,83,81,80,79 meet central processor CPU data address bus AD, pin 70 output transmit buffer write signal RAM2-W give U202, pin 40 output acquisition buffer district read signal RAM1-R give U201, pin 76,77 output direct memory access (DMA) DMA controls are write DMAWR and are replied the DACK signal, pin 78 receives the direct memory access (DMA) dma request signal that small computer system interface SCSI chip U101 comes, pin 97 meets the transferring data signalization MOV-NUM of U102 output, pin 99 connects being provided with of U102 output and transmits working method signal SET, pin 88,89 connect U102 output read address AD D4R and write address ADD4W signal, pin 90 connects the taboo of U102 output and reads locking signal LOCK, and pin 87 meets clock CLOCK.

Transmission buffer memory U202 in the control storage of the described second level, its chip model is 68512A, the pin 12,11,10,9,8,7,6,5,27,26,23,25,4,28,3 and 31 of U202 meets the transmit buffering regional address AC of U103, pin 13,14,15,17 to 21 meets total line traffic control U203 and exports to the direct memory access (DMA) DMA signal of small computer system interface SCSI chip U101, and pin 24 and 29 meets the control answer signal DACK and the transmit buffer write signal RAM2-W of U103 output.

Described bus control unit U203, its chip model is 74LS245 or uses 74HC245, the pin 2 to 9 of U203 connects the DC data of U201 output, and pin 11 to 18 output direct memory access (DMA) DMA data are given scsi interface U101, and pin 19 meets the acquisition buffer district read signal RAM1-R of U103 output.

Described small computer system interface SCSI chip U101, its chip model is AM53CF94,63 to 66 of U101,68 to 71 pin connect the data of central processor CPU, address bus AD, pin 77 to 84 connects the direct memory access (DMA) DMA data of U203 output, pin 60 meets the address latch signal ALE of central processor CPU output, pin 72 output direct memory access (DMA) dma request signal DREQ are to U103, pin 73 meets the direct memory access (DMA) DMA answer signal ADCK of U103 output, pin 55,54 connect the read-write of central processor CPU, pin 61 meets clock CLOCK, pin 56 meets the small computer system interface SCSI chip selection signal SCSI-CS of U102 output, pin 74 connects the direct memory access (DMA) DMA control write signal DMAWR of U103 output, pin 23 to 26,28 to 31 is the output DB of small computer system interface SCSI.

The beneficial effect of this programme can be according to the narration of such scheme as can be known, owing in this scheme, adopted the two-stage control storage, wherein first order control storage is by U102, U204 and U201 form, U102 is a programmable logic array FPGA1 chip, U204 revises memory chip, U201 is the acquisition buffer memory chip, U102 gives central processor CPU with the clock of crystal oscillator input through frequency division, contact image sensor CIS and analog-digital converter A/D provide clock signal, and the line synchronizing signal of contact image sensor CIS, provide timing control signal to motor, and the normal data correction of control collection pictorial data and calculating deposits U204 in, pictorial data among the U204 is defeated by U102 again, the binary pattern that carries out in U102 is handled, pictorial data after treatment is defeated by U201, send control signal also will for second level control storage, these processes are finished by U102 control, do not need the intervention of central processor CPU, the effect of central processor CPU just starts scanning, other is carried out automatically by U102, data line produces interruption after depositing the acquisition buffer district in, and the scanning of notice central processor CPU is finished and can be started next line scanning; Second level control storage is made up of U103 and U202, U103 is a programmable logic array FPGA2 chip, U202 is the transmission buffer memory chip, the logic of writing with transmit buffer read that the acquisition buffer district is arranged in U103, the write address in acquisition buffer district and reading address generator and read/write address switch, the writing address generator of transmit buffer and direct memory access (DMA) dma controller, because there are read-write two cover address generators in the acquisition buffer district, therefore can gather simultaneously and transfer work, reading locking signal LOCK signal controlling by taboo switches, transfer process is read by the acquisition buffer district, the logic of writing of transmit buffer is finished automatically, the reading of transmit buffer finished by the direct memory access (DMA) dma controller, and write small computer system interface SCSI, realize adopting transfer mode to receive the pictorial data of first order control storage output with this, then, convert pictorial data to direct memory access (DMA) DMA pattern and export to small computer system interface SCSI, improved the data transmission bauds of swept memory, exported at a high speed by small computer system interface SCSI again, the scanning of image data of even output; Bus control unit then is the bus switch that is used for controlling the two-stage control storage.This shows that the present invention compared with prior art has outstanding substantive distinguishing features and obvious improvement, its implementation result also is conspicuous.

Description of drawings:

Fig. 1 is the circuit structure block diagram of the embodiment of the invention;

Fig. 2 is the U102 wiring schematic diagram among Fig. 1;

Fig. 3 is the U103 wiring schematic diagram among Fig. 1;

Fig. 4 is the U101 wiring schematic diagram among Fig. 1;

Fig. 5 is the U201 wiring schematic diagram among Fig. 1;

Fig. 6 is the U202 wiring schematic diagram among Fig. 1;

Fig. 7 is the U203 wiring schematic diagram among Fig. 1;

Fig. 8 is the U204 wiring schematic diagram among Fig. 1.

Embodiment:

For clearly demonstrating the technical characterstic of this programme, this programme is illustrated below by an embodiment.

By accompanying drawing 1 as can be seen, this image scanning memory is by the two-stage control storage, bus control unit and small computer system interface SCSI form, first order control storage is by programmable logic array FPGA1 chip U102 in the described two-stage control storage, revising memory chip U204 and acquisition buffer memory chip U201 forms, it mainly acts on is to central processor CPU, contact image sensor CIS and analog-digital converter A/D provide the line synchronizing signal of clock signal and contact image sensor CIS, provide timing control signal to motor, the binary pattern processing of gathering pictorial data and revising and in programmable logic array FPGA1, carrying out, and the pictorial data of output through revising and handling; Second level control storage is made up of programmable logic array FPGA2 chip U103 and transmission buffer memory chip U202, it mainly acts on is to adopt transfer mode to receive the pictorial data of first order control storage output, then, convert pictorial data to direct memory access (DMA) DMA pattern and export to small computer system interface SCSI chip U101, again by small computer system interface SCSI output image data; Bus control unit U203 then controls the bus switch of two-stage control storage.By accompanying drawing 2 as can be seen, programmable logic array FPGA1 in the described first order control storage adopts programmable logic array chip U102, its model is EPM7128ST, 23 of U102 chip, 24,25,27,28,29,30,31,32 pin connect by revising the correction pictorial data DF that memory U204 comes, U102 pin 41,40,35,37,19,42,44,20,21,45,22 meet correction memory U204, the high 8-18 bit address signal AF (8-18) of memory is revised in output, the pin 81 of U102,83,84,93,92,96,97 connect the address of central processing unit CUP, data multiplex bus AD, the pin 53 of U102,50,48,46,47,49,52,54 deliver to acquisition buffer memory U201 with acquisition buffer memory block write data DC, in addition, the clock signal of the 87 pin input crystal oscillator of U102,88,89 pin connect reading of central processor CPU, write signal, 77 pin are exported to contact image sensor CIS clock CIS-CLOK, 78 pin are exported to contact image sensor CIS line synchronizing signal CIS-SIO, pin 98,99,100,1 meets the timing control signal/INA of motor, INA, / INB, INB issues Electric Machine Control, the output of 36 pin is revised memory output and is allowed signal FLASH-OE to give U204,58,60,61,63,64, pin meets SET respectively, MOV-NUM, LOCK, ADD4W, the ADD4R signal removes to control programmable logic array FPGA2, the clock CPU-CLA of 67 pin output CPU, 90 pin receive the address latch signal ALE that central processor CPU is sent here, 17 pin are exported to A/D converter clock AD-CLKO, 56 pin output acquisition buffer district write signal RAM1W give U201, the output of 71 pin has been swept delegation's interrupt signal and has been given central processor CPU, and 75 pin output small computer system interface SCSI chip selection signal/SCSI-CS give small computer system interface SCSI chip U101.By accompanying drawing 8 as can be seen, correction memory U204 in the described first order control storage, its model is M29F010B, 12,11,10,9,8,7,6,5 pin of U204 receive the image scanning signal AF (0-7) of A/D converter output, pin 27,26,23,25,4,28,29,3,2,30 and 1 receives the AF (8-18) of U102 output, pin 13,14,15,17,18,19,20 and 21 is to U102 output DF, and 24 pin connect U102 output FLASH-OE signal.By accompanying drawing 5 as can be seen, acquisition buffer memory U201 in the described first order control storage, its model is 628512,12,11,10,9,8,7,6,5,27,26,23,25,4,28,3,31,2,30 and 1 pin of U201 meets the acquisition buffer regional address AB by programmable logic array FPGA2 chip U103 output, and pin 29 is by the acquisition buffer district write signal RAM1-W of U102 output, and pin 24 is by the acquisition buffer district read signal RAM1-R of U103 output.By accompanying drawing 3 as can be seen, programmable logic array FPGA2 chip U103 in the control storage of the described second level, its model is EPM7128ST, 22 of U103,23,25,36,35,33,32,45,44,37,42,30,46,29,48,28,47,27 pin meet acquisition buffer regional address AB, the pin 54 of U103,55,57,58,61,64,67,69,65,63,56,60,71,68,72,75 meet transmit buffering regional address AC removes transmission buffer memory U202, the pin 49 of U103,50,52 connect switch are set, pin 94,92,85,84,83,81,80,79 meet central processor CPU data address bus AD, pin 70 output transmit buffer write signal RAM2-W give U202, pin 40 output acquisition buffer district read signal RAM1-R give U201, pin 76,77 output direct memory access (DMA) DMA controls are write DMAWR and are replied the DACK signal, pin 78 receives the direct memory access (DMA) dma request signal that scsi interface U101 comes, pin 97 meets the transferring data signalization MOV-NUM of U102 output, pin 99 connects being provided with of U102 output and transmits working method signal SET, pin 88,89 connect U102 output read address AD D4R and write address ADD4W signal, pin 90 connects the taboo of U102 output and reads locking signal LOCK, and pin 87 meets clock CLOCK.Drawings attached 6 as can be seen, transmission buffer memory U202 in the control storage of the described second level, its chip model is 68512A, the pin 12,11,10,9,8,7,6,5,27,26,23,25,4,28,3 and 31 of U202 meets the transmit buffering regional address AC of U103, pin 13,14,15,17 to 21 meets total line traffic control U203 and exports to the direct memory access (DMA) DMA signal of scsi interface U101, and pin 24 and 29 meets the control answer signal DACK and the transmit buffer write signal RAM2-W of U103 output.By accompanying drawing 7 as can be seen, described bus control unit U203, its chip model is 74LS245 or uses 74HC245, the pin 2 to 9 of U203 connects the DC data of U201 output, pin 11 to 18 output direct memory access (DMA) DMA data are given small computer system interface SCSI chip U101, and pin 19 meets the acquisition buffer district read signal RAM1-R of U103 output.By accompanying drawing 4 as can be seen, described small computer system interface SCSI chip U101, its chip model is AM53CF94,63 to 66 of U101,68 to 71 pin connect the data of central processor CPU, address bus AD, pin 77 to 84 connects the direct memory access (DMA) DMA data of U203 output, pin 60 meets the address latch signal ALE of central processor CPU output, pin 72 output direct memory access (DMA) dma request signal DREQ are to U103, pin 73 meets the direct memory access (DMA) DMA answer signal ADCK of U103 output, pin 55,54 connect the read-write of central processor CPU, pin 61 meets clock CLOCK, pin 56 meets the small computer system interface SCSI chip selection signal SCSI-CS of U102 output, pin 74 connects the direct memory access (DMA) DMA control write signal DMAWR of U103 output, pin 23 to 26,28 to 31 is the output DB of small computer system interface SCSI.

Claims (8)

1. image scanning memory, it is characterized in that this image scanning memory is by the two-stage control storage, bus control unit and small computer system interface SCSI form, first order control storage is by programmable logic array FPGA1 chip U102 in the described two-stage control storage, revising memory chip U204 and acquisition buffer memory chip U201 forms, it mainly acts on is to central processor CPU, contact image sensor CIS and analog-digital converter A/D provide the line synchronizing signal of clock signal and contact image sensor CIS, provide timing control signal to motor, the binary pattern processing of gathering pictorial data and revising and in programmable logic array FPGA1, carrying out, and the pictorial data of output through revising and handling; Second level control storage is made up of programmable logic array FPGA2 chip U103 and transmission buffer memory chip U202, it mainly acts on is to adopt transfer mode to receive the pictorial data of first order control storage output, then, convert pictorial data to direct memory access (DMA) DMA pattern and export to small computer system interface SCSI chip U101, again by small computer system interface SCSI output image data; Bus control unit U203 then controls the bus switch of two-stage control storage.

2. image scanning memory according to claim 1, it is characterized in that the programmable logic array FPGA1 in the described first order control storage adopts programmable logic array chip U102, its model is EPM7128ST, 23 of U102 chip, 24,25,27,28,29,30,31,32 pin connect by revising the correction pictorial data DF that memory U204 comes, U102 pin 41,40,35,37,19,42,44,20,21,45,22 meet correction memory U204, the high 8-18 bit address signal AF (8-18) of memory is revised in output, the pin 81 of U102,83,84,93,92,96,97 connect the address of central processing unit CUP, data multiplex bus AD, the pin 53 of U102,50,48,46,47,49,52,54 deliver to acquisition buffer memory U201 with acquisition buffer memory block write data DC, in addition, the clock signal of the 87 pin input crystal oscillator of U102,88,89 pin connect reading of central processor CPU, write signal, 77 pin are exported to contact image sensor CIS clock CIS-CLOK, 78 pin are exported to contact image sensor CIS line synchronizing signal CIS-SIO, pin 98,99,100,1 meets the timing control signal/INA of motor, INA, / INB, INB issues Electric Machine Control, the output of 36 pin is revised memory output and is allowed signal FLASH-OE to give U204,58,60,61,63,64, pin meets SET respectively, MOV-NUM, LOCK, ADD4W, the ADD4R signal removes to control programmable logic array FPGA2, the clock CPU-CLA of 67 pin output central processor CPU, 90 pin receive the address latch signal ALE that central processor CPU is sent here, 17 pin are exported to A/D converter clock AD-CLKO, 56 pin output acquisition buffer district write signal RAM1W give U201, the output of 71 pin has been swept delegation's interrupt signal and has been given central processor CPU, and 75 pin output small computer system interface SCSI chip selection signal/SCSI-CS give small computer system interface SCSI chip U101.

3. image scanning memory according to claim 1, it is characterized in that the correction memory U204 in the described first order control storage, its model is M29F010B, 12,11,10,9,8,7,6,5 pin of U204 receive the image scanning signal AF (0-7) of A/D converter output, pin 27,26,23,25,4,28,29,3,2,30 and 1 receives the AF (8-18) of U1 02 output, pin 13,14,15,17,18,19,20 and 21 is to U102 output DF, and 24 pin connect U102 output FLASH-OE signal.

4. image scanning memory according to claim 1, it is characterized in that the acquisition buffer memory U201 in the described first order control storage, its model is 628512,12,11,10,9,8,7,6,5,27,26,23,25,4,28,3,31,2,30 and 1 pin of U201 meets the acquisition buffer regional address AB by programmable logic array FPGA2 chip U103 output, and pin 29 is by the acquisition buffer district write signal RAM1-W of U102 output, and pin 24 is by the acquisition buffer district read signal RAM1-R of U103 output.

5. image scanning memory according to claim 1, it is characterized in that the programmable logic array FPGA2 chip U103 in the control storage of the described second level, its model is EPM7128ST, 22 of U103,23,25,36,35,33,32,45,44,37,42,30,46,29,48,28,47,27 pin meet acquisition buffer regional address AB, the pin 54 of U103,55,57,58,61,64,67,69,65,63,56,60,71,68,72,75 meet transmit buffering regional address AC removes transmission buffer memory U202, the pin 49 of U103,50,52 connect switch are set, pin 94,92,85,84,83,81,80,79 meet central processor CPU data address bus AD, pin 70 output transmit buffer write signal RAM2-W give U202, pin 40 output acquisition buffer district read signal RAM1-R give U201, pin 76,77 output direct memory access (DMA) DMA controls are write DMAWR and are replied the DACK signal, pin 78 receives the direct memory access (DMA) dma request signal that small computer system interface SCSI chip U101 comes, pin 97 meets the transferring data signalization MOV-NUM of U102 output, pin 99 connects being provided with of U102 output and transmits working method signal SET, pin 88,89 connect U102 output read address AD D4R and write address ADD4W signal, pin 90 connects the taboo of U102 output and reads locking signal LOCK, and pin 87 meets clock CLOCK.

6. image scanning memory according to claim 1, it is characterized in that the transmission buffer memory U202 in the control storage of the described second level, its chip model is 68512A, the pin 12 of U202,11,10,9,8,7,6,5,27,26,23,25,4,28,3 and 31 meet the transmit buffering regional address AC of U103, pin 13,14,15,17 to 21 connect total line traffic control U203 and the direct memory access (DMA) DMA signal of exporting to small computer system interface SCSI chip U101, and pin 24 and 29 meets the control answer signal DACK and the transmit buffer write signal RAM2-W of U103 output.

7. image scanning memory according to claim 1, it is characterized in that described bus control unit U203, its chip model is 74LS245 or uses 74HC245, the pin 2 to 9 of U203 connects the DC data of U201 output, pin 11 to 18 output DMA data are given small computer system interface SCSI chip U101, and pin 19 meets the acquisition buffer district read signal RAM1-R of U103 output.

8. image scanning memory according to claim 1, it is characterized in that described small computer system interface SCSI chip U101, its chip model is AM53CF94,63 to 66 of U101,68 to 71 pin connect the data of central processor CPU, address bus AD, pin 77 to 84 connects the direct memory access (DMA) DMA data of U203 output, pin 60 meets the address latch signal ALE of central processor CPU output, pin 72 output dma request signal DREQ are to U103, pin 73 meets the direct memory access (DMA) DMA answer signal ADCK of U103 output, pin 55,54 connect the read-write of central processor CPU, pin 61 meets clock CLOCK, pin 56 meets the small computer system interface SCSI chip selection signal SCSI-CS of U102 output, pin 74 connects the direct memory access (DMA) DMA control write signal DMAWR of U103 output, pin 23 to 26,28 to 31 is the output DB of scsi interface.

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