CN108880258B - Controller applied to secondary side of power converter and operation method thereof - Google Patents
Controller applied to secondary side of power converter and operation method thereof Download PDFInfo
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- CN108880258B CN108880258B CN201710334006.6A CN201710334006A CN108880258B CN 108880258 B CN108880258 B CN 108880258B CN 201710334006 A CN201710334006 A CN 201710334006A CN 108880258 B CN108880258 B CN 108880258B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
- H02M3/33523—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop
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- Dc-Dc Converters (AREA)
Abstract
The invention discloses a controller applied to a secondary side of a power converter and an operation method thereof. The controller includes a sampling/tracking circuit and a comparator. The sampling/tracking circuit is coupled to the secondary side of the power converter and used for generating a sampling value corresponding to the output voltage of the power converter when a sampling signal is enabled and generating a tracking value corresponding to the output voltage; the comparator is coupled to the sampling/tracking circuit and used for generating an alarm signal to a primary side regulation controller of the power converter according to the sampling value and the tracking value during a tracking signal enabling period. The primary side adjusting controller adjusts the frequency of the grid control signal according to the warning signal, and the sampling signal and the tracking signal are not enabled simultaneously. Therefore, the present invention is suitable for applications requiring a variable output voltage and can prevent ripple noise from causing the comparator to generate the warning signal.
Description
Technical Field
The present invention relates to a controller applied to a secondary side of a power converter and an operating method thereof, and more particularly, to a controller and an operating method thereof capable of enabling a primary side regulation controller of a power converter to quickly respond to a suddenly increased load.
Background
When the load on the secondary side of the power converter is light, the frequency of the gate control signal generated by the voltage regulator controller on the primary side of the power converter is low, so that the period of the gate control signal is long. Therefore, when the load on the secondary side of the power converter suddenly increases, the output voltage on the secondary side of the power converter may suddenly drop because the output power on the secondary side of the power converter can be provided only by the capacitor coupled to the secondary side of the power converter, that is, because the frequency of the gate control signal is low, the response of the voltage regulator controller to the change of the output voltage is slow, and the voltage regulator controller cannot quickly respond to the suddenly increased load, so that the output voltage may suddenly drop. Therefore, how to design a controller that can make the voltage regulator controller quickly respond to the suddenly increased load becomes an important issue.
Disclosure of Invention
An embodiment of the invention discloses a controller applied to a secondary side of a power converter. The controller includes a sampling/tracking circuit and a comparator. The sampling/tracking circuit is coupled to the secondary side of the power converter and used for generating a sampling value corresponding to the output voltage of the power converter when a sampling signal is enabled and generating a tracking value corresponding to the output voltage; the comparator is coupled to the sampling/tracking circuit, and configured to generate an alarm signal to a primary-side regulation (PSR) controller of the power converter according to the sampling value and the tracking value during an enabling period of a tracking signal. The primary side adjusting controller adjusts the frequency of the grid control signal according to the warning signal, and the sampling signal and the tracking signal are not enabled simultaneously.
Another embodiment of the present invention discloses an operation method of a controller applied to a secondary side of a power converter, wherein the controller includes a sampling/tracking circuit and a comparator. The operation method comprises the steps that the sampling/tracking circuit generates a sampling value corresponding to the output voltage of the power converter when a sampling signal is enabled; the sampling/tracking circuit generates a tracking value corresponding to the output voltage; the comparator generates an alarm signal to a primary side regulation controller of the power converter according to the sampling value and the tracking value during a tracking signal enabling period, wherein the primary side regulation controller adjusts the frequency of the grid control signal according to the alarm signal, and the sampling signal and the tracking signal are not enabled simultaneously.
The invention discloses a controller applied to a secondary side of a power converter and an operation method thereof. The controller and the operation method utilize a sampling/tracking circuit to generate a sampling value and a tracking value corresponding to the output voltage of the power converter, and utilize a comparator to generate a warning signal to a primary side regulation controller of the power converter according to the sampling value and the tracking value. Then, the primary side regulation controller may increase the frequency of the gate control signal of the primary side power switch of the power converter according to the warning signal. Therefore, compared with the prior art, the invention has the following advantages: firstly, because the tracking value is corresponding to the real-time output voltage of the power converter, the invention is suitable for the application needing variable output voltage; second, since the present invention determines whether to generate the warning signal to the primary-side regulator controller according to the percentage of drop of the output voltage, the present invention can prevent ripple noise from causing the comparator to generate the warning signal to the primary-side regulator controller when the output voltage is high.
Drawings
Fig. 1 is a schematic diagram of a controller applied to a secondary side of a power converter according to a first embodiment of the present invention.
Fig. 2 is a timing diagram illustrating a gate control signal of a power switch corresponding to a primary side of a power converter, a current of a secondary side of the power converter, a sampling signal, a tracking signal, a change in a load of the secondary side of the power converter, an output voltage, and a warning signal.
Fig. 3A is a schematic diagram of a controller applied to a secondary side of a power converter according to a second embodiment of the present invention.
Fig. 3B is a schematic diagram of a controller applied to a secondary side of a power converter according to another embodiment of the disclosure.
Fig. 4 is a flowchart of an operation method of a controller applied to a secondary side of a power converter according to a third embodiment of the present invention.
Wherein the reference numerals are as follows:
100 power converter
102 load
104 power switch
106 primary side regulating controller
108 optical coupler
200. 200a, 200b controller
202. 300 sampling/tracking circuit
204 comparator
206 drive circuit
2022 voltage dividing unit
2024 regulating unit
2026. 302 current mirror
20222 first resistance
20224 second resistance
20242 operational amplifier
20244N-type MOS transistor
20246 third resistor
20262 first P-type metal oxide semiconductor transistor
20264 second P-type MOS transistor
20266 third pmos transistor
20268 first switch
20270 second switch
20272 fourth resistor
20274 first capacitor
3022 fourth P-type metal oxide semiconductor transistor
3024 fifth P-type MOS transistor
3026 fifth resistor
3028 third switch
3030 second capacitor
Node A
DV partial pressure
GCS Gate control Signal
GND1, GND2 ground terminal
I1 first Current
I2 second Current
I3 third Current
ISEC current
PRI Primary side
SEC Secondary side
SAS sampled signal
TS tracking signal
Time T1-T8
VCC, OPTOD pin
VOUT, VOUT1, VOUT2 output voltage
First voltage of V1
Second voltage of V2
VSAM sample values
VT tracking value
WS Warning Signal
400-406 steps
Detailed Description
Referring to fig. 1, fig. 1 is a schematic diagram of a controller 200 applied to a secondary side SEC of a power converter 100 according to a first embodiment of the present invention. As shown in fig. 1, the controller 200 includes a sampling/tracking circuit 202 and a comparator 204, wherein the sampling/tracking circuit 202 is coupled to the secondary side SEC of the power converter 100, and the comparator 204 is coupled to the sampling/tracking circuit 202.
As shown in fig. 1, the sampling/tracking circuit 202 includes a voltage division unit 2022, a regulation unit 2024, and a current mirror 2026. The voltage dividing unit 2022 comprises a first resistor 20222 and a second resistor 20224, wherein the voltage dividing unit 2022 is coupled to the secondary side SEC of the power converter 100, and is configured to receive the output voltage VOUT of the secondary side SEC of the power converter 100 via a pin VCC, and divide the output voltage VOUT by using the first resistor 20222 and the second resistor 20224 according to formula (1) to generate a divided voltage DV:
wherein R is20222Is the resistance value of the first resistor 20222 and R20224Is the resistance value of the second resistor 20224. In addition, the coupling relationship between the first resistor 20222 and the second resistor 20224 can refer to fig. 1, and is not described herein again.
The adjusting unit 2024 comprises an operational amplifier 20242, an nmos transistor 20244, and a third resistor 20246, wherein the adjusting unit 2024 is coupled to the voltage dividing unit 2022 for generating a first voltage V1 according to the divided voltage DV when the nmos transistor 20244 operates normally, the first voltage V1 is related to the output voltage VOUT, the first voltage V1 is equal to the divided voltage DV, and the first voltage V1 and the third resistor 20246 can determine a first current I1 by the following formula (2):
wherein R is20246Is the resistance value of the third resistor 20246. In addition, the coupling relationship between the operational amplifier 20242, the nmos 20244 and the third resistor 20246 can be found in fig. 1, and will not be described herein again.
In addition, as shown in fig. 1, the current mirror 2026 is coupled to the adjusting unit 2024 and the comparator 204, and includes a first pmos transistor 20262, a second pmos transistor 20264, a third pmos transistor 20266, a first switch 20268, a second switch 20270, a fourth resistor 20272, and a first capacitor 20274, wherein the aspect ratio of the third pmos transistor 20266 is equal to the aspect ratio of the first pmos transistor 20262, the aspect ratio of the second pmos transistor 20264 is N times the aspect ratio of the first pmos transistor 20262, and N is a real number greater than 1. In addition, the coupling relationship among the first pmos transistor 20262, the second pmos transistor 20264, the third pmos transistor 20266, the first switch 20268, the second switch 20270, the fourth resistor 20272 and the first capacitor 20274 can refer to fig. 1 and will not be described herein again. In addition, the aspect ratio of the third pmos transistor 20266 is not limited to be equal to the aspect ratio of the first pmos transistor 20262, that is, in another embodiment of the present invention, the aspect ratio of the third pmos transistor 20266 is not equal to the aspect ratio of the first pmos transistor 20262. As shown in fig. 1, since the width-to-length ratio of the second pmos transistor 20264 is N times the width-to-length ratio of the first pmos transistor 20262, the second current I2 flowing through the second pmos transistor 20264 is N times the first current I1, and the third current I3 flowing through the third pmos transistor 20266 is equal to the first current I1, wherein the second current I2 can be represented by formula (3):
referring to fig. 2, fig. 2 is a timing diagram illustrating a gate control signal GCS of the power switch 104 corresponding to the primary-side PRI of the power converter 100, a current ISEC of the secondary-side SEC of the power converter 100, a sampling signal SAS, a tracking signal TS, a change in the load 102 of the secondary-side SEC of the power converter 100, an output voltage VOUT, and an alarm signal WS, where the sampling signal SAS and the tracking signal TS are generated by a signal generator (not shown in fig. 1) in the controller 200, the sampling signal SAS and the tracking signal TS are not simultaneously enabled, and the sampling signal SAS and the tracking signal TS correspond to the gate control signal GCS. As shown in FIG. 2, at a time T1, the gate control signal GCS is turned offSo the secondary side SEC of the power converter 100 starts to discharge (when the current ISEC has a maximum value and the tracking signal TS is also turned off). At time T2, secondary side SEC of power converter 100 is discharged and sampling signal SAS is enabled. As shown in FIG. 1, at time T2, the second voltage V2 (corresponding to time T2) at a node A in the sampling/tracking circuit 202 can be represented by formula (4), wherein R is20272The resistance value of the fourth resistor 20272 and VOUT1 are the output voltage VOUT corresponding to the sampling signal SAS (as shown in fig. 2, VOUT1 is the maximum value of the output voltage VOUT because the secondary side SEC of the power converter 100 is discharged at time T2):
because the sampling signal SAS is enabled, the second switch 20270 is turned on, causing the second voltage V2 at the node a to start charging the first capacitor 20274 to generate a sampled value VSAM at the positive input terminal of the comparator 204 equal to the second voltage V2 (i.e., at time T2, the first capacitor 20274 will store the sampled value VSAM).
As shown in fig. 1 and 2, at a time T3, since the sampling signal SAS is turned off and the tracking signal TS is enabled, the second switch 20270 is turned off, and the first switch 20268 and the comparator 204 are turned on, wherein the tracking signal TS is enabled to a time T4. Therefore, as shown in fig. 1, between the time T3 and the time T4, since the tracking signal TS is enabled, the first switch 20268 is turned on, so that a tracking value VT corresponding to a time between T3 and the time T4 is generated between the negative input of the comparator 204 and the node a (i.e. the sampling/tracking circuit 202 generates the tracking value VT during the enabled time of the tracking signal TS), wherein the tracking value VT can be represented by the following formula (5):
in addition, the operations of the controller 200 at the time T4, the time T5 and the time T6 may refer to the operations of the controller 200 at the time T1, the time T2 and the time T3, which are not described herein again.
Between time T3 and time T4, the comparator 204 is turned on because the tracking signal TS is enabled. Therefore, between time T3 and time T4 (i.e., during the enabled period of the tracking signal TS), the comparator 204 can continuously compare the tracking value VT (which has real-time information of the output voltage VOUT as shown in equation (5)) with the sampling value VSAM.
Before a time T7, since the load 102 is a light load, the frequency of the gate control signal GCS generated by the primary-side regulation (PSR) controller 106 of the primary-side PRI of the power converter 100 is low (e.g., the frequency of the gate control signal GCS may be lower than 1 KHz). Therefore, if the load 102 suddenly increases at time T7, the response of the primary-side regulator controller 106 to the change in the output voltage VOUT is slow because the frequency of the gate control signal GCS is low, resulting in a sharp drop in the output voltage VOUT. Therefore, at a time T8, the tracking value VT is equal to the sampling value VSAM, wherein the relationship between the output voltage VOUT (i.e., VOUT1) corresponding to the sampling signal SAS and the output voltage VOUT (i.e., VOUT2) corresponding to the time T8 is determined by the following equation (6):
VT＝VSAM
if N is 19, when VOUT2 is less than 0.95 × VOUT1 (i.e., after time T8), the comparator 204 generates the warning signal WS and transmits the warning signal WS to the primary-side regulation controller 106 through a driving circuit 206, a pin opto and an opto-coupler 108 included in the controller 200, wherein the primary-side regulation controller 106 can increase the frequency and the enabling time of the gate control signal GCS according to the warning signal WS to rapidly respond to the suddenly increased load 102. However, in another embodiment of the present invention, since the comparator 204 has a larger driving capability, the warning signal WS generated by the comparator 204 is directly transmitted to the primary-side regulating controller 106 through the pin opto and the optocoupler 108, that is, when the comparator 204 has a larger driving capability, the driving circuit 206 can be omitted.
In addition, the present invention is not limited to the timing of the sampling signal SAS and the tracking signal TS as shown in fig. 2, that is, it falls within the scope of the present invention as long as the sampling signal SAS and the tracking signal TS are not enabled at the same time.
In addition, the ground terminal GND1 of the primary side PRI of the power converter 100 and the ground terminal GND2 of the secondary side SEC of the power converter 100 may have the same level or different levels.
Referring to fig. 3A, fig. 3A is a schematic diagram of a controller 200a applied to a secondary side SEC of a power converter 100 according to a second embodiment of the present invention. As shown in fig. 3A, the controller 200a and the controller 200a differ in that a current mirror 302 included in the sampling/tracking circuit 300 in the controller 200a generates the tracking value VT continuously according to the first voltage V1 (i.e., the sampling/tracking circuit 300 continuously generates the tracking value VT according to the first voltage V1 regardless of whether the tracking signal TS is enabled). As shown in fig. 3A, the current mirror 302 includes a fourth pmos transistor 3022, a fifth pmos transistor 3024, a fourth resistor 20272, a fifth resistor 3026, a third switch 3028, and a second capacitor 3030, wherein the coupling relationship between the fourth pmos transistor 3022, the fifth pmos transistor 3024, the fourth resistor 20272, the fifth resistor 3026, the third switch 3028, and the second capacitor 3030 can be referred to in fig. 3A, and will not be described again. In addition, the width-to-length ratio of the fifth P-type metal oxide semiconductor transistor 3024 is equal to the width-to-length ratio of the fourth P-type metal oxide semiconductor transistor 3022. The aspect ratio of the fifth pmos transistor 3024 is not limited by the aspect ratio of the fourth pmos transistor 3022.
Please refer to fig. 2 and 3A. As shown in fig. 2, at time T2, secondary side SEC of power converter 100 is discharged and sampling signal SAS is enabled. As shown in fig. 3A, at time T2, a second voltage V2 (corresponding to time T2) at a node a in the current mirror 302 can be represented by equation (7), where VOUT1 is the output voltage VOUT corresponding to the sampling signal SAS (as shown in fig. 2, VOUT1 is the maximum value of the output voltage VOUT because the secondary side SEC of the power converter 100 is discharged at time T2):
because the sampling signal SAS is enabled, the third switch 3028 is turned on, causing the second voltage V2 at node a to begin charging the second capacitor 3030 to generate the sampled value VSAM at the positive input of the comparator 204 equal to the second voltage V2 (i.e., at time T2, the second capacitor 3030 will store the sampled value VSAM). In addition, the tracking value VT can be determined by the formula (8), wherein R3026Resistance value of the fifth resistor 3026:
when R is represented by the formula (8)20272Is R3026When the ratio is N times, the formula (8) can be rewritten as the formula (9):
in addition, the sampled value VSAM can be determined by equation (10):
therefore, as shown in fig. 2, if the load 102 suddenly increases at time T7, the response of the primary-side regulator controller 106 to the change in the output voltage VOUT is slow because the frequency of the gate control signal GCS is low, resulting in a sudden drop in the output voltage VOUT. Therefore, at time T8, the tracking value VT is equal to the sampling value VSAM, wherein the relationship between the output voltage VOUT (i.e., VOUT1) corresponding to the sampled signal SAS and the output voltage VOUT (i.e., VOUT2) corresponding to time T8 is determined by equation (6). Therefore, after the time T8, the comparator 204 will generate the warning signal WS to the primary-side adjustment controller 106, wherein the primary-side adjustment controller 106 can increase the frequency and the enabling time of the gate control signal GCS according to the warning signal WS to quickly respond to the suddenly increased load 102. In addition, the remaining operation principle of the controller 200a is the same as that of the controller 200, and is not described herein again.
In addition, in another embodiment of the present invention (as shown in fig. 3B), the controller 200B applied to the secondary side SEC of the power converter 100 and the controller 200a applied to the secondary side SEC of the power converter 100 are different in that the controller 200B does not include the fifth pmos transistor 3024 and the third resistor 20246, that is, the controller 200B and the controller 200a are different in that the controller 200B does not have a current mirror function. Therefore, as shown in fig. 2 and 3B, at time T2, the second voltage V2 (corresponding to time T2) at node a in the current mirror 302 can be represented by equation (11), where VOUT1 is the output voltage VOUT corresponding to the sampling signal SAS (as shown in fig. 2, VOUT1 is the maximum value of the output voltage VOUT because the secondary side SEC of the power converter 100 is discharged at time T2):
in addition, the tracking value VT can be determined by equation (12):
in addition, the operation principle of the controller 200b can refer to the operation principle of the controller 200a and fig. 2, and the detailed description is omitted here.
Referring to fig. 1, 2 and 4, fig. 4 is a flowchart illustrating an operation method of a controller applied to a secondary side of a power converter according to a third embodiment of the present invention. The operation method of fig. 4 is described by using fig. 1 and 2, and the detailed steps are as follows:
step 400: starting;
step 402: the sampling/tracking circuit 202 generates a sampling value VSAM corresponding to the output voltage VOUT of the power converter 100 when the sampling signal SAS is enabled;
step 404: the sampling/tracking circuit 202 generates a tracking value VT corresponding to the output voltage VOUT;
step 406: the comparator 204 generates the warning signal WS to the primary-side regulator controller 106 of the power converter 100 according to the sampling value VSAM and the tracking value VT during the enabled period of the tracking signal TS, and then returns to step 402.
In step 402, the voltage dividing unit 2022 within the sampling/tracking circuit 202 may divide the output voltage VOUT by using the first resistor 20222 and the second resistor 20224 to generate a divided voltage DV; the regulator unit 2024 in the sample/track circuit 202 generates a first voltage V1 according to the divided voltage DV when the nmos transistor 20244 operates normally, wherein the first voltage V1 is related to the output voltage VOUT, the first voltage V1 is equal to the divided voltage DV, and the first voltage V1 and the third resistor 20246 determine the first current I1.
As shown in fig. 2, at time T1, the gate control signal GCS is turned off, so the secondary side SEC of the power converter 100 starts discharging (when the current ISEC has a maximum value and the tracking signal TS is also turned off). At time T2, secondary side SEC of power converter 100 is discharged and sampled signal SAS is enabled. As shown in fig. 1, at time T2, since the sampling signal SAS is enabled, the second switch 20270 is turned on, causing the second voltage V2 (determined by the fourth resistor 20272 and the second current I2) at the node a to start charging the first capacitor 20274 to generate the sampled value VSAM at the positive input terminal of the comparator 204 equal to the second voltage V2 (i.e., at time T2, the first capacitor 20274 stores the sampled value VSAM).
In step 404, as shown in fig. 1 and 2, at time T3, since the sampling signal SAS is turned off and the tracking signal TS is turned on, the second switch 20270 is turned off, and the first switch 20268 and the comparator 204 are turned on, wherein the tracking signal TS is enabled to time T4, and the sampling signal SAS and the tracking signal TS are not enabled at the same time. Therefore, as shown in fig. 1, between time T3 and time T4, the first switch 20268 is turned on because the tracking signal TS is enabled, resulting in the generation of a tracking value VT between the corresponding time T3 and time T4 at the negative input of the comparator 204 and node a. In addition, as shown in fig. 3A and 3B, in another embodiment of the present invention, the current mirror 302 included in the sampling/tracking circuit 300 of the controller 200a continuously generates the tracking value VT according to the first voltage V1, that is, the sampling/tracking circuit 300 of the controller 200a continuously generates the tracking value VT according to the first voltage V1 regardless of whether the tracking signal TS is enabled.
In step 406, between time T3 and time T4, the comparator 204 is turned on because the tracking signal TS is enabled. Therefore, between time T3 and time T4 (i.e., during the enabled period of the tracking signal TS), the comparator 204 may compare the tracking value VT and the sampling value VSAM in real time. Before time T7, the frequency of the gate control signal GCS generated by the primary-side regulation controller 106 is low (e.g., the frequency of the gate control signal GCS may be lower than 1KHz) because the load 102 is a light load. Therefore, if the load 102 suddenly increases at time T7, the response to the change in the output voltage VOUT is slow because the frequency of the gate control signal GCS is low, resulting in a sharp drop in the output voltage VOUT. Therefore, at time T8, the tracking value VT is equal to the sampling value VSAM. After the time T8, since the tracking value VT is smaller than the sampling value VSAM, the comparator 204 will generate the warning signal WS and transmit the warning signal WS to the primary-side adjustment controller 106, wherein the primary-side adjustment controller 106 can increase the frequency and the enabling time of the gate control signal GCS according to the warning signal WS to quickly respond to the suddenly increased load 102.
In summary, the controller applied to the secondary side of the power converter and the operating method thereof disclosed by the present invention utilize the sampling/tracking circuit to generate a sampling value and a tracking value corresponding to the output voltage of the power converter, and utilize the comparator to generate the warning signal to the primary side regulation controller according to the sampling value and the tracking value. Then, the primary side adjustment controller may increase the frequency of the gate control signal according to the warning signal. Therefore, compared with the prior art, the invention has the following advantages: firstly, because the tracking value is corresponding to the real-time output voltage of the power converter, the invention is suitable for the application needing variable output voltage; second, since the present invention determines whether to generate the warning signal to the primary-side regulator controller according to the percentage of drop of the output voltage, the present invention can prevent ripple noise from causing the comparator to generate the warning signal to the primary-side regulator controller when the output voltage is high.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (13)
1. A controller for use on a secondary side of a power converter, comprising:
a sampling/tracking circuit, coupled to a secondary side of the power converter, for generating a sampling value corresponding to an output voltage of the power converter when a sampling signal is enabled, and for generating a tracking value corresponding to the output voltage; and
a comparator coupled to the sampling/tracking circuit for generating an alarm signal to a primary side regulation controller of the power converter according to the sampling value and the tracking value during an enabled period of a tracking signal;
the primary side adjusting controller adjusts the frequency of a grid control signal according to the warning signal, the sampling signal and the tracking signal are not enabled simultaneously, and the tracking signal is turned off after the grid control signal is turned off.
2. The controller of claim 1, wherein: when the tracking value is smaller than the sampling value, the comparator generates the warning signal to the primary side adjusting controller.
3. The controller of claim 1, wherein: the primary side adjusting controller increases the frequency of the gate control signal according to the warning signal.
4. The controller of claim 1, wherein: the sample/track circuit generates the tracking value during an enable period of the tracking signal.
5. The controller of claim 1, wherein: the sampling signal and the tracking signal correspond to a gate control signal of a power switch on a primary side of the power converter.
6. The controller of claim 1 wherein said sample/track circuit comprises:
a voltage division unit coupled to a secondary side of the power converter for generating a divided voltage according to the output voltage;
a regulating unit, coupled to the voltage dividing unit, for generating a first voltage according to the divided voltage, wherein the first voltage is related to the output voltage; and
a current mirror, coupled to the adjusting unit and the comparator, for generating the sampling value according to the first voltage when the sampling signal is enabled, and generating the tracking value according to the first voltage during the enabled period of the tracking signal.
7. The controller of claim 1 wherein said sample/track circuit comprises:
a voltage division unit coupled to a secondary side of the power converter for generating a divided voltage according to the output voltage;
a regulating unit, coupled to the voltage dividing unit, for generating a first voltage according to the divided voltage, wherein the first voltage is related to the output voltage; and
a current mirror, coupled to the adjusting unit and the comparator, for generating the sampling value according to the first voltage when the sampling signal is enabled, and for generating the tracking value according to the first voltage.
8. The controller of claim 1, further comprising:
and the driving circuit is coupled between the comparator and the primary side regulation controller of the power converter and used for transmitting the warning signal to the primary side regulation controller of the power converter.
9. A method of operating a controller applied to a secondary side of a power converter, wherein the controller includes a sampling/tracking circuit and a comparator, the method comprising:
the sampling/tracking circuit generates a sampling value corresponding to the output voltage of the power converter when a sampling signal is enabled;
the sampling/tracking circuit generates a tracking value corresponding to the output voltage; and
the comparator generates an alarm signal to a primary side regulation controller of the power converter according to the sampling value and the tracking value during the starting period of a tracking signal;
the primary side adjusting controller adjusts the frequency of a grid control signal according to the warning signal, the sampling signal and the tracking signal are not enabled simultaneously, and the tracking signal is turned off after the grid control signal is turned off.
10. The method of operation of claim 9, wherein: when the tracking value is smaller than the sampling value, the comparator generates the warning signal to the primary side adjusting controller.
11. The method of operation of claim 9, wherein: the primary side adjusting controller increases the frequency of the gate control signal according to the warning signal.
12. The method of operation of claim 9, wherein: the sample/track circuit generates the tracking value during an enable period of the tracking signal.
13. The method of operation of claim 9, wherein: the sampling signal and the tracking signal correspond to a gate control signal of a power switch on a primary side of the power converter.
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| CN201710334006.6A CN108880258B (en) | 2017-05-12 | 2017-05-12 | Controller applied to secondary side of power converter and operation method thereof |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1407701A (en) * | 2001-08-17 | 2003-04-02 | Tdk株式会社 | Switch power supply device |
| CN103532350A (en) * | 2012-08-06 | 2014-01-22 | 崇贸科技股份有限公司 | Control circuit with fast dynamic response for power converters |
| CN103683907A (en) * | 2012-09-12 | 2014-03-26 | 德克萨斯仪器股份有限公司 | Fixed frequency DC to DC converter control circuit with improved load transient response |
| CN104201897A (en) * | 2014-08-31 | 2014-12-10 | 广州金升阳科技有限公司 | Dynamic process detection method and fast response circuit of switching power supply |
| CN105656312A (en) * | 2014-11-27 | 2016-06-08 | 富士电机株式会社 | Switching power supply device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2482738B (en) * | 2010-08-13 | 2015-05-13 | Nujira Ltd | Switch mode power supply for envelope tracking |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1407701A (en) * | 2001-08-17 | 2003-04-02 | Tdk株式会社 | Switch power supply device |
| CN103532350A (en) * | 2012-08-06 | 2014-01-22 | 崇贸科技股份有限公司 | Control circuit with fast dynamic response for power converters |
| CN103683907A (en) * | 2012-09-12 | 2014-03-26 | 德克萨斯仪器股份有限公司 | Fixed frequency DC to DC converter control circuit with improved load transient response |
| CN104201897A (en) * | 2014-08-31 | 2014-12-10 | 广州金升阳科技有限公司 | Dynamic process detection method and fast response circuit of switching power supply |
| CN105656312A (en) * | 2014-11-27 | 2016-06-08 | 富士电机株式会社 | Switching power supply device |
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| CN108880258A (en) | 2018-11-23 |
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