CN108878366B - Memory and forming method thereof, and semiconductor device - Google Patents

Memory and forming method thereof, and semiconductor device Download PDF

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Publication number
CN108878366B
CN108878366B CN201710340261.1A CN201710340261A CN108878366B CN 108878366 B CN108878366 B CN 108878366B CN 201710340261 A CN201710340261 A CN 201710340261A CN 108878366 B CN108878366 B CN 108878366B
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bit line
contact
isolation
layer
substrate
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CN108878366A (en
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不公告发明人
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10805Dynamic random access memory structures with one-transistor one-capacitor memory cells
    • H01L27/10808Dynamic random access memory structures with one-transistor one-capacitor memory cells the storage electrode stacked over transistor
    • H01L27/10814Dynamic random access memory structures with one-transistor one-capacitor memory cells the storage electrode stacked over transistor with capacitor higher than bit line level
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/1085Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto
    • H01L27/10852Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor extending over the access transistor
    • H01L27/10855Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor extending over the access transistor with at least one step of making a connection between transistor and capacitor, e.g. plug
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/10882Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making a data line
    • H01L27/10885Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making a data line with at least one step of making a bit line
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/10882Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making a data line
    • H01L27/10888Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making a data line with at least one step of making a bit line contact

Abstract

The invention provides a memory and a forming method thereof, and a semiconductor device.A first isolation side wall is formed on the side wall of the memory by using the formed bit line and bit line contact; and the first isolation side walls on the two most adjacent bit line contacts in the two adjacent bit lines are connected with each other to form a bottleneck seal, and an opening formed by the isolation side walls and the bottleneck seal can define a formation area of the storage node contact in a self-aligning manner, so that only a contact material needs to be filled in the opening when the storage node contact is formed, and a photoetching process does not need to be utilized. Therefore, the execution times of the photoetching process can be reduced, the process flow is effectively simplified, the limitation of a photoetching process window can be avoided, and the preparation difficulty of the memory can be reduced.

Description

Memory and forming method thereof, and semiconductor device
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a memory device and a method for forming the same, and a semiconductor device.
Background
The memory typically includes a storage capacitor for storing charge representing stored information, and a storage transistor connected to the storage element. The memory transistor has formed therein a source region for constituting a bit line contact region to be connected to a bit line, a drain region for constituting a storage node contact region to be connected to a storage capacitor, and a gate electrode for controlling a current flow between the source region and the drain region.
A bit line contact is formed on the bit line contact region and connected to the bit line through the bit line contact, and a storage node contact is formed on the storage node contact region and connected to the storage capacitor through the storage node contact. In the actual manufacturing process of the memory, the method for forming the bit line contact and the storage node contact generally includes: firstly, forming a contact hole by utilizing a photoetching process and an etching process; then, conductive material is filled in the contact holes to form bit line contacts and storage node contacts, respectively.
For example, patent application publication No. CN101055871A discloses a memory, in which a method for forming a bit line contact includes: firstly, forming an insulating layer on a substrate; then, performing a photolithography process and an etching process on the insulating layer to form a contact hole, a center position of which coincides with a center position of a first cell contact (a region corresponding to a bit line contact) to expose the first cell contact; then, a conductive material is filled in the contact hole to constitute the bit line contact. And, in the patent application, the method of forming the storage node contact includes: firstly, forming an insulating layer on a substrate; then, performing a photolithography process and an etching process on the insulating layer to form a contact hole, a center position of which is not overlapped with a center position of a second cell contact (a region corresponding to a storage node contact) to expose the second cell contact; then, a conductive material is filled in the contact hole to constitute the storage node contact portion.
Therefore, the bit line contact and the storage node contact are formed by using multiple photolithography processes. In the above patent application, even though the bit line contact and the storage node contact are formed by using the same photolithography process and etching process, since the contact hole corresponding to the bit line contact and the contact hole corresponding to the storage node contact are closer to each other and the contact holes are prevented from being bordered by each other, it is necessary to control the size of the contact hole to be formed to a small range on the one hand and to strictly control the displacement deviation in the photolithography process on the other hand, so as to ensure that the first cell contact portion and the second cell contact portion can be exposed through the contact holes in consideration of the arrangement position of the subsequent bit line.
Therefore, in the existing forming method of bit line contact and storage node contact, the preparation process is complicated, the photoetching process window is small, and the preparation difficulty of the memory is increased.
Disclosure of Invention
The invention aims to provide a memory and a forming method thereof, so as to simplify the forming process of the memory.
Therefore, the invention provides a forming method of a memory, which comprises the following steps:
providing a substrate, wherein a plurality of active regions extending obliquely relative to a first direction are defined on the substrate, bit line contact regions and storage node contact regions positioned at two sides of the bit line contact regions are formed on the active regions, the active regions are arranged in an array manner, and the bit line contact regions are arranged in a staggered manner;
forming a bit line contact on the bit line contact region, and forming a plurality of bit lines on the substrate, wherein the bit lines extend along a first direction, the bit line contacts arranged on the same line are connected to the same bit line, the height of the bit line and the bit line contact is larger than that of the substrate, so that the bit line and the bit line contact form a plurality of first openings on the surface of the substrate, and the side walls of the bit line and the bit line contact form the side walls of the first openings;
forming first isolation side walls on the side walls of the first openings, wherein the first isolation side walls on the two bit lines which are adjacent to each other and are in contact with the two bit lines which are most adjacent to each other are connected with each other to form a bottleneck seal, the bottleneck seal and the first isolation side walls define a second opening, and the second opening is exposed out of the storage node contact area; and the number of the first and second groups,
a fill contact material is in the second opening to form a storage node contact.
Optionally, the step of forming the first isolation sidewall includes:
depositing a layer of isolation material on the substrate, the layer of isolation material covering the bit lines and the tops of the bit line contacts and covering the sidewalls and the bottom of the first openings; and the number of the first and second groups,
and performing a back etching process to remove the isolation material layer positioned at the top of the bit line and the bit line contact and remove the isolation material layer at the bottom of the first opening so as to form the first isolation side wall on the side wall of the first opening.
Optionally, in two adjacent bit lines, a distance between two nearest adjacent bit line contacts is less than or equal to 2 times a thickness of the isolation material layer, and the thickness of the isolation material layer is a dimension of the isolation material layer in a direction parallel to the substrate surface.
Optionally, in two adjacent bit lines, a distance between two nearest adjacent bit line contacts is greater than 2 times the thickness of the first isolation sidewall, and the thickness of the isolation material layer is a dimension of the isolation material layer in a direction parallel to the substrate surface.
Optionally, the step of depositing the isolation material layer is performed at least twice, so that the isolation material layer is filled between two bit line contacts which are most adjacent in two adjacent bit lines.
Optionally, before forming the bit line, the method further includes:
forming a word line on the substrate; and the number of the first and second groups,
covering an insulating layer on the substrate on which the word lines are formed.
Optionally, the forming of the bit line contact and the bit line includes:
forming a first mask layer on the insulating layer, wherein a plurality of grooves corresponding to the bit line patterns and the bit line contact patterns are formed in the first mask layer, each groove comprises a first groove and a second groove, the first grooves and the second grooves are communicated with each other along a first direction, the first grooves expose the insulating layer on the bit line contact regions, and the second grooves expose the insulating layer between the adjacent bit line contact regions;
forming a second mask layer on the first mask layer to cover the second groove and expose the first groove;
etching the exposed insulating layer by taking the second mask layer as a mask to expose the bit line contact region;
removing the second mask layer and filling a conductive material in the groove, wherein the conductive material in the groove forms a conductive layer of the bit line, and the conductive material in the first groove forms a conductive layer contacted with the bit line;
removing the first mask layer, exposing the bit line contact and the side wall of the bit line to form a first opening, and exposing the insulating layer on the storage node contact region through the first opening; and the number of the first and second groups,
and removing the insulating layer on the storage node contact region to expose the storage node contact region.
Optionally, the first grooves have a rectangular cross section parallel to the substrate surface, and the rectangular vertex angles of two first grooves which are most adjacent in two adjacent grooves are opposite.
Optionally, after forming the first mask layer and before forming the second mask layer, the method further includes:
and forming second isolation side walls on the side walls of the first groove and the second groove.
It is still another object of the present invention to provide a memory, comprising:
the array type memory device comprises a substrate, a plurality of storage node contact areas and a plurality of active areas, wherein the active areas extend obliquely relative to a first direction, bit line contact areas and storage node contact areas positioned on two sides of the bit line contact areas are formed in the active areas, the active areas are arranged in an array mode, and the bit line contact areas are arranged in a staggered mode;
a bit line contact formed on and in contact with the bit line contact region;
a plurality of bit lines extending in a first direction, and the bit line contacts arranged on the same line are connected to the same bit line;
the first isolation side walls are formed on the contact side walls of the bit lines and the bit lines, and the first isolation side walls on the two most adjacent bit line contacts in the two adjacent bit lines are connected with each other to form a bottleneck seal;
and the storage node contacts are formed in an opening jointly limited by the first isolation side wall and the bottleneck seal, and the storage node contacts which are arranged next to each other are isolated through the bottleneck seal.
Optionally, the distance between two nearest adjacent bit line contacts in two adjacent bit lines is less than or equal to 2 times the thickness of the first isolation side wall, and the thickness of the first isolation side wall is the size of the first isolation side wall in the direction parallel to the substrate surface.
Optionally, the cross section of the bit line contact parallel to the substrate surface is rectangular, and the top corners of the rectangles of the two bit line contacts which are nearest to each other in the two adjacent bit lines are opposite.
Optionally, the memory further includes: and the word line is formed on the substrate and extends along a second direction, and the second direction is perpendicular to the first direction.
Optionally, the bit line contact and the bit line each include:
the conductive layer positioned in the bit line contact is in contact with the bit line contact region and is connected with the conductive layer in the bit line;
and the second isolation side wall is positioned on the side wall of the conducting layer.
In the forming method of the memory provided by the invention, after bit lines and bit line contacts are formed, first isolation side walls are formed on the side walls of the bit lines and the bit line contacts, and the first isolation side walls on the adjacent bit line contacts in two adjacent bit lines are mutually connected to form a bottleneck seal, wherein the bottleneck seal can isolate the storage node contact regions which are arranged adjacently; meanwhile, the storage node contact area can be exposed in a self-aligned mode by utilizing the first isolation side wall and the bottleneck seal, so that when the storage node contact is formed, only a contact material needs to be filled in the opening, and a photoetching process does not need to be utilized. Therefore, on one hand, the execution times of the photoetching process can be reduced, the process flow is simplified, the preparation cost is saved, the limitation of a photoetching process window can be avoided, and the preparation difficulty of the memory can be reduced; on the other hand, the forming area of the storage node contact can be defined in a self-alignment mode, and the process window is further expanded.
Drawings
FIG. 1 is a flow chart illustrating a method for forming a memory according to a first embodiment of the invention;
fig. 2a is a top view of a memory in the step S100 according to the method for forming the memory in the first embodiment of the invention;
FIG. 2b is a cross-sectional view of the memory shown in FIG. 2a along the AA ', BB ' and CC ' directions when step S100 is performed according to the method for forming the memory in the first embodiment of the present invention;
fig. 3 is a flowchart illustrating a method for forming a memory according to a first embodiment of the invention when executing step S200;
FIGS. 4a to 9a are top views of the memory in the step S200 according to the method for forming the memory in the first embodiment of the present invention;
FIGS. 4 b-9 b are cross-sectional views of the memory along the directions AA ', BB ' and CC ' during the step S200 corresponding to the method for forming the memory in the first embodiment of the present invention shown in FIGS. 4 a-9 a;
fig. 10a is a top view of the memory in the step S300 according to the method for forming the memory in the first embodiment of the invention;
FIG. 10b is a cross-sectional view of the memory along the directions AA ', BB ' and CC ' during the step S300 corresponding to the method for forming the memory in the first embodiment of the invention shown in FIG. 10 a;
fig. 11a is a top view of a memory in the step S400 according to the method for forming the memory in the first embodiment of the invention;
FIG. 11b is a cross-sectional view of the memory along the directions AA ', BB ' and CC ' during the step S400 corresponding to the method for forming the memory in the first embodiment of the invention shown in FIG. 11 a;
FIG. 12a is a top view of a memory according to a second embodiment of the present invention;
FIG. 12b is a cross-sectional view of the memory shown in FIG. 12a along AA ', BB ' and CC ' directions in the second embodiment of the present invention;
FIG. 13 is a diagram illustrating an arrangement of active regions of a memory according to a second embodiment of the present invention;
fig. 14 is a schematic structural view of a semiconductor device in a third embodiment of the present invention;
fig. 15 is a schematic view showing the arrangement of the first contact regions and the second contact regions in the substrate of the semiconductor device in the third embodiment of the present invention shown in fig. 14;
wherein the reference numbers are as follows:
10-a substrate;
100-an active region;
110-bit line contact regions;
120-storage node contact area;
200-an isolation structure;
300-word line;
400-an insulating layer;
410-a first dielectric layer;
420-a second dielectric layer;
500-bit line;
510-bit line contact;
500 a-conductive layer
500 b-a second isolation sidewall;
600-a first mask layer;
610-a first groove;
620-a second recess;
700-second mask layer;
800-a first isolation sidewall;
800 a-bottleneck closure;
900-storage node contact;
1-a substrate;
1 a-a first opening;
1 b-a second opening;
11-a first contact zone;
12-a second contact zone;
2-first conductor contact;
3-a conductor line;
3 a-the extension direction of the conductor line is shown schematically;
4-isolating the side wall;
41-bottleneck closure;
5-second conductor contact.
Detailed Description
At present, when a memory is prepared, a bit line contact and a storage node contact are formed by filling a conductive material in a contact hole, and in the process, not only a plurality of photoetching processes need to be utilized, but also a process window is smaller in the photoetching process, so that the preparation difficulty of the memory is increased.
To this end, the present invention provides a method for forming a memory to simplify a process for manufacturing the memory, and with reference to a flow diagram of a method for forming a memory in a first embodiment of the present invention shown in fig. 1, the method for forming a memory includes:
step S100, providing a substrate, defining a plurality of active regions extending obliquely relative to a first direction on the substrate, forming bit line contact regions and storage node contact regions positioned at two sides of the bit line contact regions on the active regions, wherein the plurality of active regions are arranged in an array manner and the plurality of bit line contact regions are arranged in a staggered manner;
step S200, forming a bit line contact on the bit line contact area, and forming a plurality of bit lines on the substrate, wherein the bit lines extend along the first direction, the bit line contacts arranged on the same straight line are connected to the same bit line, the height of the bit line and the height of the bit line contact are greater than the height of the substrate, so that the bit line and the bit line contact jointly define a plurality of first openings on the surface of the substrate, and the combination of the sidewalls of the bit line and the bit line contact forms the sidewalls of the first openings;
step S300, forming first isolation sidewalls on sidewalls of the first openings, wherein the first isolation sidewalls of adjacent bit line contacts are connected between two adjacent bit lines to form a bottleneck seal, the bottleneck seal and the first isolation sidewalls of the adjacent bit lines define a second opening together, and the second opening is defined in the first opening and exposes the storage node contact region; and the number of the first and second groups,
step S400, filling contact material in the second opening to form a storage node contact.
According to the forming method of the memory, after the bit line contact and the bit line are formed, the storage node contact is not formed by utilizing a photoetching process, but a first isolation side wall is formed on the side wall of the bit line contact and the side wall of the bit line, and a bottleneck seal is formed between two adjacent bit line contacts in two adjacent bit lines while the first isolation side wall is formed, so that a forming area of the storage node contact can be defined in a self-aligning mode through the first isolation side wall and the bottleneck seal. Therefore, the number of times of photoetching process can be reduced, the problem that a process window is small in the photoetching process is avoided, meanwhile, the storage node contact area can be exposed in a self-aligned mode, and the preparation difficulty of the memory is further simplified.
The memory and the forming method thereof according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
Fig. 2a is a top view of the memory in the first embodiment of the present invention when step S100 is executed, and fig. 2b is a cross-sectional view of the memory in the first embodiment of the present invention shown in fig. 2a along the AA ', BB ' and CC ' directions when step S100 is executed.
In step S100, specifically referring to fig. 2a and 2b, a substrate 10 is provided, a plurality of active regions 100 extending obliquely along a first direction are defined on the substrate 10, a bit line contact region 110 and storage node contact regions 120 located at two sides of the bit line contact region 110 are formed on the active regions 100, where the first direction is an X direction shown in fig. 2a, and a direction extending obliquely along the first direction is a Z direction shown in fig. 2 a. Further, an isolation structure 200 is formed between adjacent active regions 100, and the active regions 100 are isolated from each other by the isolation structure 200.
Specifically, a pair of memory cells (not shown) is further formed in the active region 100, that is, two memory cells are formed in the active region 100, the bit line contact region 110 is formed between the two memory cells, and the two storage node contact regions 120 are formed on two sides of the two memory cells, which are away from each other. Furthermore, the memory cells are, for example, memory transistors, and a common source region is formed between two memory transistors in the same active region, and the common source region constitutes the bit line contact region through which information is read into the bit line; the drain region of the storage transistor forms the storage node contact region which can be used for connecting a storage element; and the memory transistor further comprises a gate electrode located between the common source and drain regions, a word line contact being formed on the gate electrode for connection to a word line, whereby the memory transistor is addressable via the word line. Therefore, as shown in fig. 2a, a plurality of word lines 300 are further formed on the substrate 10, and the word lines 300 extend along a second direction (Y direction shown in fig. 2 a), wherein the first direction and the second direction are perpendicular to each other. Wherein a word line contact is formed on a region where the word line 300 intersects the active region. Preferably, the word line 300 is a buried word line, so that the insulating layer above the word line 300 can have a larger thickness, and the isolation between the word line 300 and other devices can be improved.
As shown in fig. 2a, the active regions 100 are arranged in an array, and the bit line contact regions 110 are arranged in a staggered manner in the second direction. That is, the bit line contact regions 110 are staggered from each other such that the bit line contact regions 110 are adjacent to the storage node contact regions 120 in the second direction (Y direction as shown in fig. 2 a), it being understood that the bit line contact regions 110 and the storage node contact regions 120 adjacent in the second direction are respectively located in different active regions 100.
Referring to fig. 2b, after forming the bit line contact region 110, the storage node contact region 120, and the word line 300, further includes: an insulating layer 400 is covered on the substrate 10. The memory cells and the word lines 300 can be isolated from other devices to be formed later by the insulating layer 400, i.e., the insulating layer 400 covers the word lines 300 and the substrate 10 of the active region 100. The insulating layer 400 is, for example, a silicon oxide layer, a silicon nitride layer, or a combination thereof, and accordingly, the insulating layer 400 may have a single-layer structure or a multi-layer structure.
With continued reference to fig. 2b, the insulating layer 400 over the bit line contact region 110 is a multi-layer structure, and the insulating layer 400 over the non-bit line contact regions (other than the bit line contact region 110) is a single-layer structure. In this embodiment, the insulating layer over the bit line contact region 110 includes a first dielectric layer 410 and a second dielectric layer 420, while the insulating layer over the non-bit line contact region includes only the first dielectric layer 410. That is, by increasing the thickness of the insulating layer 400 on the bit line contact region 110, a formation region may be provided for a subsequent bit line contact, on the one hand, and isolation performance for the bit line contact may be improved, on the other hand. The first dielectric layer 410 may be a silicon nitride layer, and the second dielectric layer 420 may be a silicon oxide layer. The first dielectric layer 410 and the second dielectric layer 420 may be formed by a deposition process, and the specific forming method may refer to the following steps:
first, a first dielectric layer 410 is deposited on the substrate 10, and the first dielectric layer 410 covers the substrate 10, i.e., covers the memory cells formed on the substrate 10, the word lines 300, and the like. As described above, the word line 300 is preferably a buried word line, and the word line 300 may be formed in a word line trench, and thus, the first dielectric layer 410 further fills the word line trench.
Next, a second dielectric layer 420 is deposited on the first dielectric layer 410, and a photolithography and etching process is performed on the second dielectric layer 420, so that the etched second dielectric layer 420 covers the bit line contact region 110.
Fig. 4a to 9a are top views of the memory during the step S200, and fig. 4b to 9b are cross-sectional views of the memory along the directions AA ', BB ' and CC ' during the step S200, corresponding to the method for forming the memory in the first embodiment of the invention shown in fig. 4a to 9 a.
In step S200, referring to fig. 4a to 9a and fig. 4b to 9b, a bit line contact 510 is formed on the bit line contact region 110; and forming a plurality of bit lines 500 on the substrate 10, the bit lines 500 extending in a first direction, bit line contacts 510 in the same first direction being connected to the same bit lines 500. The bit lines 500 and the bit line contacts 510 are formed to have a height greater than that of the substrate 10, so that the bit lines 500 and the bit line contacts 510 together define a plurality of first openings on the surface of the substrate 10, and sidewalls of the bit lines 500 and the bit line contacts 510 constitute sidewalls of the first openings.
The bit line contact 510 and the bit line 500 may be formed separately, for example, first, an insulating material layer is formed on the substrate 10, and a photolithography process and an etching process are performed thereon to form a bit line contact window in the insulating material layer, the bit line contact window exposing the bit line contact region 110; then, filling a bit line contact material in the bit line contact window to form a bit line contact; then, a bit line material layer can be formed through a deposition process; then, forming an imaging mask layer through a photoetching process, wherein the mask layer defines a bit line pattern; and then, carrying out an etching process by taking the mask layer as a mask to form a bit line, and enabling the bit line to pass through the bit line contact to be connected with the bit line contact. Wherein the bit line contact material for forming the bit line contact and the bit line material for forming the bit line may be the same material. In addition, after the forming the bit line contact and the bit line, the removing the insulating material layer is further included to expose sidewalls of the bit line contact and the bit line. Therefore, in the subsequent process, the first isolation side wall can be formed on the side wall of the contact of the bit line and the bit line, and the formation region of the storage node contact is defined in a self-alignment manner.
However, in the present embodiment, the bit line contact 510 and the bit line 500 are formed at the same time to simplify the process flow. Fig. 3 is a schematic flow chart of a method for forming a memory according to a first embodiment of the present invention when step S200 is executed, and the method for forming bit lines and bit line contacts in this embodiment is described in detail below with reference to fig. 3, fig. 4a to 9a, and fig. 4b to 9 b. In the top views of the memories shown in fig. 4a to 9a, some of the layers, such as word lines, are omitted.
First, step S210 is executed, and referring to fig. 4a and 4b, a first mask layer 600 is formed on the insulating layer 400, wherein a plurality of grooves are formed in the first mask layer 600, and the grooves respectively correspond to bit lines and bit line contacts to be formed subsequently. That is, the first mask layer 600 is formed on the insulating layer 400, so that a photolithography process can be used to simultaneously define the bit line contact and the bit line formation region. Specifically, the grooves include a first groove 610 and a second groove 620, the first groove 610 and the second groove 620 are communicated with each other along a first direction (i.e., an X direction shown in fig. 4 a), the first groove 610 exposes the insulating layer (i.e., the second dielectric layer 420) on the bit line contact region 110, and the second groove 620 exposes the insulating layer (i.e., the first dielectric layer 410) between adjacent bit line contact regions 110.
The recess also extends along a first direction (X direction shown in fig. 4 a) corresponding to the formed bit line, and the first recess 610 defines a formation region of the bit line contact 510, and the second recess 620 defines a connection region between adjacent bit line contacts. The shape of the cross section of the first groove 610 parallel to the substrate surface may be circular, oval, rectangular, etc. as long as the insulating layer on the bit line contact region 110 can be exposed.
In the subsequent process step after forming the bit line contacts, considering that the gap between the two bit line contacts that are most adjacent to each other in the two adjacent bit lines needs to be filled with the isolation material to form the bottleneck closure between the adjacent bit line contacts, in this embodiment, the rectangular first groove 610 is adopted, and the rectangular vertex angles of the two adjacent first grooves 610 are opposite to each other in correspondence to different grooves in the two adjacent grooves, so that the distance between the first grooves 610 that are arranged in close proximity (i.e., the pitch of the first grooves indicated by the oval dotted line in fig. 4 a) can be reduced. It should be appreciated that the rectangle described herein also includes rounded rectangles, i.e., the corners of the rectangle are in an arc configuration. Since the conductive material is filled in the first recess 610 when the bit line contacts are formed subsequently, the formed bit line contacts 510 are also rectangular, and the rectangular vertex angles of the two adjacent bit lines, which correspond to different bit lines and are the most adjacent to the different bit lines, are arranged oppositely, so that the distance between the bit line contacts 510 arranged adjacently is small, the filling of the subsequent isolation material is facilitated by reducing the distance between the bit line contacts 510 arranged adjacently, and the isolation material can be completely filled between the bit line contacts 510 arranged adjacently, so as to isolate the storage node contacts arranged adjacently.
In addition, in the extending direction of the bit line (the first direction), the width Z2 of the first groove 610 and the width Z1 of the second groove 620 may be adjusted according to the inclination angle between the active region 100 and the formed bit line 500, the existing process conditions, and the like. For example, the width Z1 of the second recess 620 may be sufficient to ensure that a recess for receiving the bit line material is formed in the region corresponding to the second recess 620 when the bit line material is filled. For the width Z1 of the first recess 610, it is sufficient to ensure that the bit line contact material does not connect with other conductive regions when filling the bit line contact material; in addition, as described above, in order to further reduce the distance between the first grooves 610 disposed immediately adjacent to each other, the width of the first grooves 610 may be enlarged as much as possible.
In this embodiment, the first recess 610 defines a formation region of the bit line contact 510, and the second recess 620 defines a connection region between adjacent bit line contacts, so that in a subsequent process, the first recess 610 may be filled with a bit line contact material, and the second recess 620 may be filled with a bit line material, so as to form a bit line contact and a bit line, respectively. In this embodiment, the bit line and the bit line contact are formed simultaneously, and the bit line contact material and the bit line material may be formed of the same material. Furthermore, the bit line contact material and the bit line material both comprise a conductive material and an isolation material, and the isolation material is formed on the outer side wall of the conductive material to form a second isolation side wall for the bit line and the bit line to contact, so that the side wall for the bit line and the bit line to contact can be protected and isolated from other devices.
In this embodiment, after the first mask layer 600 is formed, the second isolation sidewall spacers may be preferentially formed by using the first groove 610 and the second groove 620 of the first mask layer 600. Of course, in other embodiments, the second isolation sidewall may also be formed in the subsequent process steps, for example, after the insulating layer in the first groove 610 is removed, the second isolation sidewall is formed by using the groove. The following description will take the example of forming the second isolation sidewall directly using the first recess 610 and the second recess 620 after forming the first mask layer 600 and before removing the insulating layer in the first recess 610 as an example.
That is, step S220 is performed, and referring to fig. 5a and 5b, a second isolation sidewall 500b is formed on sidewalls of the first and second grooves 610 and 620. The method for forming the second isolation sidewall spacers 500b includes:
a first step of depositing a layer of isolating material on the substrate 10, the layer of isolating material covering the entire substrate 10, i.e. covering the bottom and sidewalls of the first recess 610 and the second recess 620, and covering the first mask layer 600;
wherein, the isolation material Layer can be formed by Atomic Layer Deposition (Atomic Layer Deposition) or plasma Vapor Deposition (Chemical Vapor Deposition); and the resistivity of the isolating material layer is preferably 2 x 1011(Ωm)~1×1025(Ω m) to ensure the isolation performance of the formed second isolation sidewall; for example, the isolation material layer may be formed using silicon oxide or silicon nitride;
in a second step, referring to fig. 5a and 5b, an etch-back process is performed on the isolation material layer to remove the isolation material layer located above the first mask layer 600, and remove the isolation material layer at the bottom of the first groove 610 and the second groove 620, so as to form a second isolation sidewall 500b on the sidewalls of the first groove 610 and the second groove 620, where the second isolation sidewall 500b further defines a region of a conductive material to be filled subsequently.
As shown in fig. 5a, after the second isolation sidewall spacers 500b are formed in the first recess 610 and the second recess 620, they can be used to protect the sidewalls of the bit line and the bit line contact formed subsequently and isolate them from other devices; meanwhile, due to the existence of the second isolation sidewall spacers 500b, even if the width of the first groove 610 is large, the exposed area can be reduced by using the second isolation sidewall spacers 500b, and the area which is not required to be exposed is shielded, so that the storage node contact area 120 and the insulating layer above the word line are prevented from being exposed through the first groove 610. It can be seen that the thickness of the second isolation sidewall spacers 500b may also be one of the considerations for adjusting the width of the first groove 610.
Of course, even if the insulating layer above the storage node contact region 120 and the word line is exposed through the first groove 610, the formation of the memory is not affected because the insulating layer (the first dielectric layer 410) is further formed on the storage node contact region 120, as long as the insulating layer above the storage node contact region is remained when the bit line contact is formed subsequently.
Next, step S230 is executed, referring to fig. 6a and 6b, a second mask layer 700 is formed on the first mask layer 600, and the second mask layer 700 covers the second recess 620 and at least exposes a region of the first recess 610 corresponding to the bit line contact region 110, so as to at least expose the insulating layer on the bit line contact region 110. That is, a pattern of bit lines and bit line contacts is defined using the first mask layer 600, and only the pattern of the corresponding bit line contacts is exposed by overlapping the first mask layer 600 and the second mask layer 700 with each other. Therefore, compared with the method of directly defining the pattern of the bit line contact by using one photoetching process, the method has the advantages that the two mask layers are mutually overlapped, so that the photoetching critical dimension of each photoetching process can be increased, the position deviation capacity during photoetching is increased, and the photoetching process window can be favorably enlarged.
In this embodiment, the second mask layer 700 at least exposes a region of the first recess 610 corresponding to the bit line contact region 110, so that the exposed insulating layer is etched later to further expose the bit line contact region 110. As described above, in this embodiment, the second isolation sidewall spacers 500b are formed in the first recess 610 and the second recess 620, so as to prevent the storage node contact region 120 and the insulating layer above the word line from being exposed through the first recess 610. That is, at this time, the region exposed through the first recess 610 only includes the bit line contact region 110 and the corresponding spatial region of the isolation structure, and thus, in step S230, the second mask layer 700 may completely expose the first recess 610, and the insulating layer (the second dielectric layers 420 and 410) exposed in the first recess 610 is removed.
Next, step S240 is executed, and as shown in fig. 7a to 7b, the exposed insulating layer is etched by using the second mask layer 700 as a mask, so as to expose at least the bit line contact region 110. That is, the first dielectric layer and the second dielectric layer in the first recess 610 are removed to expose the bit line contact region 110, so as to be connected to a subsequently formed bit line contact; the insulating layer in the second recess 620 is preserved so that when the second recess 620 is filled with a conductive material, the conductive material is prevented from being connected to the substrate 10 under the insulating layer.
In this embodiment, the insulating layer above the bit line contact region 110 includes a first dielectric layer 410 and a second dielectric layer 420, so that when the insulating layer 400 is etched to expose the bit line contact region 110, the second dielectric layer 420 and the first dielectric layer 410 are sequentially etched.
Next, step S250 is executed, specifically referring to fig. 8a and 8b, removing the second mask layer and filling conductive materials in the first recess 610 and the second recess 620 to form the bit line contact 510 and the bit line 500, wherein the conductive materials filled in the recesses constitute the conductive layer 500a of the bit line and the bit line contact. Specifically, the conductive layer 500a and the second isolation sidewall 500b in the first groove 610 form the bit line contact 510, and the conductive layer 500a in the first groove 610 and the conductive layer 500a in the second groove 620 are connected to each other and combined with the second isolation sidewall 500b to form the bit line 500. Wherein the bit line contact 510 is formed on and in contact with the bit line contact region 110.
It is to be understood that the bit line contact 510 is formed to constitute a portion of the bit line 500; of course, it is also understood that, of the bit line contact material formed on the bit line contact region 110, the bit line contact material closer to the bit line contact region 110 constitutes a bit line contact, and the bit line contact material farther from the bit line contact region 110 constitutes a portion of the bit line 500.
Further, the conductive layer 500a may be formed in combination with a deposition process and a planarization process. For example, the method for forming the conductive layer 500 includes:
a first step of forming a conductive material layer on the substrate 10, wherein the height of the conductive material layer is greater than that of the first mask layer 600, so as to ensure that the bit line groove can be filled with the conductive material; wherein the conductive material Layer may be formed by Atomic Layer Deposition (Atomic Layer Deposition) or plasma Vapor Deposition (Chemical Vapor Deposition);
wherein the resistivity of the conductive material layer is preferably 2 × 10-8(Ωm)~1×102(Ω m) to ensure the conductive property of the formed conductive layer. Specifically, the conductive material constituting the conductive material layer may be a metal material such as one of tungsten (Wu), titanium (Ti), nickel (Ni), aluminum (Al), platinum (Po), or a combination thereof, or doped polysilicon. In addition, when the conductive material is a metal material, the bit line 500 and the bit line contact 510 may further include a metal barrier layer, and the metal barrier layer prevents metal ions in the metal material from diffusing into the peripheral isolation sidewall or the peripheral dielectric layer. The metal barrier layer may be formed preferentially on the bottom and sidewalls of the bitline recess prior to forming the conductive material layer, followed by depositing the conductive material layer on the substrate to form a conductive layer. The metal barrier layer is, for example, titanium nitride (TiN), titanium silicide (TiSi), titanium silicon nitride (TiSiN), or nickel silicide (NiSi).
A second step of performing a planarization process on the conductive material layer to remove all the conductive material above the first mask layer 600; the planarization process may be a chemical mechanical polishing process, and in addition, the planarization process may further include a back etching process, that is, after the chemical mechanical polishing process is performed, the conductive material layer is continuously back etched, so that the conductive material above the first mask layer 600 is completely removed, and the conductive material is formed in the groove to form the bit line contact 510 and the bit line 500.
It can be seen that in the present embodiment, only two photolithography processes are used to simultaneously expose the formation region of the bit line contact and the formation region of the bit line, so that bit line materials (or bit line contact materials) can be simultaneously formed to form the bit line contact 510 and the bit line 500, and the bit line contact 510 can be electrically connected to the bit line 500, thereby ensuring that the information in the bit line contact region 110 can be read out to the corresponding bit line 500 through the bit line contact 510, and on the basis of ensuring the performance of the memory, the number of times of performing the photolithography process is reduced, the process is simplified, and it is also beneficial to expanding the photolithography process window.
Further, referring specifically to fig. 8a, the bit line 500 is formed to extend along the X direction shown in fig. 8a, the active region extends obliquely relative to the bit line 500, and the bit line 500 intersects the active region 100 and forms an included angle (i.e., the included angle between the X direction and the Z direction shown in fig. 9 a), which is, for example, in the range of 58 ° to 75 °, and in the present embodiment, is equal to 72 °.
Next, step S260 is performed, specifically referring to fig. 9a and 9b, removing the first mask layer, exposing sidewalls of the bit line contact 510 and the bit 500 to define the first opening, and exposing the insulating layer (first dielectric layer 410) on the storage node contact region 120 through the first opening.
Specifically referring to fig. 9a and 9b, after forming the second isolation sidewall 500b and the conductive layer 500a in the groove of the first mask layer to form the bit line 500 and the bit line contact 510, the first mask layer may be removed, and after removing the first mask layer, the sidewalls of the bit line 500 and the bit line contact 500 may be exposed, in this embodiment, the sidewalls of the bit line 500 and the bit line contact 510 are sidewalls of the second isolation sidewall 500 b. It is understood that the heights of the bit lines 500 and the bit line contacts 510 are greater than the height of the substrate 10, so that after the first mask layer is removed, the bit lines 500 and the bit line contacts 510 form a plurality of first openings on the surface of the substrate, and the sidewalls of the bit lines and the bit line contacts are the sidewalls of the first openings.
The insulating layer exposed through the first opening is an insulating layer located below the first mask layer, and specifically, the insulating layer located below the first mask layer includes an insulating layer (i.e., a first dielectric layer) located above the storage node contact region 120, and may also include an insulating layer located above a portion of the isolation structure and an insulating layer located above a portion of the word line.
Next, step S270 is performed, and with continued reference to fig. 9a and 9b, an etching process is performed on the exposed insulating layer through the first opening to remove the insulating layer on the storage node contact region 120 and expose the storage node contact region 120. It should be understood that after removing the insulating layer in the first opening, a portion of the isolation structure formed in the substrate 10 may also be exposed.
In the etching step, an etching process having a high etching selectivity to the insulating layer may be selected. Specifically, in the present embodiment, the insulating layer located above the non-bit line contact region is a first dielectric layer 410, and the material of the first dielectric layer 410 is silicon nitride (SiN). In addition, it should be understood that, when the material of the bit line contact and the second isolation sidewall 500b of the bit line is also silicon nitride, the second isolation sidewall 500b is also partially consumed in the etching process. However, even if the second isolation sidewall 500b is partially consumed in this step, the performance of the formed memory is not affected, because the subsequent process steps further include forming a first isolation sidewall on the second isolation sidewall 500b, and at this time, the first isolation sidewall can compensate for the consumed portion.
Fig. 9b shows a case where the second isolation sidewall 500b is formed of a material different from that of the insulating layer, and therefore, when the etching process with a higher selection ratio for the insulating layer is used for etching, the second isolation sidewall 500b and the conductive layer 500a are not affected, that is, the second isolation sidewall 500b and the conductive layer 500a are directly used as a mask layer, so that the insulating layer below the second isolation sidewall 500b is retained.
Fig. 10a is a top view of the memory during the step S300, and fig. 10b is a cross-sectional view of the memory along the directions of AA ', BB ' and CC ' during the step S300, corresponding to the method for forming the memory in the first embodiment of the invention shown in fig. 10 a.
In step S300, referring to fig. 10a and 10b, first isolation spacers 800 are formed on sidewalls of the first openings, that is, the first isolation spacers 800 are formed on sidewalls of the bit lines 500 and the bit line contacts 510, in two adjacent bit lines 500, the first isolation spacers 800 on the sidewalls of the adjacent bit line contacts 510 are connected to each other to form a bottleneck seal 800a, and the bottleneck seal 800a and the first isolation spacers 800 together define a second opening, which is defined in the first opening and exposes the storage node contact region 120.
Similar to the forming method of the second isolation sidewall, the forming method of the first isolation sidewall 800 includes:
first, a layer of isolation material is deposited on the substrate 10, covering the entire substrate 10, including the tops and sidewalls covering the bit lines 500 and bit line contacts 510, and covering the substrate 10 between adjacent bit lines 500. That is, the spacer material layer covers the sidewalls and the bottom of the first opening.
In this embodiment, the first recess is rectangular, so the bit line contacts 510 are also rectangular, and the corners of the adjacent bit line contacts 510 are opposite to each other, so that the distance between two adjacent bit line contacts 500 corresponding to different bit lines 500 and adjacent bit line contacts 510 is small (i.e. the distance between two bit line contacts in the oval dotted line region in fig. 10 a). Furthermore, in two adjacent bit lines 500, when the minimum distance between the bit line contacts 510 disposed next to each other is less than or equal to 2 times the deposition thickness of the isolation material layer covering the sidewalls of the bit line contacts, the isolation material layers between the bit line contacts disposed next to each other are connected to each other, so that the isolation material is filled between the bit line contacts disposed next to each other. Here, the deposition thickness of the isolation material layer refers to the thickness of the isolation material layer in the direction parallel to the substrate surface. Of course, in two adjacent bit lines, the distance between the bit line contacts 510 corresponding to different bit lines 500 and disposed next to each other may also be greater than 2 times the thickness of the isolation material layer, and at this time, the isolation material layer may be filled between the bit line contacts disposed next to each other by performing the deposition process of the isolation material layer multiple times.
Next, referring to fig. 10a and 10b, an etch back process is performed to remove the isolation material layer on the top of the bit line 500 and the bit line contact 510, and to partially remove the isolation material layer on the bottom of the first opening, so as to form a first isolation sidewall spacer 800 on the sidewalls of the bit line 500 and the bit line contact 510. At this time, in two adjacent bit lines 500, the first isolation sidewalls 800 between the bit line contacts 510 that are adjacent to and correspond to different bit lines are connected to each other to form the bottleneck seal 800a, that is, the region CC' in fig. 10b shows a schematic diagram of the bottleneck seal 800a formed by the first isolation sidewalls 800a connected to each other between the bit line contacts 510 that are adjacent to and adjacent to each other. In this embodiment, the thickness of the first isolation sidewall 800 is, for example, 3nm to 50 nm.
Referring to fig. 10a, after the bottleneck seal 800a is formed, the storage node contact regions 120 disposed adjacent to each other may be isolated from each other, so as to prevent the storage node contacts subsequently formed on the storage node contact regions 120 from being connected to each other. Furthermore, as shown in fig. 10a, due to the existence of the bottleneck seal 800a, the first isolation sidewall 800 and the bottleneck seal 800a can form a second opening, and the second opening exposes the storage node contact region 120, i.e., a self-aligned formation region defining the storage node contact.
Fig. 11a is a top view of the memory during the step S400, and fig. 11b is a cross-sectional view of the memory along the directions of AA ', BB ' and CC ' during the step S400, corresponding to the method of fig. 11 a.
In step S400, referring to fig. 11a and 11b, a contact material is filled in the second opening formed after the first isolation sidewall 800 is formed, and the contact material contacts the storage node contact region 120 to form the storage node contact 900.
Wherein the contact material is a conductive material. Further, the conductive material of the storage node contact 900 may be the same as the conductive material of the bit line contact 510. As mentioned above, detailed description is omitted here. Similarly, the storage node contact 900 may be formed in the same method as the filling method of the conductive material in the bit line contact 510. That is, the storage node contact 900 is formed in combination with a deposition process and an etch-back process.
As can be seen from the combination of step S300 and step S400, when the storage node contact 900 is formed, a photolithography process is not required, but a first opening formed by the bit line 500 and the bit line contact 510 is used, and a bottleneck seal 800a is formed while forming the first isolation sidewall 800 by using the first opening, and a second opening in which the storage node contact is to be formed is defined by self-aligning the first isolation sidewall 800 and the bottleneck seal 800a, so that the storage node contact 900 can be formed only by filling a contact material in the second opening. Therefore, the execution times of the photoetching process can be reduced; in addition, a forming area of the storage node contact is not required to be defined by utilizing a photoetching process, so that the limitation of a photoetching process window is avoided; meanwhile, the forming area of the storage node contact is defined through self-alignment, and the preparation difficulty of the memory is simplified.
Example two
Fig. 12a is a top view of the memory according to the second embodiment of the present invention, and fig. 12b is a cross-sectional view of the memory according to the second embodiment of the present invention shown in fig. 12a along the directions AA ', BB ' and CC '. As shown in fig. 12a and 12b, the memory includes:
a substrate 10, wherein a plurality of active regions 100 extending obliquely to a first direction (i.e., Z direction shown in fig. 12 a) are defined on the substrate 10, and bit line contact regions 110 and storage node contact regions 120 located at two sides of the bit line contact regions 110 are formed on the active regions 100; it should be noted that fig. 12a only schematically shows several active regions 100;
a plurality of bit line contacts 510 formed on the bit line contact regions 110 and contacting the bit line contact regions 110;
a plurality of bit lines 500 extending in the first direction (i.e., the X direction shown in fig. 12 a), and the bit line contacts 510 arranged on the same line are connected to the same bit line 500;
wherein the bit lines 500 and the bit line contacts 510 together define a plurality of first openings on the surface of the substrate 10, the combination of the sidewalls of the bit lines 500 and the bit line contacts 510 constituting the sidewalls of the first openings;
a plurality of first isolation sidewalls 800 on sidewalls of the first opening (i.e., on sidewalls of the bit line 500 and the bit line contact 510), the first isolation sidewalls 800 on sidewalls of two adjacent bit line contacts 510 between two adjacent bit lines 500 are connected to each other to form a bottleneck seal 800 a;
specifically, the bottleneck seal 800a and the first isolation sidewall 800 on the sidewall of the adjacent bit line 500 together define a second opening, and the second opening is in the first opening and defines a region corresponding to the storage node contact region 110;
and a plurality of storage node contacts 900 formed in the second opening, wherein the immediately adjacent storage node contacts 900 are separated by at least the bottleneck closure 800 a.
Fig. 13 shows an arrangement of active regions in a memory according to a second embodiment of the present invention, and the substrate is described in detail below with reference to fig. 12a, 12b, and 13.
As shown in fig. 13, a plurality of active regions 100 are arranged in an array, and isolation structures 200 are further formed at the periphery of the active regions 100, wherein adjacent active regions 100 are isolated from each other by the isolation structures 200.
Next, as shown in fig. 12a and fig. 13, since the active regions 100 extend obliquely with respect to the first direction and the bit line contact regions 110 are arranged in a staggered manner, in two adjacent active regions 100, two sides of a connection line between two bit line contact regions 110 are respectively provided with a storage node contact region 120. Therefore, after the bit line contacts 510 are formed on the bit line contact regions 110 and the storage node contacts 900 are formed on the storage node contact regions 120, the storage node contacts 900 located at both sides of the bottleneck seal 800a can be isolated by forming the bottleneck seal 800a between the two bit line contacts 510 in the two adjacent active regions 100.
Wherein the bit line contact region 110 is used for contacting the bit line contact 510 and connecting to the bit line 500; the storage node contact region 120 is used for contacting the storage node 900, which may be connected to a storage capacitor. Further, the bit line contact region 110 and the storage node contact region 120 are also used to form a portion of a memory cell (not shown), which is at least partially formed in the substrate 10. Specifically, the memory cell is a memory transistor, a source region of the memory transistor forms the bit line contact region 110, a drain region of the memory transistor forms the storage node contact region 110, and the storage capacitor is connected to the memory transistor, so that the memory can be operated by controlling an operating state of the memory transistor, for example, information in the storage capacitor can be read.
Further, a plurality of word lines 300 are formed in the substrate 10, and the word lines 300 extend in a second direction (Y direction shown in fig. 12a or 13). Wherein the gates of the memory transistors are connected to said word line 300, so that the memory transistors are addressed via said word line 300. As shown in fig. 12b, the word line 300 is also covered with an insulating layer 400, so that the word line 300 can be isolated from other devices by the insulating layer 400. Alternatively, the word line 300 is a buried word line, i.e., the word line 300 is formed in a word line trench. Preferably, the word line 300 does not completely fill the word line trench, and the insulating layer 400 is further filled in the word line trench in which the word line 300 is formed.
In addition, the insulating layer 400 is formed in a position corresponding to the word line 300, and the insulating layer 400 is covered in other regions. In the present embodiment, the insulating layer 400 is formed on the surface of the substrate 10 at the positions of the non-corresponding bit line contacts 510 and the non-corresponding storage node contacts 900, for example, referring to the schematic structure in the AA' direction shown in fig. 12b, the insulating layer 400 is formed on the substrate at the regions of the bit lines 500 not corresponding to the bit line contacts 510, so that the bit lines 500 can be isolated from the substrate 10 therebelow by the insulating layer 400.
With continued reference to fig. 12a and 12b, the bit line contact 510 includes a conductive layer 500a and a plurality of second isolation sidewall spacers 500 b. The conductive layer 500a contacts the bit line contact region 110, and the second isolation sidewall 500b is located on a sidewall of the conductive layer 500a to protect the conductive layer 500a and isolate the conductive layer 500a from other devices. In addition, the second isolation sidewall spacers 500b may also be used to define a formation region of the conductive layer 500 a. In this embodiment, when defining the formation region of the conductive layer 500a, the second isolation sidewall 500b is used, and an insulating layer is further combined. Specifically, the insulating layer is formed on the substrate 10, and the second isolation sidewall 500b is formed on the insulating layer. The insulating layer may have a stacked structure, and in this embodiment, the insulating layer includes a first dielectric layer 410 and a second dielectric layer 420, and the first dielectric layer 410 and the second dielectric layer 420 may be formed of different materials, for example, the first dielectric layer 410 may be an oxide layer, and the second dielectric layer 420 may be a nitride layer.
Further, the cross section of the bit line contact 510 parallel to the substrate surface is rectangular, and the rectangular corners of two bit line contacts 510 nearest to each other in two adjacent bit lines 500 are opposite to each other. Therefore, the distance between the bit line contacts 510 arranged in close proximity can be reduced, and the purpose of interconnecting the first isolation spacers 800 between the bit line contacts 510 arranged in close proximity can be achieved more easily. That is, in the present embodiment, the bit line contact 510 is used to realize the function of the bit line contact 510 itself, and the rectangular bit line contact 510 is also used to facilitate the isolation of the storage node contact 900. Specifically, the distance between the bit line contacts 510 arranged in close proximity is reduced, which is beneficial to connecting the first isolation side walls 800 on the side walls of the two bit line contacts 510 arranged in close proximity to each other, so as to form a bottleneck seal 800a, and the storage node contacts 900 arranged in close proximity are isolated by the bottleneck seal 800 a.
Referring next to fig. 12a and 12b, bit line contacts 510 arranged in the same straight line are connected to the same bit line 500. In this embodiment, the bit line contact 510 forms part of the bit line 500, i.e. as shown in fig. 12a, the bit line 500 comprises the bit line contact 510 and a connecting wire connecting adjacent bit line contacts 510. Further, the bit line 500 may also include a conductive layer 500a and a second isolation sidewall 500b, where the second isolation sidewall 500b is located on a sidewall of the conductive layer 500a, and the conductive layer 500a in the connection wire is connected to the conductive layer 500a in the bit line contact 510. That is, a portion of the conductive layer 500a located in the bit line contact 510 is in contact with the bit line contact region 110 and is connected to a portion of the conductive layer 500a located in the bit line 500. Similar to the bit line contact 510, the second isolation sidewall spacers 500b in the bit line 500 may be used to define a formation region of the conductive layer 500 a. Preferably, the second isolation sidewall spacers 500b in the bit line 500 and the bit line contact 510 are simultaneously formed to simultaneously define the formation regions of the conductive layer 500a in the bit line 500 and the bit line contact 510.
In addition, fig. 13 schematically shows the arrangement direction of a bit line 500, and as shown in fig. 13, the bit line extends along the first direction (X direction), the active region 100 extends along the direction inclined with respect to the first direction (Z direction), and an included angle θ may be formed between the bit line 500 and the active region 100, and the included angle θ may range from 58 ° to 75 °, for example, and in this embodiment, is equal to 72 °.
As mentioned above, in the present embodiment, the distance between the bit line contacts 510 disposed in close proximity is reduced by using the bit line contacts 510 having a rectangular shape, which is advantageous for forming the bottleneck closure 800 a. Preferably, the distance between the bit line contacts 510 disposed closely to each other may be adjusted according to the thickness Z3 of the first isolation sidewall 800 (the thickness Z3 is a thickness in a direction parallel to the substrate surface). For example, the minimum distance between the bit line contacts 510 disposed immediately adjacent to each other may be less than or equal to 2 times the thickness Z3 of the first isolation sidewall spacer 800. In this way, an isolation material may be deposited by a single deposition process to form the isolation sidewall spacers 800, and at the same time, the isolation material may be filled between the bit line contacts 510 disposed in close proximity to each other, which is equivalent to interconnecting the first isolation sidewall spacers 800 to form the bottleneck seal 800 a. Reference may be made to the schematic structural diagrams in the CC' direction in fig. 12a and 12 b.
As can be seen, by forming the first isolation sidewall 800 and the bottleneck closure 800a, the formation region of the storage node contact 900 can be defined in a self-aligned manner, and the storage node contacts 900 disposed adjacent to each other can be further isolated from each other. As shown in fig. 12a, in the present embodiment, the storage node contact 900 is formed in the opening formed by the first isolation sidewall 800 and the bottleneck seal 800. Further, the storage node contact 900 includes a metal barrier layer formed on the bottom and the sidewall of the opening and a contact layer formed on the metal barrier layer and filling the opening. The material of the metal barrier layer is, for example, titanium nitride (TiN), titanium silicide (TiSi), titanium silicon nitride (TiSiN), or nickel silicide (NiSi); the material of the contact layer is, for example, one or a combination of tungsten (Wu), titanium (Ti), nickel (Ni), aluminum (Al), platinum (Po), and the like.
Obviously, the conductive layer 500a in the bit line 500 and the bit line contact 510 may also be formed of the same material as the contact layer in the storage node contact 900. And, a metal barrier layer may be further included in the bit line 500 and the bit line contact 510, and after forming the second isolation sidewall spacers 500b to define a formation region of the conductive layer 500a, the metal barrier layer may be formed in the formation region, and then the conductive layer 500a is filled. That is, the metal barrier layer is formed between the conductive layer 500a and the second isolation sidewall spacers 500b, and between the conductive layer 500a and the bit line contact regions 110.
EXAMPLE III
In addition, based on the memory, the invention also provides a semiconductor device. In the semiconductor field, when the lead-out region is led out, it is usually necessary to form a corresponding lead-out terminal in contact with the lead-out region, so that the lead-out region can be controlled and led out through the lead-out terminal. When a plurality of different lead-out regions need to be led out, the lead-out terminals which do not correspond to each other should be ensured to be isolated from each other, so as to avoid the problem of crosstalk of signals.
In this respect, the invention provides a semiconductor component in which at least two different extraction regions, namely a first contact region and a second contact region, are present. And forming a first conductor contact on the first contact region, defining an opening by using the side wall of the first conductor contact after the first conductor contact is formed, and defining the second contact region in a self-aligned manner through the opening so as to enable the formed second conductor contact to be in self-aligned contact with the second contact region. The semiconductor device in this embodiment will be described in detail below with reference to the drawings.
Fig. 14 is a schematic structural diagram of a semiconductor device according to a third embodiment of the present invention, and fig. 15 is a schematic distribution diagram of first contact regions and second contact regions in a substrate of the semiconductor device according to the third embodiment of the present invention shown in fig. 14; as shown in connection with fig. 14 and 15, the semiconductor device includes:
a substrate 1 comprising a first contact region 11 and a second contact region 12;
a plurality of first conductor contacts 2 disposed on the substrate 1 and electrically connected to the first contact regions 11;
a plurality of conductor lines 3 disposed on the substrate 1, wherein the first contact regions 11 arranged in series along the same conductor line 3 are electrically connected via the same conductor line 3, the conductor lines 3 and the first conductor contacts 2 jointly define a plurality of first openings 1a on the surface of the substrate 1, and the combination of the conductor lines 3 and the sidewalls of the first conductor contacts 2 forms sidewalls of the first openings 1 a;
a plurality of isolation side walls 4, wherein the isolation side walls 4 on the side walls of the adjacent first conductor contacts 2 are connected with each other between two adjacent conductor lines 3 on the side walls of the first opening 1a to form a bottleneck seal 41, the bottleneck seal 41 and the isolation side walls 4 on the side walls of the adjacent conductor lines 3 jointly define a second opening 1b, the second opening 1b is defined in the first opening 1a and defines a region corresponding to the second contact region 12, and the second opening 1b has a more rounded shape relative to the first opening 1 a; and the number of the first and second groups,
and a plurality of second conductor contacts 5 formed in the second opening 1b and electrically connected to the second contact region 12.
That is, in the semiconductor device, the extending direction of the conductor line 3 may be arranged according to the distribution of the first contact region 11 and the second contact region 12, so that the first contact region 11 and the conductor line 3 can be matched with each other, and thus at least the region of the second contact region 12 can be corresponded in the first opening 1a defined by the conductor line 3 and the first conductor contact 2 after the first conductor contact 2 and the conductor line 3 are formed. The isolation side wall 4 located in the first opening 1a can be used for isolating the first conductor contact 2 from the second conductor contact 5, and meanwhile, the isolation side wall 4 can also be used for correcting the appearance of the first opening 1a, so that the appearance of the second opening 1b defined by the isolation side wall 4 is more rounded relative to the appearance of the first opening 1a, and the appearance of the second opening 1b is more rounded relative to the appearance of the second opening 1 b.
In addition, between two adjacent conductor lines 3, the isolation side walls 4 located on the side walls of the adjacent first conductor contacts 2 are connected to form a bottleneck seal 41, which is not only beneficial to correcting the appearance of the first opening 1a, but also beneficial to isolating the adjacent second conductive contacts 5 from each other by using the bottleneck seal 41 when the first opening 1a corresponds to a region with a plurality of second contact regions 12. That is, the second opening 1b can be defined by the sidewall spacer 4 and the neck seal 41 in the first opening 1a, and the second opening 1b corresponds to only one second contact area 12.
As described above, the extending direction of the conductor lines 3 can be adjusted according to the distribution of the first contact regions 11 and the second contact regions 12, and therefore, the shape of the conductor lines 3 may be a straight line, a curved line, or any other shape, and the plurality of conductor lines 3 formed may be parallel or nearly parallel to each other.
Referring to fig. 14 and 15, in the present embodiment, only one arrangement of the first contact region 11 and the second contact region 12 is schematically shown. That is, the plurality of first contact regions 11 are arranged in an array, and the plurality of first contact regions 11 are aligned in a first direction (X direction shown in fig. 14) and a second direction (Y direction shown in fig. 14), wherein the first direction and the second direction are perpendicular to each other; the second contact region 12 is located between two adjacent first contact regions 11 in the first direction.
With reference to fig. 15, according to the arrangement of the first contact area 11 and the second contact area 12 in the embodiment, a curved conductor line 3 may be further disposed, as shown in the extending direction 3a of the conductor line 3 shown in fig. 15, which is curved, so that the first contact areas 11 located on the same straight line can be connected to the conductor line 3, and the second contact areas 12 can be bypassed to avoid being connected to the second contact areas 12.
The first contact area 11 is formed with a first conductor contact 2, and the first conductor contact 2 is connected to the corresponding conductor line 3, so as to electrically connect the first contact area 11 and the conductor line 3. Wherein the conductor line 3 and the first conductor contact 2 are both arranged on the substrate 1, the surface height of the conductor line 3 and the first conductor contact 2 is greater than the surface height of the substrate 1, and therefore the conductor line 3 and the first conductor contact 2 can jointly define a plurality of first openings 1a on the surface of the substrate 1, the combination of the conductor line 3 and the side wall of the first conductor contact 2 constituting the side wall of the first openings 1 a. And at least one second contact region 12 is correspondingly arranged in the first opening 1 a.
Referring to fig. 15, after forming the isolation sidewall 4 on the sidewall of the first opening 1a, the corresponding position of the second conductor contact 5 can be further defined. Specifically, the isolation side wall 4 can isolate the first conductor contact 2 and the second conductor contact 5 on the one hand; on the other hand, between two adjacent conductor lines 3, the isolation side walls 4 on the side walls of the adjacent first conductor contacts 2 are connected to each other, so that a bottleneck seal 41 can be formed, a second opening 1b can be defined by the bottleneck seal 41 and the isolation side walls 4 together, and the second opening 1b is defined in the first opening 1a and defines a region corresponding to the second contact region 12. It can be seen that in the second opening 1b formed by the isolating sidewall 4 and the bottleneck closure 41, only one second contact region 12 can be corresponded, so that adjacent second conductor contacts 5 can be isolated from each other.
In addition, the shape of the first opening 1a can be corrected by forming the isolation side wall 4 on the side wall of the first opening 1a, so that the shape of the second opening 1b is more rounded. Specifically, the corner area of the first opening 1a can be modified to make the corner of the second opening 1b smoother than the corner of the first opening 1 a. For example, when a vertex angle exists in the first opening 1a, after the isolation sidewall 4 is formed, an arc shape may be formed in a region corresponding to the vertex angle. Therefore, the shape of the cross section of the second opening 1b parallel to the surface of the substrate 1 may be a rounded rectangle, a circle, an ellipse, or the like.
As mentioned above, between two adjacent conductor lines 3, the isolation side walls 4 on the side walls of the adjacent first conductor contacts 2 are connected to each other to form a bottleneck seal 41. Therefore, in two adjacent conductor lines 3, the minimum spacing distance Z3 between two adjacent first conductor contacts 2 may be less than or equal to 2 times the thickness of the isolation side wall 4, and the thickness of the isolation side wall 4 is the dimension of the isolation side wall 4 along the direction parallel to the surface of the substrate 1, so that the isolation side walls 4 on the side walls of the adjacent first conductor contacts 2 can be ensured to be connected with each other. The thickness of the isolation sidewall 4 is, for example, 3nm to 50 nm.
That is, by adjusting the minimum separation distance Z4 between two adjacent first conductor contacts 2, it is advantageous to ensure the formation of the bottleneck closure 41. To be able to further adjust the minimum separation distance Z4 between adjacent first conductor contacts 2, the shape and/or size, etc. of the first conductor contacts 2 may be set. For example, by increasing the size of the first conductor contacts 2 to reduce the minimum separation distance Z4 between adjacent first conductor contacts 2, it is sufficient if the first conductor contacts 2 are prevented from being electrically connected to other devices. In this embodiment, the first conductor contact 2 includes a conductive layer (not shown) and a conductive isolation sidewall (not shown), the conductive layer is electrically connected to the first contact region 11, and the conductive isolation sidewall is located on a sidewall of the conductive layer. The conductive isolation side wall can ensure the isolation effect of the conductive layer in the first conductor contact 2 and avoid connection with other devices; moreover, the size of the first conductor contact 2 can be further increased on the basis of not influencing the size of the conductive layer in the first conductor contact 2, which is beneficial to reducing the minimum spacing distance Z4 between adjacent first conductor contacts 2. Preferably, the conductor line 3 also includes a conductive layer and a conductive isolation sidewall on a sidewall of the conductive layer, and the conductive layer in the first conductor contact 2 is connected to the conductive layer in the conductor line.
In the present embodiment, the first contact regions 11 are aligned, and therefore, the first conductor contact 2 formed on the first contact region 11 may have any shape as long as the first conductor contact 2 can be electrically connected to the first contact region 11 to lead out the first contact region 11. The shape of the first conductor contact 2 is a shape parallel to the cross section of the surface of the substrate 1, and the arbitrary shape is, for example, a rectangle, a circle, an ellipse, or the like, and the rectangle also includes a rounded rectangle. Of course, in other embodiments, if the first contact regions 11 are arranged in a staggered manner, rectangular first conductor contacts may be adopted, that is, the cross section of the first conductor contacts parallel to the substrate surface is rectangular, and the rectangular corners of the adjacent first conductor contacts are opposite, so that the minimum spacing distance between the adjacent first conductor contacts can be further reduced.
The second conductor contact 5 is formed in the second opening 1b, and it can be seen that when the second opening 1b is defined by forming the isolation sidewall 4, a forming region of the second conductor contact 5 can be defined by self-alignment due to the self-aligned second conductor contact region 12 corresponding to the second opening 1 b.
In summary, in the method for forming a memory provided by the present invention, after bit lines and bit line contacts are formed, isolation sidewalls are formed on sidewalls of the first opening by using the first opening formed by the bit lines and the bit line contacts, and the first isolation sidewalls on two nearest adjacent bit line contacts in two adjacent bit lines are connected to form a bottleneck seal, where the bottleneck seal can isolate the storage node contact regions disposed adjacent to each other; meanwhile, a second opening can be formed by utilizing the first isolation side wall and the bottleneck seal, and the second opening can be self-aligned to expose the storage node contact area, so that the storage node contact can be formed without utilizing a photoetching process when the storage node contact is formed. Therefore, on one hand, the execution times of the photoetching process can be reduced, the process flow is simplified, the preparation cost is saved, the limitation of a photoetching process window can be avoided, and the preparation difficulty of the memory can be reduced; on the other hand, the forming area of the storage node contact can be defined in a self-alignment mode, and the process window is further expanded.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (17)

1. A method for forming a memory, comprising:
providing a substrate, wherein a plurality of active regions extending obliquely relative to a first direction are defined on the substrate, bit line contact regions and storage node contact regions positioned at two sides of the bit line contact regions are formed on the active regions, the active regions are arranged in an array manner, and the bit line contact regions are arranged in a staggered manner;
forming a bit line contact on the bit line contact region, and forming a plurality of bit lines on the substrate, the bit lines extending in the first direction, the bit line contacts arranged in a same line being connected to a same bit line, the bit line and the bit line contact having a height greater than a height of the substrate, such that the bit line and the bit line contact together define a plurality of first openings on a surface of the substrate, a combination of sidewalls of the bit line and the bit line contact constituting sidewalls of the first openings;
forming first isolation side walls on the side walls of the first openings, wherein the first isolation side walls of the adjacent bit line contacts are connected between the two adjacent bit lines to form a bottleneck seal, the bottleneck seal and the first isolation side walls on the side walls of the adjacent bit lines and the adjacent bit line contacts define a second opening together, and the second opening is defined in the first opening and exposes the storage node contact region; and the number of the first and second groups,
a fill contact material is in the second opening to form a storage node contact.
2. The method for forming the memory according to claim 1, wherein the step of forming the first isolation sidewall spacers comprises:
depositing a layer of isolation material on the substrate, the layer of isolation material covering the bit lines and the tops of the bit line contacts and covering the sidewalls and the bottom of the first openings; and the number of the first and second groups,
and performing a back etching process to remove the isolation material layer on the top of the bit line and the bit line contact and partially remove the isolation material layer at the bottom of the first opening so as to form the first isolation side wall on the side wall of the first opening.
3. The method according to claim 2, wherein a minimum separation distance between two adjacent bit lines among two adjacent bit line contacts is less than or equal to 2 times a deposition thickness of the isolation material layer, and the deposition thickness of the isolation material layer is a dimension of the isolation material layer in a direction parallel to the substrate surface before the back etching process.
4. The method of claim 2, wherein a minimum separation distance between two adjacent bit lines among two adjacent bit line contacts is greater than 2 times a thickness of the isolation material layer, and the isolation material layer is deposited to a thickness that is a dimension of the isolation material layer in a direction parallel to the substrate surface before the etch-back process.
5. The method of claim 4, wherein the step of depositing the isolation material layer is performed at least twice to fill the isolation material layer between two adjacent bit line contacts of two adjacent bit lines.
6. The method of forming a memory according to any one of claims 1 to 5, further comprising, before forming the bit line:
forming a word line in the substrate; and the number of the first and second groups,
an insulating layer is formed on the substrate, the insulating layer covering the word lines.
7. The method of forming a memory of claim 6, wherein the forming of the bit line contact and the bit line comprises:
forming a first mask layer on the insulating layer, wherein a plurality of grooves corresponding to the bit lines and the bit line contacts are formed in the first mask layer, the grooves comprise first grooves and second grooves, the first grooves and the second grooves are communicated with each other along the first direction, the first grooves expose the insulating layer on the bit line contact regions, and the second grooves expose the insulating layer between the adjacent bit line contact regions;
forming a second mask layer on the first mask layer to cover the second groove and expose the first groove;
etching the exposed insulating layer by taking the second mask layer as a mask to expose the bit line contact region;
removing the second mask layer and filling a conductive material in the groove, wherein the conductive material in the groove forms a conductive layer of the bit line, and the conductive material in the first groove forms a conductive layer contacted with the bit line;
removing the first mask layer, exposing the bit line contact and the side wall of the bit line to define a first opening together, and exposing the insulating layer on the storage node contact region through the first opening; and the number of the first and second groups,
and removing the insulating layer on the storage node contact region to expose the storage node contact region.
8. The method of claim 7, wherein a cross section of the first recess parallel to the surface of the substrate has a rectangular shape, and corners of the rectangles of two adjacent first recesses of two adjacent recesses are opposite.
9. The method of forming a memory as claimed in claim 7, wherein after forming the first mask layer and before forming the second mask layer, further comprising:
and forming second isolation side walls on the side walls of the first groove and the second groove.
10. A memory, comprising:
the array type memory device comprises a substrate, a plurality of storage node contact areas and a plurality of control circuits, wherein a plurality of active areas extending obliquely relative to a first direction are defined on the substrate, bit line contact areas and storage node contact areas positioned on two sides of the bit line contact areas are formed on the active areas, the active areas are arranged in an array mode, and the bit line contact areas are arranged in a staggered mode;
a plurality of bit line contacts formed on and in contact with the bit line contact regions;
a plurality of bit lines extending in the first direction, wherein the bit line contacts arranged in a same straight line are connected to a same bit line, the bit lines and the bit line contacts define a plurality of first openings on the surface of the substrate, and the combination of the bit lines and the sidewalls of the bit line contacts form sidewalls of the first openings;
the first isolation side walls on the side walls of the first openings and between two adjacent bit lines are connected with each other to form a bottleneck seal, the bottleneck seal and the first isolation side walls on the adjacent bit lines and the side walls of the bit line contacts define a second opening together, and the second opening is arranged in the first opening and defines an area corresponding to the storage node contact area; and the number of the first and second groups,
a plurality of storage node contacts formed in the second opening, immediately adjacently disposed storage node contacts being isolated from each other by at least the bottleneck closure.
11. The memory of claim 10, wherein a minimum distance between two adjacent bit line contacts in two adjacent bit lines is less than or equal to 2 times the thickness of the first isolation sidewall, and the thickness of the first isolation sidewall is equal to a dimension of the first isolation sidewall in a direction parallel to the substrate surface.
12. The memory of claim 10, wherein a cross-section of the bit line contact parallel to the substrate surface has a rectangular shape, and corners of rectangles of two adjacent bit line contacts of two adjacent bit lines are opposite.
13. The memory of claim 10, wherein the memory further comprises:
and a plurality of word lines formed on the substrate and extending in a second direction, the second direction being perpendicular to the first direction.
14. The memory of claim 10, wherein the bit line contact and the bit line each comprise:
a conductive layer, wherein a portion of the conductive layer located in the bit line contact is in contact with the bit line contact region and is connected to a portion of the conductive layer located in the bit line; and the second isolation side walls are positioned on the side walls of the conducting layer.
15. A semiconductor device, comprising:
a substrate comprising a first contact region and a second contact region;
a plurality of first conductor contacts disposed on the substrate and electrically connected to the first contact regions; a plurality of conductor lines disposed on the substrate, and the first contact regions arranged in series in the same conductor line are electrically connected via the same conductor line, the conductor lines and the first conductor contacts together defining a plurality of first openings on the surface of the substrate, and the combination of the conductor lines and the sidewalls of the first conductor contacts constitute sidewalls of the first openings;
the isolation side walls on the adjacent side walls of the first conductor contact are connected between the two adjacent conductor lines on the side walls of the first opening to form a bottleneck seal, the bottleneck seal and the isolation side walls on the adjacent conductor lines and the side walls of the first conductor contact jointly define a second opening, the second opening is defined in the first opening and defines an area corresponding to the second contact area, and the appearance of the second opening is more rounded relative to that of the first opening; and the number of the first and second groups,
and the second conductor contacts are formed in the second openings and electrically connected with the second contact areas.
16. The semiconductor device of claim 15, wherein the first conductor contact and the conductor line each comprise:
a conductive layer, wherein the conductive layer is in contact with the first contact region at a first location in the first conductor contact and is connected to a second location of the conductive layer in the conductor line; and the number of the first and second groups,
and the conductive isolation side walls are positioned on the side walls of the conductive layers.
17. The semiconductor device according to claim 15, wherein an extending direction of the conductor line is set in accordance with an arrangement of the first contact region and the second contact region, and wherein a plurality of conductor lines are arranged in parallel.
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Publication number Priority date Publication date Assignee Title
US20050009273A1 (en) * 2003-07-11 2005-01-13 Yi-Shing Chang Method and system for forming source regions in memory devices
CN101996950A (en) * 2009-08-11 2011-03-30 海力士半导体有限公司 Semiconductor device and method of fabricating the same
CN102148197A (en) * 2010-02-09 2011-08-10 三星电子株式会社 Method of fabricating semiconductor device
CN105932012A (en) * 2015-02-26 2016-09-07 台湾积体电路制造股份有限公司 Capacitor structure and method of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050009273A1 (en) * 2003-07-11 2005-01-13 Yi-Shing Chang Method and system for forming source regions in memory devices
CN101996950A (en) * 2009-08-11 2011-03-30 海力士半导体有限公司 Semiconductor device and method of fabricating the same
CN102148197A (en) * 2010-02-09 2011-08-10 三星电子株式会社 Method of fabricating semiconductor device
CN105932012A (en) * 2015-02-26 2016-09-07 台湾积体电路制造股份有限公司 Capacitor structure and method of manufacturing the same

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