CN108877635B - Control method of power supply driver, power supply driver and display device - Google Patents
Control method of power supply driver, power supply driver and display device Download PDFInfo
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The embodiment of the invention provides a control method of a power supply driver, the power supply driver and a display device, relates to the technical field of display, and aims to shorten the identification time of a power supply signal and improve the identification efficiency. The control method comprises the following steps: a control circuit of the power supply driver outputs a clock control signal and outputs a binary level signal according to a power supply voltage control signal; a power supply signal output circuit of the power supply driver outputs an actual power supply voltage signal according to the clock control signal and the binary level signal. The control method is used for controlling and outputting the actual power supply voltage signal.
Description
[ technical field ] A method for producing a semiconductor device
The present invention relates to the field of display technologies, and in particular, to a control method for a power driver, and a display device.
[ background of the invention ]
The display device generally includes a first driving circuit, a second driving circuit and a display panel, wherein the first driving circuit is used for controlling the second driving circuit to output a power signal so as to drive the display panel to normally operate.
Based on the current control mode, the first driving circuit outputs a specific pulse signal to the second driving circuit, and the second driving circuit determines the voltage value of the power supply signal required to be output by identifying the number of pulses contained in the pulse signal. However, the number of pulses corresponding to the power signal is large, which results in a long time required for the second driving circuit to spend in the identification process. Moreover, the second driving circuit usually needs to output a plurality of power signals, and at this time, the number of pulses needs to be grouped and identified, which undoubtedly further increases the identification time, resulting in low identification efficiency.
[ summary of the invention ]
In view of this, embodiments of the present invention provide a method for controlling a power driver, and a display device, so as to shorten the recognition time of a power signal and improve the recognition efficiency.
In one aspect, an embodiment of the present invention provides a control method for a power driver, where the control method includes:
a control circuit of the power supply driver outputs a clock control signal and outputs a binary level signal according to a power supply voltage control signal;
and a power supply signal output circuit of the power supply driver outputs an actual power supply voltage signal according to the clock control signal and the binary level signal.
In another aspect, an embodiment of the present invention provides a power driver, where the power driver includes:
the control circuit is used for outputting a clock control signal and outputting a binary level signal according to a power supply voltage control signal;
and the power supply signal output circuit is electrically connected with the control circuit and is used for outputting an actual power supply voltage signal according to the clock control signal and the binary level signal.
In still another aspect, an embodiment of the present invention provides a display device, which includes a display panel and the power driver.
One of the above technical solutions has the following beneficial effects:
by adopting the technical scheme provided by the embodiment of the invention, when a power supply voltage signal which is the same as the power supply voltage control signal needs to be output, the control circuit can directly output a binary level signal containing binary information according to the corresponding relation between the power supply voltage control signal and the binary number, and does not need to output a pulse signal containing dozens of or even hundreds of pulses; correspondingly, the power supply signal output circuit can acquire the actual power supply voltage signal to be output only by identifying the binary number of six bits, ten bits or twelve bits contained in the binary level signal according to the clock control signal and the binary level signal without identifying the number of pulses, so that the identification time is shortened to a great extent, the identification efficiency is improved, and the output time of the actual power supply voltage signal is shortened.
In addition, by adopting the technical scheme provided by the embodiment of the invention, the control circuit only needs to output the binary level signal containing a plurality of binary numbers, and the identification mode of the binary numbers by the power signal output circuit is simpler.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a flow chart of a driving method provided by an embodiment of the present invention;
FIG. 2 is a timing diagram of clock control signals and binary level signals provided by an embodiment of the present invention;
FIG. 3 is another flow chart of a driving method provided by an embodiment of the present invention;
FIG. 4 is another timing diagram of clock control signals and binary level signals provided by an embodiment of the present invention;
FIG. 5 is a timing diagram of a clock control signal and a binary level signal according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a power driver according to an embodiment of the present invention;
fig. 7 is a schematic diagram of another structure of the power driver according to the embodiment of the invention;
fig. 8 is a schematic structural diagram of a power driver according to another embodiment of the invention;
fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present invention.
[ detailed description ] embodiments
In order to better understand the technical scheme of the invention, the following detailed description of the embodiments of the invention is made with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely a relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B, may represent: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that although the terms first and second may be used to describe the start control instructions in the embodiments of the present invention, the start control instructions should not be limited to these terms. These terms are only used to distinguish the activation control instructions from one another. For example, the first start-up control instruction may also be referred to as a second start-up control instruction, and similarly, the second start-up control instruction may also be referred to as a first start-up control instruction without departing from the scope of embodiments of the present invention.
An embodiment of the present invention provides a control method of a power driver, as shown in fig. 1, where fig. 1 is a flowchart of a driving method provided in an embodiment of the present invention, and the control method includes:
step S1: the control circuit of the power driver outputs a clock control signal and outputs a binary level signal according to the power supply voltage control signal.
Step S2: a power supply signal output circuit of the power supply driver outputs an actual power supply voltage signal according to the clock control signal and the binary level signal.
First, it should be noted that, in the prior art, each of the power voltage control signals corresponds to a pulse value, and the embodiment of the present invention converts each of the values into a binary number. For example, assuming that the value of the pulse corresponding to the 4.7V supply voltage control signal is 47, 47 is converted into a binary number of 101111, and it can be seen that the binary number corresponding to the 4.7V supply voltage control signal is 101111. Therefore, the corresponding relation between the power supply voltage control signal and the binary number can be obtained according to the corresponding relation between the existing power supply voltage control signal and the pulse numerical value.
When the control method provided by the embodiment of the present invention is adopted, taking the binary number corresponding to the power voltage control signal as 101111 as an example, and referring to fig. 2, fig. 2 is a timing diagram of the clock control signal and the binary level signal provided by the embodiment of the present invention, the control circuit outputs the clock control signal CLK and the binary level signal BLS containing information of the binary number 101111, wherein one clock cycle of the clock control signal CLK corresponds to one level value in the binary level signal BLS, and one level value corresponds to one bit in the binary number contained in the binary level signal BLS. After the power supply signal output circuit receives the clock control signal CLK and the binary level signal BLS, the binary number contained in the binary level signal BLS is identified according to the clock control signal CLK and the binary level signal BLS, and then the actual power supply voltage signal required to be output is determined.
Therefore, by adopting the control method provided by the embodiment of the invention, when the power supply voltage signal which is the same as the power supply voltage control signal needs to be output, the control circuit can directly output the binary level signal containing the binary information according to the corresponding relation between the power supply voltage control signal and the binary number, and does not need to output the pulse signal containing dozens or even hundreds of pulses; correspondingly, the power supply signal output circuit only needs to identify binary numbers contained in the binary level signals according to the clock control signals and the binary level signals, illustratively, the binary numbers can be six-bit, ten-bit or twelve-bit binary numbers, the actual power supply voltage signals required to be output can be obtained, the number of pulses does not need to be identified, therefore, the identification time is shortened to a great extent, the identification efficiency is improved, and the output time of the actual power supply voltage signals is shortened.
In addition, by adopting the control method provided by the embodiment of the invention, the control circuit only needs to output the binary level signal containing a plurality of binary numbers, and the identification mode of the power signal output circuit on the binary numbers is simpler, compared with the control mode of identifying the number of pulses in the prior art, the hardware structure of the control circuit and the power signal output circuit can be simplified, and the realizability of the control circuit and the power signal output circuit can be improved.
Optionally, as shown in fig. 3, fig. 3 is another flowchart of the driving method according to the embodiment of the present invention, and step S1 may specifically include:
step S11: a clock signal output module of the control circuit outputs a clock control signal.
Step S12: and a binary signal generation module of the control circuit acquires a corresponding binary number according to the power supply voltage control signal and generates a binary level signal containing binary number information according to the binary bit number information corresponding to the power supply voltage control signal.
The "binary digit information" refers to information including the digit of the binary digit corresponding to the power supply voltage control signal, for example, the binary digit corresponding to the 4.7V power supply voltage control signal is 101111, and the digit information included in the binary digit information is six digits.
Step S13: a binary signal output module of the control circuit outputs the generated binary level signal.
Because the embodiment of the invention identifies the actual power supply voltage signal through the corresponding relation of the power supply voltage control signal, the binary number and the actual power supply voltage signal, the binary level signal generated by the binary signal generating module only needs to contain the pulse corresponding to the binary information of several bits, and the pulse signal containing dozens of or even hundreds of pulses does not need to be output, thereby simplifying the signal output and shortening the identification time of the power supply signal output circuit.
Optionally, referring to fig. 3 again, step S2 may specifically include:
step S21: a binary number identification module of the power supply signal output circuit acquires a binary number contained in the binary level signal according to binary digit information corresponding to the clock control signal, the binary level signal and the power supply voltage control signal; when the bit number information contained in the binary bit number information is n bits, the level value of the binary level signal corresponding to the mth clock period of the clock control signal is the nth- (m-1) bit in the binary number.
Here, the "level value of the binary level signal corresponding to the mth clock cycle of the clock control signal is the nth- (m-1) bit in the binary number" may include two cases. The following description will be given taking an example in which binary information included in the binary level signal is 101111.
In the first case: referring to fig. 2 again, the high and low levels output by the binary level signal BLS correspond to the forward direction order of 101111, at this time, when the power signal output circuit recognizes binary information, the level value of the binary level signal corresponding to the 1 st clock cycle of the clock control signal is the most significant bit 1 in the binary number, the level value of the binary level signal corresponding to the 2 nd clock cycle of the clock control signal is the second most significant bit 0 in the binary number, and so on, the level value of the binary level signal corresponding to the 6 th clock cycle of the clock control signal is the least significant bit 1 in the binary number.
In the second case: as shown in fig. 4, fig. 4 is another timing diagram of the clock control signal and the binary level signal provided by the embodiment of the present invention, where the high and low levels output by the binary level signal BLS correspond to a reverse order of 101111, at this time, when the power signal output circuit recognizes binary information, the level value of the binary level signal corresponding to the 1 st clock cycle of the clock control signal is the least significant bit 1 in the binary number, the level value of the binary level signal corresponding to the 2 nd clock cycle of the clock control signal is the second least significant bit 1 in the binary number, and so on, the level value of the binary level signal corresponding to the 5 th clock cycle of the clock control signal is the second most significant bit 0 in the binary number, and the level value of the binary level signal corresponding to the 6 th clock cycle of the clock control signal is the most significant bit 1 in the binary number.
Step S22: and a power supply signal output module of the power supply signal output circuit outputs a power supply voltage signal corresponding to the binary number according to the binary number.
When the binary number identification module receives the clock control signal and the binary level signal, the binary number contained in the binary level signal can be accurately identified according to the binary bit number information. For example, if the binary digit information includes 6 digits, the binary digit recognition module may stop recognizing after recognizing the 6 th clock cycle of the clock control signal, and if the recognition is continued subsequently, the digit of the recognized binary digit may not match the digit of the original binary digit, resulting in a recognition error.
Further, when the power signal output circuit needs to output a plurality of actual power voltage signals, that is, the power voltage control signal includes a plurality of sub-power control signals, at this time, step S12 may specifically include: the binary signal generation module acquires binary numbers corresponding to the plurality of sub-power control signals according to the plurality of sub-power control signals, and generates a binary level signal containing a plurality of binary information according to binary bit number information corresponding to each sub-power control signal and binary bit information corresponding to each sub-power control signal.
The binary position information refers to the information of the binary number corresponding to the plurality of sub power control signals in the sequential order corresponding to the subsequently generated binary level signals.
For example, the power signal output circuit needs to output three power voltage signals, namely a negative power voltage signal (PVEE), a positive power voltage signal (PVDD), and an analog power voltage signal (AVDD), assuming that the binary number corresponding to the sub-negative power control signal is 100111, the corresponding bit information is six bits, the corresponding bit information is the first bit, the binary number corresponding to the sub-positive power control signal is 111001, the corresponding bit information is six bits, the corresponding bit information is the second bit, the binary number corresponding to the sub-analog power control signal is 1010110001, the corresponding bit information is ten bits, and the corresponding bit information is the third bit. At this time, the binary level signal generated by the binary signal generating module according to the binary number, the binary digit information and the binary position information is as shown in fig. 5, and fig. 5 is still another timing diagram of the clock control signal and the binary level signal provided by the embodiment of the invention.
When the power supply signal output circuit needs to output a plurality of actual power supply voltage signals, the binary signal generation module can accurately and orderly arrange the binary information corresponding to the plurality of sub-power supply control signals in the generated binary level signal according to the binary number, the binary bit number information and the binary position information corresponding to each sub-power supply control signal, and further the binary identification module can subsequently and accurately identify.
Correspondingly, when the power-supply-voltage control signal includes a plurality of sub-power-supply control signals, that is, the binary level signal includes a plurality of binary information, step S21 may specifically include: the binary number identification module identifies a plurality of binary numbers contained in the binary level signal according to the clock control signal, the binary level signal, the binary bit number information corresponding to each sub-power control signal and the binary bit information corresponding to each sub-power control signal.
Taking the timing diagram shown in fig. 5 as an example, when the binary number identification module receives the clock control signal and the binary level signal, the binary number information and the binary position information are combined to know that the first 6-bit binary number corresponds to the negative power voltage signal (PVEE), the middle 6-bit binary number corresponds to the positive power voltage signal (PVDD), and the last 10-bit binary number corresponds to the analog power voltage signal (AVDD). Therefore, by adopting the mode, the binary number identification module can accurately identify a plurality of binary numbers contained in the binary level signal according to the binary digit information and the binary position information.
Optionally, when the display panel needs to display a picture, the control method provided in the embodiment of the present invention may further include: the starting circuit of the power supply driver generates and sends a first starting control instruction to the control circuit, the control circuit outputs a clock control signal and a binary level signal under the action of the first starting control instruction, and the control power supply signal output circuit outputs a positive power supply voltage signal and a negative power supply voltage signal for driving picture display so as to enable the display panel to normally display.
Optionally, when the analog power supply voltage signal needs to be output, the control method provided in the embodiment of the present invention may further include: the starting circuit of the power supply driver generates and sends a second starting control instruction to the control circuit, the control circuit outputs a clock control signal, a binary level signal and an enabling signal under the action of the second starting control instruction, and then the power supply signal output circuit outputs an analog power supply voltage signal under the action of the enabling signal.
Fig. 6 is a schematic structural diagram of the power supply driver provided in the embodiment of the present invention, where the power supply driver includes a control circuit 1 and a power supply signal output circuit 2. The control circuit 1 is used for outputting a clock control signal and outputting a binary level signal according to a power supply voltage control signal; the power signal output circuit 2 is electrically connected to the control circuit 1, and the power signal output circuit 2 is configured to output an actual power voltage signal according to the clock control signal and the binary level signal.
The principle of the control method of the power driver has been described in detail in the above embodiments, and is not described herein again.
By adopting the power supply driver provided by the embodiment of the invention, when the power supply voltage signal which is the same as the power supply voltage control signal needs to be output, the control circuit 1 can directly output the binary level signal containing the binary information according to the corresponding relation between the power supply voltage control signal and the binary number, and correspondingly, the power supply signal output circuit 2 only needs to identify the binary numbers contained in the binary level signal according to the clock control signal and the binary level signal, so that the actual power supply voltage signal which needs to be output can be obtained. Compared with the prior art, the method has the advantages that the identification time is shortened to a great extent, the identification efficiency is improved, and the output time of the actual power supply voltage signal is shortened.
On the other hand, with the power supply driver provided by the embodiment of the present invention, the control circuit 1 only needs to output a binary level signal containing several binary digits, and the identification manner of the binary digits by the power supply signal output circuit 2 is also simple, so that the hardware structures of the control circuit 1 and the power supply signal output circuit 2 can be simplified, and the realizability thereof can be improved.
Alternatively, as shown in fig. 7, fig. 7 is another schematic structural diagram of the power driver provided in the embodiment of the present invention, and the control circuit 1 may include a clock signal output module 11, a binary signal generation module 12, and a binary signal output module 13. The clock signal output module 11 is electrically connected with the power signal output circuit 2, and the clock signal output module 11 is used for outputting a clock control signal; the binary signal generating module 12 is configured to obtain a corresponding binary number according to the power supply voltage control signal, and generate a binary level signal including binary number information according to binary bit number information corresponding to the power supply voltage control signal; the binary signal output module 13 is electrically connected to the binary signal generating module 12, and the binary signal output module 13 is configured to output the generated binary level signal.
Because the binary level signal generated by the binary signal generating module 12 only needs to include pulses corresponding to binary information of several bits, and does not need to output pulse signals including dozens or even hundreds of pulses, the signal output is simplified, and the identification time of the power signal output circuit 2 is shortened.
Alternatively, referring to fig. 7 again, the power signal output circuit 2 may include a binary number recognition module 21 and a power signal output module 22. The binary number identification module 21 is electrically connected with the control circuit 1, and the binary number identification module 21 is used for identifying the binary number contained in the binary level signal according to the binary digit information corresponding to the clock control signal, the binary level signal and the power supply voltage control signal; when the binary digit information contains digit information of n digits, the level value of a binary level signal corresponding to the mth clock period of the clock control signal is the nth- (m-1) digit in the binary digit; the power signal output module 22 is electrically connected to the binary number identification module 21, and the power signal output module 22 is configured to output a power voltage signal corresponding to the binary number according to the binary number.
When the binary number identification module 21 receives the clock control signal and the binary level signal, the binary number included in the binary level signal can be accurately identified according to the binary bit number information. For example, if the binary bit number information includes 6 bits, the binary bit number identification module 21 may stop the identification after identifying the 6 th clock period of the clock control signal.
In addition, as shown in fig. 8, fig. 8 is a schematic structural diagram of a power supply driver according to an embodiment of the present invention, and the power supply driver may further include a starting circuit 3, where the starting circuit 3 is electrically connected to the control circuit 1. When the display panel needs to display the picture, the starting circuit 3 generates a first starting control instruction, so that the control circuit 1 controls the power signal output circuit 2 to output a positive power voltage signal and a negative power voltage signal for driving the picture to display. When the analog power supply voltage signal needs to be output, the starting circuit 3 generates a second starting control instruction, so that the control circuit 1 outputs an enable signal, and the power supply signal output circuit 2 outputs the analog power supply voltage signal under the action of the enable signal.
As shown in fig. 9, fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present invention, where the display device includes a display panel 100 and the power driver 200. The specific structure and control method of the power driver 200 have been described in detail in the above embodiments, and are not described herein again. Of course, the display device shown in fig. 9 is only a schematic illustration, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, or a television.
Because the display device provided by the embodiment of the invention comprises the power supply driver, the display device can shorten the identification time required by a power supply signal output circuit in the power supply driver and improve the identification efficiency on one hand, and can simplify the hardware structure of the power supply driver and improve the realizability on the other hand.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A control method of a power driver, the control method comprising:
a control circuit of the power supply driver outputs a clock control signal and outputs a binary level signal according to a power supply voltage control signal;
a power supply signal output circuit of the power supply driver outputs an actual power supply voltage signal according to the clock control signal and the binary level signal;
the power signal output circuit outputting an actual power voltage signal according to the clock control signal and the binary level signal includes:
a binary number identification module of the power supply signal output circuit acquires a binary number contained in the binary level signal according to binary bit number information corresponding to the clock control signal, the binary level signal and the power supply voltage control signal; when the binary bit number information contains n bits of bit number information, the level value of the binary level signal corresponding to the mth clock cycle of the clock control signal is the nth- (m-1) bit in the binary number;
and a power supply signal output module of the power supply signal output circuit outputs a power supply voltage signal corresponding to the binary number according to the binary number.
2. The control method of the power driver as claimed in claim 1, wherein the controlling circuit outputs a clock control signal and outputs a binary level signal according to the power supply voltage control signal comprises:
a clock signal output module of the control circuit outputs a clock control signal;
a binary signal generation module of the control circuit acquires a corresponding binary number according to the power supply voltage control signal and generates a binary level signal containing binary number information according to binary digit information corresponding to the power supply voltage control signal;
and a binary signal output module of the control circuit outputs the generated binary level signal.
3. The control method of the power driver according to claim 2, wherein the power supply voltage control signal includes a plurality of sub power supply control signals;
the binary signal generation module acquires a corresponding binary number according to the power supply voltage control signal, and generates a binary level signal containing binary number information according to binary bit number information corresponding to the power supply voltage control signal, wherein the binary level signal comprises:
the binary signal generation module acquires binary numbers corresponding to the sub-power control signals according to the sub-power control signals, and generates binary level signals containing a plurality of binary number information according to binary number information corresponding to the sub-power control signals and binary position information corresponding to the sub-power control signals.
4. The control method of the power driver as claimed in claim 1, wherein the power voltage control signal comprises a plurality of sub-power control signals, and the binary level signal comprises a plurality of binary information;
the binary number identification module identifies binary numbers contained in the binary level signal according to binary bit number information corresponding to the clock control signal, the binary level signal and the power supply voltage control signal, and comprises the following steps:
the binary number identification module identifies a plurality of binary numbers contained in the binary level signal according to the clock control signal, the binary level signal, binary digit information corresponding to each sub-power control signal, and binary digit information corresponding to each sub-power control signal.
5. The control method of a power driver according to claim 1, further comprising:
and the starting circuit of the power supply driver generates a first starting control instruction, so that the control circuit controls the power supply signal output circuit to output a positive power supply voltage signal and a negative power supply voltage signal for driving picture display.
6. The control method of a power driver according to claim 1, further comprising:
and the starting circuit of the power supply driver generates a second starting control instruction to enable the control circuit to output an enabling signal, and the power supply signal output circuit outputs an analog power supply voltage signal under the action of the enabling signal.
7. A power driver, comprising:
the control circuit is used for outputting a clock control signal and outputting a binary level signal according to a power supply voltage control signal;
the power supply signal output circuit is electrically connected with the control circuit and is used for outputting an actual power supply voltage signal according to the clock control signal and the binary level signal;
the power supply signal output circuit includes:
the binary number identification module is electrically connected with the control circuit and is used for identifying the binary number contained in the binary level signal according to the binary bit number information corresponding to the clock control signal, the binary level signal and the power supply voltage control signal; when the binary bit number information contains n bits of bit number information, the level value of the binary level signal corresponding to the mth clock cycle of the clock control signal is the nth- (m-1) bit in the binary number;
and the power supply signal output module is electrically connected with the binary number identification module and used for outputting a power supply voltage signal corresponding to the binary number according to the binary number.
8. The power driver of claim 7, wherein the control circuit comprises:
the clock signal output module is electrically connected with the power signal output circuit and is used for outputting a clock control signal;
the binary signal generating module is used for acquiring a corresponding binary number according to the power supply voltage control signal and generating a binary level signal containing binary number information according to binary digit information corresponding to the power supply voltage control signal;
and the binary signal output module is electrically connected with the binary signal generation module and is used for outputting the generated binary level signal.
9. The power driver of claim 7, further comprising:
the starting circuit is electrically connected with the control circuit and is used for generating a first starting control instruction so that the control circuit controls the power signal output circuit to output a positive power voltage signal and a negative power voltage signal for driving picture display; and generating a second starting control instruction to enable the control circuit to output an enable signal, and enabling the power supply signal output circuit to output an analog power supply voltage signal under the action of the enable signal.
10. A display device comprising a display panel and the power driver as claimed in any one of claims 7 to 9.
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| CN108877635A (en) | 2018-11-23 |
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