CN117612486A - Display driving circuit, display driving method and display device - Google Patents

Abstract

The present disclosure relates to a display driving circuit, a display driving method, and a display device. The display driving circuit includes: a synchronization control circuit and a clock gating circuit. The synchronization control circuit is configured to: receiving a data effective synchronous signal, a line synchronous signal and a field synchronous signal, and generating a clock enabling signal according to the data effective synchronous signal, the line synchronous signal and the field synchronous signal; wherein the clock enable signal comprises: a clock sleep signal in a signal blanking period, and a clock active signal in a non-signal blanking period. The clock gating circuit is connected with the synchronous control circuit and is configured to: a clock signal and a clock enable signal are received to control the clock signal to sleep in response to the clock sleep signal and to control the clock signal to operate in response to the clock valid signal. The present disclosure is easy to further reduce power consumption of the display device.

Description

Display driving circuit, display driving method and display device

Technical Field

The disclosure relates to the technical field of display, and in particular relates to a display driving circuit, a display driving method and a display device.

Background

Currently, organic Light-Emitting Diode (OLED) display devices are now widely used in portable devices. In addition, the power consumption index of the OLED display device is one of the most important parameters, and directly affects the power consumption rate of the portable device. However, in the related art, power consumption optimization of the OLED display device is generally achieved by reducing power consumption of an analog circuit, for example, power consumption of a pixel driving circuit, power consumption of a digital-to-analog conversion (Digital to analog converter, abbreviated as DAC) chip, power consumption of a negative voltage power supply circuit, or the like may be optimized, but there is still a technical problem that power consumption of the OLED display device is high.

Disclosure of Invention

Based on this, the embodiment of the disclosure provides a display driving circuit, a display driving method and a display device, which are easy to further reduce the power consumption of the display device.

To achieve the above object, in a first aspect, some embodiments of the present disclosure provide a display driving circuit. The display driving circuit includes: a synchronization control circuit and a clock gating circuit. The synchronization control circuit is configured to: receiving a data effective synchronous signal, a line synchronous signal and a field synchronous signal, and generating a clock enabling signal according to the data effective synchronous signal, the line synchronous signal and the field synchronous signal; wherein the clock enable signal comprises: a clock sleep signal in a signal blanking period, and a clock active signal in a non-signal blanking period. The clock gating circuit is connected with the synchronous control circuit and is configured to: a clock signal and a clock enable signal are received to control the clock signal to sleep in response to the clock sleep signal and to control the clock signal to operate in response to the clock valid signal.

In some embodiments, the synchronization control circuit includes: the system comprises an enabling control module, a zero clearing control module and a blanking counting circuit. The enable control module is configured to: a row synchronization signal and a pixel count signal are received, and a count enable signal is generated. The clear control module is configured to: and receiving the data effective synchronous signal, the field synchronous signal and the line synchronous signal, and generating a count zero clearing signal according to the data effective synchronous signal, the field synchronous signal and the line synchronous signal. The blanking counting circuit is respectively connected with the enabling control module, the zero clearing control module and the clock gating circuit and is configured to: the clock signal, the count enable signal, and the count clear signal are received, a pixel count signal is generated from the clock signal, the count enable signal, and the count clear signal, and the clock enable signal is generated based on the pixel count signal.

In some embodiments, the enabling control module includes: smaller than the comparator and the first or gate. The first input end smaller than the comparator is connected with the blanking counting circuit and is used for receiving the pixel counting signal. The second input terminal smaller than the comparator is used for inputting the total pixel number of one row of pixels. The first input end of the first OR gate is connected with the output end of the comparator. The second input terminal of the first or gate is used for receiving the line synchronization signal. The output end of the first OR gate is connected with the enabling input end of the blanking counting circuit and is used for outputting a counting enabling signal to the blanking counting circuit.

In some embodiments, the zeroing control module includes: a second or gate, an inverter, and an and gate. The first input end of the second or gate is used for receiving the data valid synchronous signal. The second input of the second or gate is for receiving the field sync signal. The input terminal of the inverter is used for receiving the line synchronization signal. The first input end of the AND gate is connected with the output end of the second OR gate. The second input of the AND gate is connected to the output of the inverter. The output end of the AND gate is connected with the zero clearing input end of the blanking counting circuit and is used for outputting a counting zero clearing signal to the blanking counting circuit.

In some embodiments, the blanking counting circuit includes a counter and a comparator or less. The enable input end of the counter is connected with the enable control module and is used for receiving a counting enable signal. The zero clearing input end of the counter is connected with the zero clearing control module and is used for receiving a counting zero clearing signal. The clock input of the counter is used for receiving a clock signal. The output end of the counter is used for outputting a pixel counting signal. The first input end smaller than or equal to the comparator is connected with the output end of the counter. The second input end smaller than or equal to the comparator is used for receiving the number of pixel points corresponding to the effective image width. The output end of the comparator is connected with the clock gating circuit and used for outputting a clock enabling signal to the clock gating circuit.

In a second aspect, the present disclosure also provides a display driving method according to some embodiments, the display driving method including:

a data valid synchronization signal, a row synchronization signal, and a field synchronization signal are received.

Generating a clock enable signal according to the data valid synchronous signal, the line synchronous signal and the field synchronous signal; wherein the clock enable signal comprises: a clock sleep signal in a signal blanking period, and a clock active signal in a non-signal blanking period.

A clock signal is received and is controlled to sleep in response to the clock sleep signal and is controlled to operate in response to the clock valid signal.

In some embodiments, generating the clock enable signal from the data valid sync signal, the row sync signal, and the field sync signal includes the steps of:

and generating a counting enabling signal according to the line synchronizing signal and the pixel counting signal fed back in real time.

And generating a count zero clearing signal according to the data valid synchronous signal, the field synchronous signal and the line synchronous signal.

A pixel count signal is generated from the clock signal, the count enable signal, and the count clear signal, and the clock enable signal is generated based on the pixel count signal.

In some embodiments, generating the count enable signal according to the row synchronization signal and the pixel count signal fed back in real time includes the steps of:

the total pixel number of a row of pixels is obtained.

And judging whether the pixel counting signal is smaller than the total pixel number or not, so as to output a first level when the pixel counting signal is smaller than the total pixel number and output a second level when the pixel counting signal is larger than or equal to the total pixel number.

And performing OR operation on the row synchronous signal and the first level or the second level to obtain a first OR logic signal as a counting enabling signal.

In some embodiments, the count zero signal is generated from a data valid sync signal, a field sync signal, and a row sync signal, comprising the steps of:

and performing OR operation on the data valid synchronous signal and the field synchronous signal to obtain a second OR logic signal.

And carrying out inversion operation on the line synchronous signals to obtain inversion signals.

And performing AND operation on the second OR logic signal and the inversion signal to obtain an AND logic signal as a count zero clearing signal.

In a third aspect, the present disclosure also provides a display device according to some embodiments, including a display driving circuit according to the first aspect of the embodiments of the present disclosure.

Embodiments of the present disclosure may/have at least the following advantages:

in the embodiment of the disclosure, a synchronous control circuit and a clock gating circuit are arranged in a display driving circuit, a clock enabling signal can be generated by the synchronous control circuit based on a data valid synchronous signal, a row synchronous signal and a field synchronous signal, and the clock gating circuit is used for: the clock signal dormancy is controlled by responding to the clock dormancy signal in the clock enable signal in the signal blanking period, and the clock signal work is controlled by responding to the clock valid signal in the clock enable signal in the non-signal blanking period. Thus, the display driving circuit and the display driving method provided by the embodiment of the disclosure can control the clock signal to sleep in the signal blanking period, and are easy to further reduce the power consumption of the display device.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present disclosure, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to the drawings without inventive effort to those of ordinary skill in the art.

FIG. 1 is a block diagram of a display driver circuit provided in some embodiments;

FIG. 2 is a block diagram of another display driver circuit provided in some embodiments;

FIG. 3 is a block diagram of yet another display driver circuit provided in some embodiments;

FIG. 4 is a flow chart of a display driving method provided in some embodiments;

FIG. 5 is a flow chart of a step S200 provided in some embodiments;

FIG. 6 is a flow chart of a step S210 provided in some embodiments;

FIG. 7 is a flow chart of a step S220 provided in some embodiments;

FIG. 8 is a timing diagram of an original clock signal, a data valid sync signal, a field sync signal, a line sync signal, and a video data signal during a line blanking period provided in some embodiments;

FIG. 9 is a timing diagram of an original clock signal, a data valid sync signal, a field sync signal, a row sync signal, and a pixel count signal during a line blanking period provided in some embodiments;

FIG. 10 is a timing diagram of the original clock signal, the data valid sync signal, the field sync signal, the row sync signal, and the pixel count signal during a vertical blanking period provided in some embodiments;

FIG. 11 is a timing diagram of clock signals, data valid sync signals, field sync signals, row sync signals, and pixel count signals output by a clock gating circuit during a row blanking period provided in some embodiments;

FIG. 12 is a timing diagram of an original clock signal, a data valid sync signal, a field sync signal, a row sync signal, a count clear signal, a count enable signal, a pixel count signal, a clock enable signal, and a clock signal output by a clock gating circuit during a row blanking period provided in some embodiments;

fig. 13 is a timing diagram of clock signals, data valid sync signals, field sync signals, row sync signals, and pixel count signals output by a clock gating circuit during the row and vertical blanking periods provided in some embodiments.

Reference numerals illustrate:

100-display driving circuit, 1-synchronous control circuit, 2-clock gating circuit, 11-enabling control module, 111-less comparator, 112-first OR gate, 12-zero clearing control module, 121-second OR gate, 122-inverter, 123-AND gate, 13-blanking counting circuit, 131-counter, 132-less than or equal to comparator.

Detailed Description

In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.

The terms "first," "second," and the like, as used in embodiments of the present disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

The display driving circuit is used for controlling the display of an Organic Light Emitting Diode (OLED) display device, and may transmit image data to each row of pixels line by line in a progressive scanning driving manner, for example, the pixels may be individually gated from left to right and simultaneously row by row from top to bottom, so as to display an image.

Referring to fig. 1, 2 and 3, some embodiments of the present disclosure provide a display driving circuit 100. The display driving circuit 100 includes: a synchronization control circuit 1 and a clock gating circuit 2. The synchronization control circuit 1 is configured to: receiving a data valid synchronization signal endi, a row synchronization signal hsy and a field synchronization signal vsy, and generating a clock enable signal clk-en according to the data valid synchronization signal endi, the row synchronization signal hsy and the field synchronization signal vsy; wherein the clock enable signal clk-en comprises: a clock sleep signal in a signal blanking period, and a clock active signal in a non-signal blanking period. The clock gating circuit 2 is connected to the synchronization control circuit 1 and is configured to: the clock signal clki and the clock enable signal clk-en are received to control the clock signal clki to sleep in response to the clock sleep signal and to control the clock signal clki to operate in response to the clock enable signal.

Illustratively, controlling clock signal sleep in response to a clock sleep signal may be represented as: during the signal blanking period, the output of the clock signal is stopped or the clock signal generator is turned off in response to the clock sleep signal in the clock enable signal clk-en. Controlling the operation of the clock signal in response to the clock valid signal may be represented as: during the non-signal blanking period, the clock signal is continuously output or the clock signal generator is turned on or kept in an operating state in response to the clock valid signal in the clock enable signal clk-en.

The signal blanking period includes, for example, a line blanking period and/or a vertical blanking period.

For example, the clock signal clk output or stopped from being output by the clock gating circuit 2 may be the clock signal clki originally input, or may be the clock signal clk output after the clock gating circuit 2 converts the clock signal clki originally input. The embodiments of the present disclosure are not limited in this regard. Accordingly, the internal structure of the clock gating circuit 2 may be matched to the demand selection setting.

In the embodiment of the present disclosure, the synchronization control circuit 1 and the clock gating circuit 2 are disposed in the display driving circuit 100, and the clock enable signal clk-en can be generated by the synchronization control circuit 1 based on the data valid synchronization signal endi, the row synchronization signal hsy, and the field synchronization signal vsy, and by the clock gating circuit 2: the clock signal clki is controlled to sleep in response to a clock sleep signal in the clock enable signal clk-en during the signal blanking period, and the clock signal clki is controlled to operate in response to a clock active signal in the clock enable signal clk-en during the non-signal blanking period. In this way, the display driving circuit 100 provided in the embodiment of the present disclosure may control the clock signal clki to sleep in the signal blanking period, which is easy to further reduce the power consumption of the display device.

In some embodiments, please understand in conjunction with fig. 2 and 3, the synchronization control circuit 1 includes: an enable control module 11, a clear control module 12 and a blanking count circuit 13. The enabling control module 11 is configured to: the row synchronization signal hsy and the pixel count signal hcnt are received to generate the count enable signal hcnt-en. The clear control module 12 is configured to: the data valid synchronization signal endi, the field synchronization signal vsy, and the line synchronization signal hsy are received, and the count clear signal hcnt-clr is generated from the data valid synchronization signal endi, the field synchronization signal vsy, and the line synchronization signal hsy. The blanking counting circuit 13 is connected to the enable control module 11, the clear control module 12, and the clock gating circuit 2, and configured to: the clock signal clki, the count enable signal hcnt-en and the count clear signal hcnt-clr are received, the pixel count signal hcnt is generated according to the clock signal clki, the count enable signal hcnt-en and the count clear signal hcnt-clr, and the clock enable signal clk-en is generated based on the pixel count signal hcnt.

In some embodiments, referring to fig. 3, the blanking counting circuit 13 includes a counter 131 and a comparator 132. The enable control module 11 includes: smaller than the comparator 111 and the first or gate 112. The first input terminal smaller than the comparator 111 is connected to the blanking counting circuit 13, for example, to the output terminal of the counter 131, for receiving the pixel count signal hcnt. A second input terminal smaller than the comparator 111 is used for inputting the total pixel count htotal of a row of pixels. A first input of the first or gate 112 is connected to an output of the comparator 111. A second input of the first or gate 112 is for receiving the row synchronization signal hsy. The output of the first or gate 112 is connected to an enable input EN of the blanking counting circuit 13, for example to an enable input EN of the counter 131, for outputting a count enable signal hcnt-EN to the blanking counting circuit 13.

In some embodiments, referring still to FIG. 3, the zeroing control module 12 includes: a second or gate 121, an inverter 122, and an and gate 123. Wherein a first input of the second or gate 121 is for receiving the data valid synchronization signal endi. A second input of the second or gate 121 is for receiving the field sync signal vsy. An input of the inverter 122 is for receiving the row synchronization signal hsy. A first input of the and gate 123 is connected to an output of the second or gate 121. A second input of and gate 123 is connected to the output of inverter 122. The output terminal of the and gate 123 is connected to the clear input terminal CLR of the blanking counter circuit 13, for example, to the clear input terminal CLR of the counter 131, and is configured to output a count clear signal hcnt-CLR to the blanking counter circuit 13.

In some embodiments, referring to fig. 3, the blanking counting circuit 13 includes a counter 131 and a comparator 132. The enable input EN of the counter 131 is connected to the output of the enable control module 11, for example, the first or gate 112, for receiving the count enable signal hcnt-EN. The clear input CLR of the counter 131 is connected to the output of the clear control module 12, e.g. the and gate 123, for receiving the count clear signal hcnt-CLR. The clock input CK of the counter 131 is used to receive the clock signal clki. The output terminal Q of the counter 131 is used for outputting the pixel count signal hcnt. A first input terminal of the comparator 132 is connected to the output terminal Q of the counter 131. The second input terminal of the comparator 132 is configured to receive the number of pixels corresponding to the effective image width img-width. The output terminal of the comparator 132 is connected to the clock gating circuit 2 for outputting the clock enable signal clk-en to the clock gating circuit 2.

Illustratively, the counter 131 is a horizontal counter, i.e.: the pixel points of each row of pixels may be counted in the horizontal row direction.

Some embodiments of the present disclosure further provide a display driving method, which may be applied to the display driving circuit provided in some embodiments. The display driving circuit can achieve the technical effects that the display driving method is also provided, and the description is omitted herein.

Referring to FIG. 4, the display driving method includes the following steps S100 to S300.

S100, receiving a data valid synchronous signal, a line synchronous signal and a field synchronous signal.

S200, generating a clock enabling signal according to the data effective synchronous signal, the line synchronous signal and the field synchronous signal; wherein the clock enable signal comprises: a clock sleep signal in a signal blanking period, and a clock active signal in a non-signal blanking period.

S300, receiving a clock signal, controlling the clock signal to sleep in response to the clock sleep signal, and controlling the clock signal to work in response to the clock valid signal.

In some embodiments, referring to fig. 5, in step S200, a clock enable signal is generated according to the data valid synchronization signal, the row synchronization signal and the field synchronization signal, including the following steps S210 to S230.

S210, generating a counting enabling signal according to the line synchronizing signal and the pixel counting signal fed back in real time.

S220, generating a count zero clearing signal according to the data valid synchronous signal, the field synchronous signal and the line synchronous signal.

S230, generating a pixel count signal from the clock signal, the count enable signal, and the count clear signal, and generating the clock enable signal based on the pixel count signal.

In some embodiments, referring to fig. 6, in step S210, a count enable signal is generated according to a row synchronization signal and a pixel count signal fed back in real time, including the following steps S211 to S213.

S211, obtaining the total pixel number of one row of pixels.

S212, judging whether the pixel count signal is smaller than the total pixel count number, outputting a first level when the pixel count signal is smaller than the total pixel count number, and outputting a second level when the pixel count signal is greater than or equal to the total pixel count number.

S213, OR operation is carried out on the row synchronous signal and the first level or the second level, and the first or logic signal is obtained as a count enable signal.

In some embodiments, referring to fig. 7, in step S220, a count zero signal is generated according to the data valid synchronization signal, the field synchronization signal and the line synchronization signal, including the following steps S221 to S223.

S221, performing OR operation on the data effective synchronous signal and the field synchronous signal to obtain a second OR logic signal.

S222, performing inversion operation on the line synchronization signal to obtain an inversion signal.

S223, performing AND operation on the second OR logic signal and the inversion signal to obtain an AND logic signal as a count zero clearing signal.

It should be understood that, although the steps in the flowcharts of fig. 4 to 7 are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in fig. 4 to 7 may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed in turn or alternately with at least a portion of the steps or stages in other steps or other steps.

In order to more clearly illustrate the display driving circuit and the display driving method provided in the embodiments of the present disclosure, in the following embodiments, the display driving circuit 100 shown in fig. 3 is taken as an example, and some display driving methods that can be implemented are described in detail. Before describing the display driving method provided by the embodiments of the present disclosure, reference is made to fig. 8 to 10 to introduce video driving signals of a display device and some related concepts related to the embodiments of the present disclosure.

For example, referring to fig. 8 to 10, the video driving signals include, for example, an original clock signal clki, a data valid synchronization signal endi, a field synchronization signal vsy, a line synchronization signal hsy, and a video data signal data; wherein, assume that: the data valid synchronization signal endi is valid at a high level, and the valid width is fixed three clock cycles; the field synchronizing signal vsy is active high and has an active width of two clock cycles; the row sync signal hsy is active high and has an active width of two clock cycles that is fixed; the first clock period after the high level in the line synchronization signal hsy is used to display the first valid video data signal data of the corresponding line, for example, the valid video data signal D1. And, the effective image width img-width may be represented by the number of pixel points corresponding to the display video data signal data, the effective image height img-height may be represented by the number of pixel lines corresponding to the display video data signal data, and the total number of pixel points corresponding to any line of pixels is represented by htotal.

In some embodiments below, the number of pixels corresponding to the effective image width img-width is 1024, the number of pixels corresponding to the effective image height img-height is 768, and the total number of pixels htotal corresponding to one row of pixels is 1400, but it is understood that the present invention is not limited thereto.

Furthermore, it is understood that the OLED display device does not need to collect video data signals during the horizontal blanking period and the vertical blanking period, i.e.: in the line blanking period and the vertical blanking period, the clock signal clki, the DATA valid synchronization signal endi, the field synchronization signal vsy, the line synchronization signal hsy, and the video DATA signal DATA are all inactive signals.

As will be appreciated in conjunction with fig. 3 and 9, the counter 131 can be used to count the pixels of each line of display video data, and the counting rule of the counter 131 may be: the counter 131 starts to count up when the line synchronization signal hsy rises, and stops counting when the pixel count signal hcnt (i.e., the count value) is equal to the total pixel count htotal corresponding to one line of pixels; the counter 131 clears when the data valid synchronization signal endi rises to the rising edge of the row synchronization signal hsy, and the counter is used to identify the row blanking period of the OLED video driving signal.

As will be understood in conjunction with fig. 3 and 10, in the vertical blanking period, since the line synchronization signal hsy is a low-level inactive signal, the pixel count signal hcnt (i.e., the count value) of the counter 131 will remain htotal.

From the above, as will be understood with reference to fig. 3, 11 and 12, the count enable signal hcnt-en may be at a high level when the pixel count signal hcnt (i.e. the count value) starts counting until the number of pixels corresponding to the effective image width img-width is equal to the number of pixels, and at a low level when the pixel count signal hcnt (i.e. the count value) is 0 or greater than the number of pixels corresponding to the effective image width img-width and less than or equal to the total number of pixels htotal corresponding to a row of pixels. The count zero signal hcnt-clr may be high between the rising edge of the data valid synchronization signal endi to the rising edge of the row synchronization signal hsy. Accordingly, the clock enable signal clk-en may be low during the line blanking period and high when the rising edge of the data valid synchronization signal endi reaches the valid image width img-width; the low level corresponds to a clock dormancy signal to control the clock gating circuit 2 to be turned off; the high level corresponds to a clock valid signal to control the clock gating circuit 2 to turn on.

As will be understood in conjunction with fig. 3 and 13, the line synchronization signal hsy is kept low during the vertical blanking period, and the pixel count signal hcnt (i.e., the count value) of the counter 131 is kept at htotal. Accordingly, the count enable signal hcnt-en and the clock enable signal clk-en are both low in the vertical blanking period.

In summary, the display driving method provided in the embodiments of the present disclosure may specifically be performed as follows:

in step S100, a data valid synchronization signal endi, a row synchronization signal hsy, and a field synchronization signal vsy are received.

In step S200, a clock enable signal clk-en is generated from the data valid synchronization signal endi, the row synchronization signal hsy, and the field synchronization signal vsy; wherein the clock enable signal clk-en comprises: a clock sleep signal in a signal blanking period, and a clock active signal in a non-signal blanking period.

The signal blanking period includes, for example, a line blanking period and/or a vertical blanking period.

Illustratively, the clock sleep signal is low and the clock active signal is high.

For example, step S200 may include steps S210 to S230.

In step S210, a count enable signal hcnt-en is generated according to the row synchronization signal hsy and the pixel count signal hcnt fed back in real time.

For example, step S210 may include steps S211 to S213.

In step S211, the total pixel count htotal of one row of pixels is acquired. That is, the total pixel count htotal of one row of pixels may be input to the second input terminal of the enable control module 11 smaller than the comparator 111.

In step S212, it is determined whether the pixel count signal hcnt is smaller than the total pixel count htotal, so as to output a first level when the pixel count signal hcnt is smaller than the total pixel count htotal, and output a second level when the pixel count signal hcnt is greater than or equal to the total pixel count htotal. That is, the pixel count signal hcnt fed back in real time from the output terminal Q of the counter 131 may be input to the first input terminal smaller than the comparator 111 in the enable control module 11, so that the comparison result is output smaller than the comparator 111.

Illustratively, the first level is a high level and the second level is a low level.

In step S213, the row synchronization signal hsy and the first level or the second level are ored to obtain a first or logic signal as the count enable signal hcnt-en. That is, the first level or the second level may be input to the first input terminal of the first or gate 112 in the enable control module 11, and the row synchronization signal hsy may be input to the second input terminal of the first or gate 112, so that the first or gate 112 outputs the or operation result as the first or logic signal.

For example, the count enable signal hcnt-en may be at a high level when the pixel count signal hcnt (i.e., the count value) starts counting (is 1) until equal to the number of pixel points corresponding to the effective image width img-width, and at a low level when the pixel count signal hcnt (i.e., the count value) is 0 or greater than the number of pixel points corresponding to the effective image width img-width and less than or equal to the total number of pixel points htotal corresponding to one line of pixels, i.e., at least at the line blanking period and the field blanking period.

In step S220, a count zero signal hcnt-clr is generated based on the data valid sync signal endi, the field sync signal vsy, and the line sync signal hsy.

For example, step S220 may include steps S221 to S223.

In step S221, the data valid synchronization signal endi and the field synchronization signal vsy are ored to obtain a second or logic signal. That is, the data valid synchronization signal endi may be input to the first input terminal of the second or gate 121 in the clear control module 12, and the field synchronization signal vsy may be input to the second input terminal of the second or gate 121, so that the second or gate 121 outputs an or operation result as a second or logic signal.

In step S222, the line synchronization signal hsy is inverted to obtain an inverted signal. That is, the row synchronization signal hsy can be input to the input of the inverter 122 in the clear control module 12 to obtain the inverted signal of the row synchronization signal hsy.

In step S223, the second or logic signal and the inverted signal are subjected to an and operation, so as to obtain an and logic signal as a count zero signal hcnt-clr. That is, a second or logic signal may be input to the first input terminal of the and gate 123 in the clear control module 12, and an inverted signal of the row synchronization signal hsy may be input to the second input terminal of the and gate 123, so that the and gate 123 outputs the and operation result as the count clear signal hcnt-clr.

In step S230, a pixel count signal hcnt is generated from the clock signal clki, the count enable signal hcnt-en, and the count clear signal hcnt-clr. That is, the counter 131 may be enabled to input the count enable signal hcnt-EN to the enable input EN of the counter 131 in the blanking counting circuit 13, the count clear signal hcnt-CLR to the clear input CLR of the counter 131, and the clock signal clk to the clock input CK of the counter 131 to start the accumulation count when the row synchronization signal hsy rises, stop the count when the pixel count signal hcnt (i.e., the count value) is equal to the total pixel count htotal corresponding to one row of pixels, and clear the counter 131 when the data valid synchronization signal endi rises to the rising edge of the row synchronization signal hsy, thereby enabling the output Q of the counter 131 to output the pixel count signal hcnt.

In step S230, the clock enable signal clk-en is generated based on the pixel count signal hcnt. That is, the pixel count signal hcnt may be input to the first input terminal of the comparator 132 or less in the blanking count circuit 13, and the number of pixels corresponding to the effective image width img-width may be input to the second input terminal of the comparator 132 or less, so that the comparator 132 outputs the comparison result as the clock enable signal clk-en or less.

Illustratively, when the pixel count signal hcnt is less than or equal to the number of pixel points corresponding to the effective image width img-width, the comparator 132 outputs a high level; when the pixel count signal hcnt is greater than the number of pixels corresponding to the effective image width img-width, the comparator 132 outputs a low level.

Further by way of example, the clock enable signal clk-en may be low during the horizontal blanking period and/or the vertical blanking period, and high when the rising edge of the data valid synchronization signal endi is up to the valid image width img-width; the low level corresponds to a clock sleep signal, and the high level corresponds to a clock active signal.

In step S300, a clock signal clki is received and is controlled to sleep in response to the clock sleep signal and is controlled to operate in response to the clock enable signal.

For example, when the clock enable signal clk-en is a clock sleep signal, the clock gating circuit 2 may be controlled to turn off to stop outputting the clock signal clk. When the clock enable signal clk-en is a clock enable signal, the clock gating circuit 2 may be controlled to turn on to maintain the output clock signal clk.

For example, the clock signal clk output or stopped from being output by the clock gating circuit 2 may be the clock signal clki originally input, or the clock signal clk output after the clock gating circuit 2 converts the clock signal clki originally input.

In summary, the display driving circuit and the display driving method provided in the embodiments of the present disclosure may realize low power consumption of the display device based on a digital circuit (e.g., a blanking counting circuit), and have a simple structure and are easy for mass production.

The embodiments of the present disclosure also provide a display device including the display driving circuit in some of the embodiments above. The display driving method and the display driving circuit have technical advantages, and the display device also has the technical advantages, which are not described in detail herein.

The display device is an OLED display device, for example, and may be applied to a portable device.

Illustratively, the display device includes: consumer electronic terminals such as sighting telescope, AR/VR/XR, electronic paper, mobile phone, tablet computer, television, display, notebook computer or navigator.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The foregoing examples represent only a few embodiments of the present disclosure, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that variations and modifications can be made by those skilled in the art without departing from the spirit of the disclosure, which are within the scope of the disclosure.

Claims (10)

1. A display driving circuit, comprising:

a synchronization control circuit configured to: receiving a data effective synchronous signal, a line synchronous signal and a field synchronous signal, and generating a clock enabling signal according to the data effective synchronous signal, the line synchronous signal and the field synchronous signal; wherein the clock enable signal comprises: a clock sleep signal in a signal blanking period and a clock valid signal in a non-signal blanking period;

a clock gating circuit, coupled to the synchronization control circuit, configured to: and receiving a clock signal and the clock enabling signal to control the clock signal to sleep in response to the clock sleep signal and to control the clock signal to work in response to the clock valid signal.

2. The display drive circuit according to claim 1, wherein the synchronization control circuit includes:

an enable control module configured to: receiving the row synchronization signal and the pixel counting signal, and generating a counting enabling signal;

a clear control module configured to: receiving the data effective synchronous signal, the field synchronous signal and the line synchronous signal, and generating a count zero clearing signal according to the data effective synchronous signal, the field synchronous signal and the line synchronous signal;

and the blanking counting circuit is respectively connected with the enabling control module, the zero clearing control module and the clock gating circuit and is configured to: the clock signal, the count enable signal and the count clear signal are received, the pixel count signal is generated according to the clock signal, the count enable signal and the count clear signal, and the clock enable signal is generated based on the pixel count signal.

3. The display driver circuit of claim 2, wherein the enable control module comprises: less than the comparator and the first or gate; wherein,

the first input end smaller than the comparator is connected with the blanking counting circuit and is used for receiving the pixel counting signal; the second input end smaller than the comparator is used for inputting the total pixel number of one row of pixels;

the first input end of the first OR gate is connected with the output end of the smaller comparator; the second input end of the first OR gate is used for receiving the row synchronous signal; the output end of the first OR gate is connected with the enabling input end of the blanking counting circuit and is used for outputting the counting enabling signal to the blanking counting circuit.

4. The display driver circuit of claim 2, wherein the clear control module comprises: a second or gate, an inverter, and an and gate; wherein,

the first input end of the second OR gate is used for receiving the data valid synchronous signal; the second input end of the second OR gate is used for receiving the field synchronous signal; the input end of the inverter is used for receiving the row synchronous signal;

the first input end of the AND gate is connected with the output end of the second OR gate; the second input end of the AND gate is connected with the output end of the inverter; the output end of the AND gate is connected with the zero clearing input end of the blanking counting circuit and is used for outputting the counting zero clearing signal to the blanking counting circuit.

5. The display driving circuit according to any one of claims 2 to 4, wherein the blanking counting circuit includes a counter and a comparator or less; wherein,

the enabling input end of the counter is connected with the enabling control module and is used for receiving the counting enabling signal; the zero clearing input end of the counter is connected with the zero clearing control module and is used for receiving the counting zero clearing signal; the clock input end of the counter is used for receiving the clock signal; the output end of the counter is used for outputting the pixel counting signal;

the first input end of the comparator which is smaller than or equal to the first input end is connected with the output end of the counter; the second input end of the comparator is used for receiving the number of pixel points corresponding to the effective image width; the output end of the comparator is connected with the clock gating circuit and is used for outputting the clock enabling signal to the clock gating circuit.

6. A display driving method, characterized by comprising:

receiving a data valid synchronous signal, a line synchronous signal and a field synchronous signal;

generating a clock enable signal according to the data valid synchronization signal, the row synchronization signal and the field synchronization signal; wherein the clock enable signal comprises: a clock sleep signal in a signal blanking period and a clock valid signal in a non-signal blanking period;

and receiving a clock signal, controlling the clock signal to sleep in response to the clock sleep signal, and controlling the clock signal to work in response to the clock valid signal.

7. The display driving method according to claim 6, wherein the generating a clock enable signal from the data valid synchronization signal, the row synchronization signal, and the field synchronization signal includes:

generating a counting enabling signal according to the line synchronizing signal and the pixel counting signal fed back in real time;

generating a count zero clearing signal according to the data effective synchronous signal, the field synchronous signal and the line synchronous signal;

the pixel count signal is generated from the clock signal, the count enable signal, and the count clear signal, and the clock enable signal is generated based on the pixel count signal.

8. The display driving method according to claim 7, wherein generating a count enable signal according to the line synchronization signal and a pixel count signal fed back in real time comprises:

acquiring the total pixel number of a row of pixels;

judging whether the pixel counting signal is smaller than the total pixel number or not, outputting a first level when the pixel counting signal is smaller than the total pixel number, and outputting a second level when the pixel counting signal is larger than or equal to the total pixel number;

and performing OR operation on the row synchronous signal and the first level or the second level to obtain a first OR logic signal as the counting enabling signal.

9. The display driving method according to claim 7, wherein the generating a count clear signal according to the data valid synchronization signal, the field synchronization signal, and the line synchronization signal includes:

performing OR operation on the data effective synchronous signal and the field synchronous signal to obtain a second OR logic signal;

performing inversion operation on the line synchronization signal to obtain an inversion signal;

and performing an AND operation on the second OR logic signal and the inversion signal to obtain an AND logic signal as the count zero clearing signal.

10. A display device comprising the display driving circuit according to any one of claims 1 to 5.