CN108845517A - Anticoincidence circuit and pulse signal detection circuit - Google Patents
Anticoincidence circuit and pulse signal detection circuit Download PDFInfo
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- CN108845517A CN108845517A CN201810384199.0A CN201810384199A CN108845517A CN 108845517 A CN108845517 A CN 108845517A CN 201810384199 A CN201810384199 A CN 201810384199A CN 108845517 A CN108845517 A CN 108845517A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/21—Pc I-O input output
- G05B2219/21119—Circuit for signal adaption, voltage level shift, filter noise
Abstract
A kind of anticoincidence circuit and pulse signal detection circuit, the anticoincidence circuit include：The anticoincidence logic control element (11) and pulse signal realized on programmable logic device (3) generate unit (12)；The anticoincidence logic control element (11), with the first input end to receive the first examination pulse (VL) and the second input terminal to receive the second examination pulse (VH), the anticoincidence logic control element screens pulse (VL) and the second examination pulse (VH) to based on the received first and generates and export control signal；The pulse signal generates unit (12) and connect with the anticoincidence logic control element (11), and the pulse signal generates unit (12) and generates pulse signal to respond the control signal.
Description
Technical field
The present invention relates to pulse signal detection technical fields more particularly to a kind of anticoincidence circuit and pulse signal to examine
Slowdown monitoring circuit.
Background technique
In nuclear electronics field, the pulse signal exported to detector is needed to detect.Pulse signal is pressed amplitude by it
Size classified and record the number of every class signal.It is usually used in analyzing the output signal of ray detector, measures ray
Power spectrum.In addition to nuclear electronics, this detection technique is but also widely used for the fields such as consumer electronics, biomonioring and nuclear medicine
In, have certain technological value.
In nuclear electronics, there are many correlations in occurring simultaneously or occurring in short time interval and have in causal relation
Event is known as meeting event.The electronic system that measurement meets event is known as meeting system；Opposite, some measurements will exclude to accord with
Conjunction event, this system are known as anticoincidence system.Anticoincidence circuit can help to realize the classification and Detection of pulse signal.
However, component is various in current anticoincidence circuit, each component needs to be routed connection on PCB, excessively
Component increase the area of PCB so that system cost is high；In addition, global reliability is not high, the use of a variety of components increases
The unstability of system is added, the more piece PCB transmission line between multiple components be easy to cause signal distortion, it is also possible to which there are sides
Along the problem of being overlapped, so that occurring race hazard problem when edging trigger, system malfunction is caused.
Summary of the invention
The present invention provides a kind of anticoincidence circuit and pulse signal detection circuit, can reduce cost, improves reliability.
According to a first aspect of the embodiments of the present invention, a kind of anticoincidence circuit includes：It is real on programmable logic device (3)
Existing anticoincidence logic control element and pulse signal generate unit；
The anticoincidence logic control element has to receive the first input end of the first examination pulse and to receive
Second screens the second input terminal of pulse, and the anticoincidence logic control element screens pulse and the to based on the received first
Two screen pulses and generate and export control signal；
The pulse signal generates unit and connect with the anticoincidence logic control element, and the pulse signal generates unit
Pulse signal is generated to respond the control signal.
According to a first aspect of the embodiments of the present invention, the anticoincidence logic control element includes finite state machine, according to
It is described first screen pulse and second screen pulse level change and generating state jumps.
According to a first aspect of the embodiments of the present invention, the finite state machine is screened pulse described first and is become from high level
For low level and when the corresponding second examination pulse persistance is low level, the state for exporting the control signal is jumped to.
According to a first aspect of the embodiments of the present invention, the state that jumps of the finite state machine includes state ID LE, state
S0, state S1, state S2；
Under the state ID LE, the first examination pulse and the second examination pulse are low level, the mark of output
Remember that position is 0, jumps to the state S0 when the first examination pulse becomes high level from low level；
Under the state S0, the first examination pulse is high level, the second examination pulse is low level, output
Marker bit is 0, jumps to the state S1 when the first examination pulse becomes low level from high level, and described second
It screens pulse and jumps to the state S2 when becoming high level from low level；
Under the state S1, the first examination pulse and the second examination pulse are low level, the label of output
Position is 1, as the control signal, jumps to the state ID LE later；
Under the state S2, the first examination pulse and the second examination pulse are high level, the label of output
Position is 0, jumps to the state ID LE when the first examination pulse becomes low level from high level.
According to a first aspect of the embodiments of the present invention, further include clock unit, connect the programmable logic device when
Clock input terminal, to export clock signal, the clock signal can carry out timing control to the finite state machine.
According to a first aspect of the embodiments of the present invention, further include reset unit, connect answering for the programmable logic device
Position end, to output reset signal, the reset signal can carry out state reset to finite state machine.
According to a first aspect of the embodiments of the present invention, the programmable logic device includes FPGA.
According to a first aspect of the embodiments of the present invention, a kind of pulse signal detection circuit, including：Discriminator circuit, counter
And the anticoincidence circuit as described in any one of previous embodiment；
The discriminator circuit, to receive input signal, and by the input signal respectively with the first reference voltage and
Described first is exported after two reference voltages screen pulse and second and screen pulse, wherein first reference voltage and the
The voltage value of two reference voltages is different；
The anticoincidence circuit connects the discriminator circuit and the counter, to receive the discriminator circuit output
First, which screens pulse and second, screens pulse；
The counter is counted to the pulse signal exported to the anticoincidence circuit.
According to a first aspect of the embodiments of the present invention, the counter is realized in the programmable logic device.
It according to a first aspect of the embodiments of the present invention, further include signal conditioning circuit, before being connected to the discriminator circuit
End, to output after carrying out signal condition to the input signal into the discriminator circuit.
According to a first aspect of the embodiments of the present invention, the discriminator circuit includes the first discriminator and the second discriminator；
Two input terminals of first discriminator receive the input signal and first reference voltage respectively, in institute
When stating input signal higher than first reference voltage, pulse is screened in the output end output described first of first discriminator；
Two input terminals of second discriminator receive the input signal and second reference voltage respectively, in institute
When stating input signal higher than second reference voltage, pulse is screened in the output end output described second of second discriminator.
It according to a first aspect of the embodiments of the present invention, further include reference voltage circuit, to export described first with reference to electricity
Pressure and the second reference voltage.
After adopting the above technical scheme, the present invention has the advantages that compared with prior art：
It since anticoincidence logic control element and pulse signal generate unit is realized in programmable logic device,
Without numerous components, the area of circuit board is saved, reduces the cost of implementation of anticoincidence circuit；Moreover, because without passing through
PCB transmission line carries out component connection, improves the stability of system, is realized by programmable logic device, will not be because of first device
Part parameter differences and influence signal conformance, reliability is higher；
Based on programmable logic device, anticoincidence logic control element is realized by finite state machine, different first
Screen pulse and second examination pulse pair answer different states, can according to first screen pulse and second screen pulse variation come
Realize jumping for these states, finite state machine is realized under corresponding state and to the signal progress logical process for inputting it
Corresponding output can reduce the cost of realization with the pulse signal expected, and due to the programmable and spirit of finite state machine
Activity can further improve the reliability of system by temporal constraint；
Anticoincidence circuit and counter are realized in programmable logic device, so that a programmable logic device has
The dual function of anticoincidence circuit needed for pulse signal detection circuit and counter, has saved cost, improves the utilization of resources
Rate.
Detailed description of the invention
Fig. 1 is the structural block diagram of the anticoincidence circuit of one embodiment of the invention；
Fig. 2 is the structural block diagram of the pulse signal detection circuit of one embodiment of the invention；
Fig. 3 is the structural block diagram of the pulse signal detection circuit of another embodiment of the present invention；
Fig. 4 is the waveform diagram of the input signal of one embodiment of the invention；
Fig. 5 a is the structural block diagram of the discriminator of one embodiment of the invention；
Fig. 5 b is input-output wave shape relation schematic diagram of the signal of one embodiment of the invention on discriminator；
Fig. 6 is the waveform diagram that function is realized needed for anticoincidence system；
Fig. 7 is that the anticoincidence circuit of one embodiment of the invention embodies the waveform diagram of function；
Fig. 8 is the intermediatenesses machine of the present invention of the finite state machine of one embodiment of the invention；
Fig. 9 is that the pulse signal of one embodiment of the invention generates the workflow schematic diagram of unit.
Specific embodiment
Example embodiments are described in detail here, and the example is illustrated in the accompanying drawings.Following description is related to
When attached drawing, unless otherwise indicated, the same numbers in different drawings indicate the same or similar elements.Following exemplary embodiment
Described in embodiment do not represent all embodiments consistented with the present invention.On the contrary, they be only with it is such as appended
The example of device and method being described in detail in claims, some aspects of the invention are consistent.
It is only to be not intended to limit the invention merely for for the purpose of describing particular embodiments in terminology used in the present invention.
It is also intended in the present invention and the "an" of singular used in the attached claims, " described " and "the" including majority
Form, unless the context clearly indicates other meaning.It is also understood that term "and/or" used herein refers to and wraps
It may be combined containing one or more associated any or all of project listed.
It should be appreciated that " first " " second " and similar word used in present specification and claims
It is not offered as any sequence, quantity or importance, and is used only to distinguish different component parts.Equally, "one" or
The similar word such as " one " does not indicate that quantity limits yet, but indicates that there are at least one.Unless otherwise noted, " front ", " after
The similar word such as portion ", " lower part " and/or " top " is not limited to a position or a kind of sky only to facilitate explanation
Between orient.The similar word such as " comprising " or "comprising" means to appear in element or object before " comprising " or "comprising"
Cover the element for appearing in " comprising " or "comprising" presented hereinafter or object and its equivalent, it is not excluded that other elements or
Object." connection " either the similar word such as " connected " is not limited to physics or mechanical connection, and may include
Electrical connection, it is either direct or indirect.
In one embodiment, referring to Fig. 1, a kind of anticoincidence circuit may include：It is realized in programmable logic device 3
Anticoincidence logic control element 11 and pulse signal generate unit 12.
Anticoincidence logic control element 11 has to receive the first input end of the first examination pulse VL and to receive
Second screen pulse VH the second input terminal, anticoincidence logic control element 11 to based on the received first screen pulse VL and
Second screens pulse VH and generates and export control signal.
It is laggard that first examination pulse VL and the second examination pulse VH can be input to discriminator circuit by same input signal
What row generated after screening, in anticoincidence circuit, the two pulses only need to be received, pulse VL and second is screened to first and discriminates
Other pulse VH is judged and is screened.Anticoincidence logic control element 11 screens pulse to first by the control logic of itself
The examination of VL and second pulse VH is handled, and required control signal is exported under its control logic.Anticoincidence logic control list
The control logic of member can be depending on the functional requirement that need to be realized.
Pulse signal generates unit 12 and connect with anticoincidence logic control element 11, and pulse signal generates unit 12 to sound
Signal should be controlled and generate pulse signal.Anticoincidence logic control element 11 is meeting condition according to itself control logic
In the case of can just export control signal, at this time pulse signal generate unit according to control signal and generate a pulse signal, this arteries and veins
Rushing signal can be shown that the generation of anticoincidence event of anticoincidence logic control element 11, as a result, can be further to the pulse signal
The pulse signal for generating unit is counted, and can realize the statistics of this anticoincidence event, is also achieved that and is discriminated to generation first
Other pulse VL and second screens the classification and Detection of the input pulse of pulse VH.
Realize that anticoincidence logic control element 11 and pulse signal generate the side of unit 12 by programmable logic device 3
Formula can generate unit 12 to anticoincidence logic control element 11 and pulse signal by way of hardware programming and carry out accordingly
Hardware description, be then cured in programmable logic device.
It is the reality in programmable logic device 3 since anticoincidence logic control element 11 and pulse signal generate unit 12
Existing, numerous components are not necessarily to, the area of circuit board is saved, reduces the cost of implementation of anticoincidence circuit；Moreover, because being not necessarily to
Component connection is carried out by PCB transmission line, the stability of system is improved, is realized by programmable logic device, Bu Huiyin
Component parameter difference and influence signal conformance, reliability is higher.
Referring to Fig. 2, in one embodiment, the pulse signal of anticoincidence circuit can realize pulsimeter by counter 2
Number statistics, to realize the classification and Detection to input signal.Pulse signal generates unit 12 and connect with counter 2, and pulse is believed
Number output is to counter 12.
The waveform of input signal for example may refer to Fig. 4, be a narrow pulse signal.It is appreciated that input signal not
Certain conditioning directly can be carried out to input signal in use, can according to need, certainly, the conditioning of signal can't change defeated
Enter the essential information of signal.
Referring to Fig. 5 a and 5b, thus it is shown that a discriminator and its input and output situation, signal viAs input signal, letter
Number voAs output signal.The essence of discriminator is comparison circuit, by input signal viWith reference voltage VTIt is compared, compares
As a result it is indicated with low and high level, input signal can connect the positive input terminal or negative input end in discriminator.In order to express easily, false
If connecing input signal in its positive input terminal, reference voltage VTIt connects in its negative input end, in signal viHigher than reference voltage VTPortion
There is signal v in brancho(high level) output, remaining time do not export and (keep low level).
It is different in the reference voltage of two discriminators (being referred to as upper discriminator and lower discriminator in the present embodiment)
In the case of, same input signal is inputted, the output signal of the two is different, can be according to anticoincidence with specific reference to the value of voltage
Depending on the value range of the input signal detected needed for circuit.Referring to Fig. 6, the function realized needed for anticoincidence circuit is shown
Can, it is V in the signal of inputi(t) under, the signal of corresponding required output is Vo(t).It is supplied to common defeated of upper and lower discriminator
Entering signal is Vi(t), with the first reference voltage VLWith the second reference voltage VHComparison under, only peak segment be located at first ginseng
Examine voltage VLWith the second reference voltage VHBetween pulse, just have pulse output after anticoincidence circuit.It can from Fig. 6
Out, Vi(t) there are three peak segments for signal tool：
For peak value of pulse section a, Vi(t)<VL, the output of upper and lower discriminator is low level, Vo(t) defeated without effective impulse
Out；
For peak value of pulse section b, VL<Vi(t)<VH, lower discriminator output high level, upper discriminator output low level, this
V under parto(t) effective impulse is exported；Counter can be to Vo(t) effective impulse in is counted；
And for peak value of pulse section c, Vi(t)>VH, upper and lower discriminator has high level output, Vo(t) defeated without effective impulse
Out.
Referring to Fig. 7, the output of upper and lower discriminator is respectively the second waveform for screening pulse VH, the first examination pulse VL, instead
The waveform that coincident circuit output is signal Vo.During being high for the first examination pulse VL, if the second examination pulse VH is also high
Level is then exported without effective impulse；If first screens pulse VL between high period, the second examination pulse VH is always maintained at low electricity
It is flat, then there is an effective impulse output.Here the wave of the first examination pulse VL (or second examination pulse VH) and output signal Vo
Shape is in phase without particular/special requirement.
In brief, the function of realizing needed for anticoincidence circuit is to be lower than the second reference voltage V input signal occursH
And it is higher than the first reference voltage VLIn the case where, export an effective impulse, and input signal and the second reference voltage VHComparison
As a result pulse VH can be screened by received second to embody, input signal and the first reference voltage VLComparison result can be by connecing
First received screens pulse VL and embodies.
In one embodiment, anticoincidence logic control element 11 includes finite state machine.Finite state machine can be according to
One examination pulse VL and second screens the level change of pulse VH and generating state jumps.Finite state machine is in programmable logic
The timing application of logic circuit module realized in device 3.
Based on programmable logic device 3, anticoincidence logic control element 11 is realized by finite state machine, different is defeated
Enter signal and correspond to different states, can realize these states according to the variation of the first examination pulse VL and the second examination pulse VH
Jump, finite state machine realizes corresponding output and carrying out logical process to the signal for inputting it under corresponding state,
With the pulse signal expected, the cost of realization can be reduced, and due to the programmable and flexibility of finite state machine, can be passed through
Temporal constraint further improves the reliability of system.
Further, finite state machine becomes low level from high level in the first examination pulse VL and corresponding second screens
When pulse VH is continuously low level, the state of output control signal is jumped to.One pulse of input signal has corresponding
One examination pulse VL and the second examination pulse VH namely the first examination pulse VL and the second examination pulse VH is to correspond to occur,
State is high level or low level.When the first examination pulse VL from high level becomes low level, and first screen pulse VL herein
Second examination pulse VH corresponding to period is continuously low level, illustrates input signal occurred lower than the second reference voltage VHAnd
Higher than the first reference voltage VLThe case where, the state for first jumping to output control signal at this time carries out the output of control signal.
Preferably, referring to Fig. 8, the state that jumps of finite state machine may include state ID LE, state S0, state S1, shape
State S2.Marker bit is indicated with FLAG.
Under state ID LE, it is low level, the marker bit FLAG of output that the first examination pulse VL and second, which screens pulse VH,
It is 0, when the first examination pulse VL becomes high level from low level, shows that the pulse for having amplitude to be greater than the first reference voltage is arrived
Come, jumps to state S0；State ID LE be idle state, can be after programmable logic device powers on automatically into shape
State, can also be automatically into state ID LE after system reset；
Under state S0, the first examination pulse VL is high level, the second examination pulse VH is low level, shows impulse amplitude one
Straight between the first reference voltage and the second reference voltage, the marker bit FLAG of output is 0, screens pulse VL from height first
Level becomes jumping to state S1 when low level, and when the second examination pulse VH becomes high level from low level, show pulse
Amplitude be greater than the second reference voltage, jump to state S2；
Under state S1, it is low level that the first examination pulse VL and second, which screens pulse VH, and the marker bit FLAG of output is
1, as control signal, state ID LE is jumped to later；It, can when next clock signal arrives after system enters state S1
Unconditionally it is transferred to state ID LE
Under state S2, it is high level that the first examination pulse VL and second, which screens pulse VH, and the marker bit FLAG of output is
0, when the first examination pulse VL becomes low level from high level, shows that a pulse experience is completed, jump to state ID LE, weight
New status condition is newly waited to generate.
It, will for pulse of the amplitude between the first reference voltage and the second reference voltage for anticoincidence logic
Effective marker bit FLAG can be generated.In order to export effective impulse, in programmable logic device 3, need to design an independence
Pulse signal generate unit 12 export a high level pulse in marker bit FLAG=1.
In one embodiment, anticoincidence circuit can also include clock unit.With continued reference to Fig. 2, clock unit connection
The input end of clock of programmable logic device 3, to export clock signal clk, clock signal clk can carry out finite state machine
Timing control can also be used to realize other function certainly.When clock signal clk can be used as the work of programmable logic device
Clock.
In one embodiment, anticoincidence circuit can also include reset unit.With continued reference to Fig. 2, reset unit connection
The reset terminal of programmable logic device 3, to output reset signal RST, reset signal RST can carry out state to finite state machine
It resets.
Realize that first screens pulse VL, the second examination pulse VH, clock signal clk and reset signal by finite state machine
The logical operation of RST, the marker bit FLAG generated under corresponding state generate unit generation pulse signal to pulse signal.
Preferably, the pulsewidth that pulse signal generates the pulse signal that unit 12 exports can pass through programmable logic device 3
In counter determine, referring to Fig. 9, define a Vo ' variable, if after detecting the mark position FLAG 1, Vo ' is set 1, and
Start the counter in programmable logic device 3, clock signal clk is counted.It, will after counting arrival certain threshold value
Vo ' sets 0, counter O reset.The pulse width of pulse signal is determined by count threshold and the clock cycle product of clock signal clk
It is fixed.
Preferably, programmable logic device 3 may include (Field-Programmable Gate Array, the scene FPGA
Programmable gate array).It is certainly not limited to this, can also be other programmable logic device.
In one embodiment, referring to Fig. 2 and Fig. 3, a kind of pulse signal detection circuit may include：Discriminator circuit, meter
The number devices 2 and anticoincidence circuit 1 as described in any one of previous embodiment, the particular content about anticoincidence circuit 1 can be with
Referring to the description in previous embodiment, details are not described herein.
Discriminator circuit to receive input signal, and by input signal respectively with the first reference voltage and the second reference voltage
Output first screens pulse VL and second and screens pulse VH more afterwards.Wherein, the electricity of the first reference voltage and the second reference voltage
Pressure value is different；For example, the voltage value of the first reference voltage can be lower than the voltage value of the second reference voltage.
Anticoincidence circuit 1 connects discriminator circuit and counter 2, and first to receive discriminator circuit output screens pulse VL
Pulse VH is screened with second.Counter 2 is counted to the pulse signal exported to anticoincidence circuit 1.Pulse signal conduct
The input signal of counter 2, when there is a pulse signal, counter 2 is just counted, such as cumulative one.
Preferably, counter 2 is realized in programmable logic device 3.The programmable logic device 3 of the present embodiment equally may be used
To include FPGA, as shown in Fig. 2, can be counter 2 and anticoincidence circuit 1 is integrated in one piece of programmable logic device 3.
Anticoincidence circuit 1 and counter 2 are realized in programmable logic device, so that a programmable logic device 3
The dual function of anticoincidence circuit 1 and counter 2, has saved cost needed for having pulse signal detection circuit, improves money
Source utilization rate.
It is counter 2 after anticoincidence circuit, the counter in programmable logic device 3 can be called, to the feelings of Vo=1
Condition is counted, and count value is externally exported.The unit for being used to export shown in Fig. 3 is display unit, to count value etc.
Information is shown, this is certainly not limited to.
Pulse signal shown in Fig. 9 generates the counter 2 after the counter and anticoincidence circuit that unit is called,
It can be the different counter modules in programmable logic device 3.
In one embodiment, referring to Fig. 3, pulse signal detection circuit can also include signal conditioning circuit 5.Signal tune
Reason circuit 5 is connected to the front end of discriminator circuit, to output after carrying out signal condition to input signal into discriminator circuit.Signal
Conditioning circuit 5 carries out pulse conditioning such as may include current-voltage conversion circuit, pre-amplification circuit, to input signal,
So that its input requirements for being suitable for late-class circuit, the waveform of waveform and input signal that signal conditioning circuit 5 exports keeps one
It causes.
Preferably, with continued reference to Fig. 3, discriminator circuit may include the first discriminator 41 and the second discriminator 42.First discriminates
Other device 41 and the second discriminator 42 can the discriminator as shown in Fig. 5 a, the reference voltage being only arranged is different.
Two input terminals of the first discriminator 41 receive input signal and the first reference voltage respectively, are higher than in input signal
When the first reference voltage, pulse VL is screened in the output end output first of the first discriminator 41.
Two input terminals of the second discriminator 42 receive input signal and the second reference voltage respectively, are higher than in input signal
When the second reference voltage, pulse VH is screened in the output end output second of the second discriminator 42.
Preferably, with continued reference to Fig. 3, pulse signal detection circuit can also include reference voltage circuit 6.Reference voltage electricity
Road 6, to export the first reference voltage and the second reference voltage.Reference voltage circuit 6 is that the first discriminator 41 and second is screened
Device 42 mentions reference voltage for comparison, and high stability can divide to obtain by divider resistance to reference voltage, or can be with
It is realized by digital analog converter, specific unlimited, value can be set.
The above is only presently preferred embodiments of the present invention, not does limitation in any form to the present invention, though
So the present invention has been disclosed as a preferred embodiment, and however, it is not intended to limit the invention, any technology people for being familiar with this profession
Member, in the range of not departing from technical solution of the present invention, when the technology contents using the disclosure above are modified or are repaired
Decorations are the equivalent embodiment of equivalent variations, but anything that does not depart from the technical scheme of the invention content, technology according to the present invention are real
Matter any simple modification, equivalent change and modification to the above embodiments, still fall within the range of technical solution of the present invention
It is interior.
This patent document disclosure includes material protected by copyright.The copyright is all for copyright holder.Copyright
Owner does not oppose the patent document in the presence of anyone replicates the proce's-verbal of Patent&Trademark Office and archives or should
Patent discloses.
Claims (12)
1. a kind of anticoincidence circuit, which is characterized in that including：The anticoincidence logic control list realized in programmable logic device
Member and pulse signal generate unit；
The anticoincidence logic control element has to receive the first input end of the first examination pulse and to receive second
The second input terminal of pulse is screened, the anticoincidence logic control element is screened pulse and second to based on the received first and discriminated
Other pulse and generate and export control signal；
The pulse signal generates unit and connect with the anticoincidence logic control element, the pulse signal generation unit to
It responds the control signal and generates pulse signal.
2. anticoincidence circuit as described in claim 1, which is characterized in that the anticoincidence logic control element includes limited shape
State machine, screens the level change of pulse according to the first examination pulse and second and generating state jumps.
3. anticoincidence circuit as claimed in claim 2, which is characterized in that the finite state machine screens pulse described first
From high level become low level and corresponding described second to screen pulse persistance be low level when, jump to the output control and believe
Number state.
4. anticoincidence circuit as claimed in claim 3, which is characterized in that the state that jumps of the finite state machine includes state
IDLE, state S0, state S1, state S2；
Under the state ID LE, the first examination pulse and the second examination pulse are low level, the marker bit of output
It is 0, jumps to the state S0 when the first examination pulse becomes high level from low level；
Under the state S0, the first examination pulse is high level, the second examination pulse is low level, the label of output
Position is 0, jumps to the state S1 when the first examination pulse becomes low level from high level, and is screened described second
Pulse jumps to the state S2 when becoming high level from low level；
Under the state S1, the first examination pulse and the second examination pulse are low level, and the marker bit of output is
1, as the control signal, the state ID LE is jumped to later；
Under the state S2, the first examination pulse and the second examination pulse are high level, and the marker bit of output is
0, the state ID LE is jumped to when the first examination pulse becomes low level from high level.
5. anticoincidence circuit as claimed in claim 2, which is characterized in that further include clock unit, connect described may be programmed and patrol
The input end of clock for collecting device, to export clock signal, the clock signal can carry out timing control to the finite state machine
System.
6. anticoincidence circuit as claimed in claim 2, which is characterized in that further include reset unit, connect described may be programmed and patrol
The reset terminal for collecting device, to output reset signal, the reset signal (RST) can carry out state reset to finite state machine.
7. anticoincidence circuit as described in claim 1, which is characterized in that the programmable logic device includes FPGA.
8. a kind of pulse signal detection circuit, which is characterized in that including：Appoint in discriminator circuit, counter and such as claim 1-7
Anticoincidence circuit described in meaning one；
The discriminator circuit is joined with the first reference voltage and second respectively to receive input signal, and by the input signal
The first examination pulse and the second examination pulse are exported after examining voltage, wherein first reference voltage and the second ginseng
The voltage value for examining voltage is different；
The anticoincidence circuit connects the discriminator circuit and the counter, to receive the first of the discriminator circuit output
It screens pulse and second and screens pulse；
The counter is counted to the pulse signal exported to the anticoincidence circuit.
9. pulse signal detection circuit as claimed in claim 8, which is characterized in that the counter is in the programmable logic
It is realized on device.
10. pulse signal detection circuit as claimed in claim 8, which is characterized in that further include signal conditioning circuit, be connected to
The front end of the discriminator circuit, to output after carrying out signal condition to the input signal into the discriminator circuit.
11. pulse signal detection circuit as claimed in claim 8, which is characterized in that the discriminator circuit includes the first examination
Device and the second discriminator；
Two input terminals of first discriminator receive the input signal and first reference voltage respectively, described defeated
When entering signal higher than first reference voltage, pulse is screened in the output end output described first of first discriminator；
Two input terminals of second discriminator receive the input signal and second reference voltage respectively, described defeated
When entering signal higher than second reference voltage, pulse is screened in the output end output described second of second discriminator.
12. pulse signal detection circuit as claimed in claim 8, which is characterized in that further include reference voltage circuit, to defeated
First reference voltage and the second reference voltage out.
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